DAC芯片TLC5620verilog代码

1、实用标准文案DAC 芯片 TLC5620 Verilog代码TLC5620是 TI 公司的DA 转换芯片，下面的代码实现的简单的DA 转换功能。说明：数码管1 显示通道，数码管 2 显示 RNG 值，数码管3 和 4 显示 CODE 值。按键1 切换通道，按键2 改变 RNG 值 (0 或 1) ，按键 3 改变 CODE 值，按键4 未使用。/* DAC11位数据输入说明:Bit10:9通道选择00:CHA; 01:CHB; 10:CHC; 11:CHDBit8 RNG 0:参考电压到地1:两倍参考电压到地Bit7:0 DAC转换代码，范围0255.输出电压Vo=REF*(CODE/256)

2、*(1+RNG)*/moduledac(clk,rst_n,文档大全实用标准文案dac_clk,dac_data,dac_load,sw1_n,sw2_n,sw3_n,sw4_n,digit_o,cs);inputclk;/输入时钟50MHzinputrst_n;/复位inputsw1_n,sw2_n,sw3_n,sw4_n;/按键outputdac_clk;/ DAC时钟MAX=1MHzoutputdac_data;/ DAC数据输出outputdac_load;/加载信号/电路图中LDAC 已经接地，因此略去output 7:0 digit_o;/数码管输出output 3:0cs;/数码

3、管片选parameterDAC_Idle = 3'b001,/状态参数DAC_Send = 3'b010,DAC_Store = 3'b100;文档大全实用标准文案/=parameter/ 字模MSK_0= 8'hC0,/ '0'MSK_1= 8'hF9,/ '1'MSK_2= 8'hA4,/ '2'MSK_3= 8'hB0,/ '3'MSK_4= 8'h99,/ '4'MSK_5= 8'h92,/ '5'MSK_6= 8

4、9;h82,/ '6'MSK_7= 8'hF8,/ '7'MSK_8= 8'h80,/ '8'MSK_9= 8'h90,/ '9'MSK_A= 8'h88,/ 'A'MSK_B= 8'h83,/ 'B'MSK_C= 8'hC6,/ 'C'MSK_D= 8'hA1,/ 'D'MSK_E= 8'h86,/ 'E'MSK_F= 8'h8E;/ 'F'/=/*文档大全实用标

5、准文案* 按键部分*/reg 3:0 key_rst;/保存按键前一个状态always (posedge clk or negedge rst_n)if (!rst_n)key_rst <= 4'b1111;else key_rst <= sw4_n,sw3_n,sw2_n,sw1_n;reg3:0 key_rst_r;/保存按键下一个状态always (posedge clk or negedge rst_n)if (!rst_n)key_rst_r <= 4'b1111;else key_rst_r <= key_rst;wire3:0 key_va

6、l = key_rst_r & (key_rst);/检测是否有1 到 0 跳变reg19:0 cnt;/计数器always (posedge clk or negedge rst_n)if (!rst_n)cnt <= 20'd0;文档大全实用标准文案else if (key_val)/有按键按下(由 1 变为 0) 计数器开始计时20mscnt <= 20'd0;elsecnt <= cnt + 1'b1;/去抖动后的按键检测,仍然用两级寄存器reg3:0 low_sw;always (posedge clk or negedge rst_

7、n)if (!rst_n)low_sw <= 4'b1111;else if (cnt = 20'hfffff)/ 20ms后的按键状态锁存到low_sw中low_sw <= sw4_n,sw3_n,sw2_n,sw1_n;reg3:0 low_sw_r;always (posedge clk or negedge rst_n)if (!rst_n)low_sw_r <= 4'b1111;elselow_sw_r <= low_sw;wire3:0 led_ctrl = low_sw_r & (low_sw);reg 10:0 rData

8、;always (posedge clk or negedge rst_n)文档大全实用标准文案if (!rst_n)rData <= 11'd255;else beginif (led_ctrl0 = 1)/ S1键按下rData10:9 <= rData10:9 + 1'b1;/通道切换if (led_ctrl1 = 1)/ S2键按下rData8 <= rData8;/ RNG位变化if (led_ctrl2 = 1)/ S3键按下rData7:0 <= rData7:0 + 8'd8;/ CODE变化end/*/* DAC 控制部分*/r

9、eg 5:0div_cnt;/分频计数器64 分频regdiv_clk;/分频时钟注意不是DAC 输入时钟always (posedge clk or negedge rst_n)if (!rst_n) begindiv_cnt <= 6'd0;文档大全实用标准文案div_clk <= 1'bz;endelse begindiv_cnt <= div_cnt + 1'b1;if (div_cnt = 6'd63)div_clk <= 1'b1;elsediv_clk <= 1'b0;end/*/reg 2:0curr

10、ent_state,next_state;regrDac_load;regbit_cnt_rst;/位计数器复位信号wiredat_send_done;always (posedge clk or negedge rst_n)/时序进程if (!rst_n)current_state <= DAC_Idle;elsecurrent_state <= next_state;always (current_state or div_clk or dat_send_done) begin/组合进程文档大全实用标准文案rDac_load<= 1'b1;bit_cnt_rst

11、<= 1'b0;next_state <= DAC_Idle;case (current_state)DAC_Idle: beginbit_cnt_rst <= 1'b1;next_state <= DAC_Send;/空闲时直接进入send 状态endDAC_Send: beginif (dat_send_done)/数据发送完成next_state <= DAC_Store;elsenext_state <= DAC_Send;endDAC_Store: beginbit_cnt_rst <= 1'b1;rDac_load&

12、lt;= 1'b0;/ LOAD变低进行锁存if (div_clk)next_state <= DAC_Idle;else文档大全实用标准文案next_state <= DAC_Store;endendcaseend/*/reg 4:0 bit_cnt;/位计数器对 div_clk计数always (posedge clk or negedge rst_n) beginif (!rst_n)bit_cnt <= 5'd0;else if (bit_cnt_rst)bit_cnt <= 5'd0;else if (div_clk)bit_cnt &

13、lt;= bit_cnt + 1'b1;endassign dat_send_done = (bit_cnt = 5'd24);/*/regrDac_data;always (bit_cnt4:1 or rData) begincase (bit_cnt4:1)/从高到低发送11 位数据文档大全实用标准文案4'd1 : rDac_data <= rData10;4'd2 : rDac_data <= rData9;4'd3 : rDac_data <= rData8;4'd4 : rDac_data <= rData7;4

14、'd5 : rDac_data <= rData6;4'd6 : rDac_data <= rData5;4'd7 : rDac_data <= rData4;4'd8 : rDac_data <= rData3;4'd9 : rDac_data <= rData2;4'd10: rDac_data <= rData1;4'd11: rDac_data <= rData0;default : rDac_data <= 1'b0;endcaseend/*/regrDac_clk;alw

15、ays (bit_cnt) begin/ DAC_CLK输出时钟的产生period=2560nsif (bit_cnt >= 2) && (bit_cnt <24)rDac_clk <= bit_cnt0;/在时钟下降沿数据要有效elserDac_clk <= 1'b0;文档大全实用标准文案end/*/assign dac_clk = rDac_clk;assign dac_data = rDac_data;assign dac_load = rDac_load;/*/* 数码管显示部分* 说明 :数码管 1 显示通道 数码管 2 显示 RNG

16、值* 数码管 3和4显示 CODE 值*/reg3:0cs;/片选信号reg16:0cnt2;/计数寄存器2,确定扫描间隔reg3:0submsk;/ 保存要显示的数据always (posedge clk or negedge rst_n)if (!rst_n)begin文档大全实用标准文案cnt2 <= 17'd0;/计数器2 置零cs<= 4'b0111;endelse begincnt2 <= cnt2 + 1'b1;/计数器2 开始计数if (cnt2 = 17'd0)/溢出了，又从0 开始beginif (cs = 4'b0

17、111)begincs<= 4'b1110;/选择第四个数码管submsk <= rData3:0;/显示 CODE 低 4 位endelse if (cs = 4'b1110)begincs<= 4'b1101;/选择第三个数码管submsk <= rData7:4;/显示 CODE 高 4 位endelse if (cs = 4'b1101)begincs<= 4'b1011;/选择第二个数码管submsk <= 3'b000,rData8;/显示 RNG 值end文档大全digit_o <= MSK

18、_0;digit_o <= MSK_1;digit_o <= MSK_2;digit_o <= MSK_3;digit_o <= MSK_4;digit_o <= MSK_5;digit_o <= MSK_6;digit_o <= MSK_7;digit_o <= MSK_8;digit_o <= MSK_9;digit_o <= MSK_A;digit_o <= MSK_B;实用标准文案else if (cs = 4'b1011)begincs<= 4'b0111;/选择第一个数码管submsk <= 2'b00,rData10:9 + 1'b1;/显示通道endendendreg7:0digit_o;/数码管输出寄存器always (submsk)case (subms