VHDL程序练习题(含答案)

1、VHDL程序填空题（一）在下面横线上填上合适的VHDL关键词，完成2选1多路选择器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;MUX21 ISP ORT(SEL:IN STD_LOGIC;A,B:IN STD_LOGIC;Q: OUT STD_LOGIC );END MUX21;2BHV OF MUX21 ISBEGINQ<=A WHEN SEL= 1 ' ELSE B;END BHV;(二)在下面横线上填上合适的语句，完成BCD-7段LED显示译码器的设计。LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.

2、ALL;ENTITY BCD_7SEG ISP ORT( BCD_LED : IN STD_LOGIC_VECTOR(3 DOWNTO 0);LEDSEG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END BCD_7SEG;ARCHITECTURE BEHA VIOR OF BCD_7SEG ISBEGINP ROCESS(BCD_LED)3IF BCD_LED="0000" THEN LEDSEG<="0111111" "0000110"4ELSIF BCD LED="0001"

3、 THEN LEDSEG<ELSIF BCD LED="0010" THEN LEDSEG<ELSIF BCD LED="0011" THEN LEDSEG<ELSIF BCD LED="0100" THEN LEDSEG<ELSIF BCD LED="0101" THEN LEDSEG<"1001111""1100110""1101101"ELSIF BCD LED="0110" THEN LEDSEG&

4、lt;ELSIF BCD LED="0111" THEN LEDSEG<ELSIF BCD LED="1000" THEN LEDSEG<ELSIF BCD LED="1001" THEN LEDSEG<"1111101""0000111""1111111""1101111"ELSE LEDSEG<=END IF;END P ROCESS;END BEHA VIOR;（三）在下面横线上填上合适的语句，完成数据选择器的设计。LIBRA

5、RY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX16 ISP ORT( D0, D1, D2, D3: IN STD_LOGIC_VECTOR(15 DOWNTO 0);SEL:IN STD_LOGIC_VECTOR( DOWNTO 0);Y: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); END;ARCHITECTURE ONE OF MUX16 ISBEGINSELECTWITHY <= DOD1D2D3WHEN "00",WHEN "01",WHEN "10&quo

6、t;,WHEN 810END;（四）在下面横线上填上合适的语句，完成JK触发器的设计。说明：设计一个异步复位/置位JK触发器，其真值表如下：INPUTOUTPUTP SETCLRCLKJKQ01XXX110XXX000XXX不定11上升沿01011上升沿10111上升沿11翻转11上升沿00保持LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JKFF1 ISPORT (P SET,CLR,CLK,J,K : IN STD_LOGIC;Q : OUT STD_LOGIC);END JKFF1;ARCHITECTURE MAX PLD OF JKFF

7、1 ISSIGNAL TEMP:STD_LOGIC;BEGINP ROCESS( PSET,CLR,CLK)BEGINIF (P SET='0'AND CLR='1' ) THEN TEMP <='1'ELSIF (P SET='1'AND CLR='0' ) THEN TEMP <='0：ELSIF (P SET='0'AND CLR='0' ) THEN NULL;9 (CLK'EVENT AND CLK='1') THEN.(J=&#

8、39;0' AND K='0') THEN TEMP<=TE MP;ELSIF (J='0' AND K='1') THEN TEMP <='0：ELSIF (J='1' AND K='0') THEN TgMP <='1'11ELSIF (J='1' AND K='1') THEN TEMP<= END IF;END IF;END P ROCESS;Q<=TE MP;END ;（五）在下面横线上填上合适的语句，完成计数器

9、的设计。说明：设电路的控制端均为高电平有效，时钟端 CLK,电路的预置数据输入端为 4位D,计 数输出端也为4位Q,带同步始能EN、异步复位CLR和预置控制LD的六进制减法计数器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 ISP ORT(EN,CLR,LD,CLK:IN STD_LOGIC;D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(3 D

10、OWNTO 0);END CNT6;ARCHITECTURE BEHA OF CNT6 ISSIGNAL QTE MP: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINP ROCESS(CLK,CLR,LD)BEGINIF CLR='1' THENQTE MP <="0000"ELSIF (CLK'EVENT AND CLK='1') THENIF LD='1' THEN QTE MP<=ELSIF EN='1' THENIF QTE MP="0000&qu

11、ot; THEN QTEMP<=ELSE QTEM P<= 12-CLR=1 清零-判断是否上升沿-判断是否置位-判断是否允许计数;-等于0，计数值置5-否则，计数值减113END IF;END IF;END IF;Q<=QTE MP;END P ROCESS;END BEHA;（六）在下面横线上填上合适的语句，完成状态机的设计。说明：设计一个双进程状态机，状态 0时如果输入”10则转为下一状态，否则输出 ”1001” 状态1时如果输入” 11则转为下一状态，否则输出”0101”；状态2时如果输入” 01则转为下 一状态，否则输出”1100”状态3时如果输入” 00则转为状态

12、0,否则输出”0010。复位时为状态0。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MOORE1 ISPORT (DATAIN: IN STD_LOGIC_VECTOR(1 DOWNTO 0);CLK, RST:IN STD_LOGIC;Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE ONE OF MOORE1 IS-定义4个状态-定义两个信号（现态和次态）TYPE ST_T YPE IS (ST0, ST1, ST2,

13、ST3);SIGNAL CST, NST: ST_T YPE;SIGNAL Q1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN-主控时序进程REG: P ROCESS(CLK, RST)BEGINIF RST='1' THEN CST<=15-异步复位为状态0ELSIF CLK'EVENT AND CLK='1' THENCST<=16-现态=次态END IF;END P ROCESS;COM: PROCESS(CST, DA TAIN)BEGINCASE CST ISWHEN ST0 => IF DATAIN=

14、"10" THEN NST<=ST1;ELSE NST<=ST0; Q1<="1001" END IF;WHEN ST1 => IF DATAIN="11" THEN NST<=ST2;ELSE NST<=ST1; Q1<="0101" END IF;WHEN ST2 => IF DATAIN="01" THEN NST<=ST3;ELSE NST<=ST2; Q1<="1100" END IF;WHEN ST

15、3 => IF DATAIN="00" THEN NST<=ST0;ELSE NST<=ST3; Q1<="0010" END IF;17;END P ROCESS;Q<=Q1；END;（七）在下面横线上填上合适的语句，完成减法器的设计。 由两个1位的半减器组成一个 1位的全减器 -1位半减器的描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HALF SUB ISP ORT(A,B : IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC);END

16、HALF_SUB;ARCHITECTURE ART OF HALF SUB ISBEGINCOUT<=18-借位-差DIFF<= _END ;-1位全减器描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FALF_SUB ISP ORT(A,B,CIN: IN STD_LOGIC;DIFF,COUT : OUT STD_LOGIC); END FALF_SUB;ARCHITECTURE ART OF FALF_SUB IS19COMPO NENT HALF_SUBP ORT(A,B : IN STD_LOGIC;DIFF,COUT

17、: OUT STD_LOGIC);END COMPO NENT;20 T0,T1,T2:STD_LOGIC; BEGINU1: HALF_SUB PORT MAP( A,B, U2: HALF_SUB PORT MAP( T0,COUT<=24;END ;2122,T1);23,T2);（八）在下面横线上填上合适的语句，完成分频器的设计。 说明：占空比为1： 2的8分频器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLKDIV8_1TO2 ISP ORT(CLK:IN ST

18、D_LOGIC;CLKOUT:OUT STD_LOGIC );END CLKDIV8_1TO2;ARCHITECTURE TWO OF CLKDIV8_1TO2 ISSIGNAL CNT:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL CK:STD_LOGIC;BEGINP ROCESS(CLK)25)THENBEGINIF RISING_EDGE(IF CNT="11" THENCNT<="00"CK<=26ELSE CNT<=27END IF;END IF;CLKOUT<=CK;END P ROCESS

19、;END;（九）在下面横线上填上合适的语句，完成60进制减计数器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT ISP ORT(CLK: IN STD_LOGIC;H,L: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT;ARCHITECTURE BHV OF COUNT ISBEGINP ROCESS(CLK)VARIABLE HH,LL: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLK&#

20、39;EVENT AND CLK='1' THENIF LL=0 AND HH=0 THENHH:="0101"LL:="1001"ELSIF LL=0 THENLL:=28HH:=29ELSELL:=30END IF;END IF;H<=HH;L<=LL;END P ROCESS;END BHV;（十） 在下面横线上填上合适的语句，完成4-2优先编码器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CODE4 ISP ORT(A,B,C,D : IN STD_LOGIC

21、;Y0,Y1 : OUT STD_LOGIC);END CODE4;ARCHITECTURE C0DE4 OF CODE4 ISSIGNAL DDD:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL Q:STD_LOGIC_VECTOR( 31BEGINDOWNTO 0);DDD<=32P ROCESS(DDD)BEGINIF (DDD(0)='0') THENQ <= "11"ELSIF (DDD(1)='0') THEN Q <= "10"ELSIF(DDD(2)='0&

22、#39;) THENELSEQ <= "00"Q<="01"END IF;33Y1<=Q(0);Y0<=Q(1);END CODE4;(十一)在下面横线上填上合适的语句，完成LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_10位二进制加法器电路的设计。34.ALL;ENTITY ADDER1 ISPORT(A,B:IN STD_LOGIC_VECTOR(9 DOWNTO 0);COUT:OUT STD_LOGIC;SUM:OUT STD_LOGIC_VECTO

23、R(9 DOWNTO 0);END;ARCHITECTURE JG OF ADDER1 ISSIGNAL ATE MP: STD_LOGIC_VECTOR(10 DOWNTO 0);SIGNAL BTE MP: STD_LOGIC_VECTOR(10 DOWNTO 0);DOWNTO 0);SIGNAL SUMTE MP: STD_LOGIC_VECTOR( 35BEGINATEMP<= 0' & A;BTEMP<= 0' & B;SUMTE MP<=36SUM<=SUMTE MP(9 DOWNTO 0);COUT<=37 ;END

24、 JG;（十二）在下面横线上填上合适的语句，完成移位寄存器的设计。说明：8位的移位寄存器，具有左移一位或右移一位、并行输入和同步复位的功能。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY SHIFTER ISP ORT(DATA :IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC;SHIFTLEFT，SHIFTRIGHT:IN STD_LOGIC;RESET:IN STD_LO

25、GIC;MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0);QOUT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END SHIFTER;ARCHITECTURE ART OF SHIFTER ISBEGINPROCESSBEGIN38-等待上升沿-同步复位(RISING_EDGE(CLK);IF RESET='1' THEN QOUT<="00000000"ELSECASE MODE ISWHEN "01"=>QOUT<=SHIFTRIGHT &39WHEN &

26、quot;10"=>QOUT<=QOUT(6 DOWNTO 0)&WHEN "11"=>QOUT<= 41;40-右移一位-左移一位-不移，并行输入WHEN OTHERS=>NULL;42END IF;END P ROCESS;END ART;（十三）在下面横线上填上合适的语句，完成计数器的设计。说明：设计一个带有异步复位和时钟使能的一位八进制加法计数器（带进位输出端）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY

27、CNT8 ISPORT (CLK,RST,EN : IN STD_LOGIC;43DOWNTO 0);CQ : OUT STD_LOGIC_VECTOR(COUT : OUT STD_LOGIC );END CNT8;ARCHITECTURE BEHA V OF CNT8 ISBEGINP ROCESS(CLK, RST, EN)44 CQI : STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINIF RST = '1' THEN CQI :=“ 000” ;45CLK'EVENT AND CLK='1' THENIF EN = 

28、9;1' THENIF CQI < "111" THENCQI :=46ELSE CQI :=47END IF;END IF;END IF;IF CQI = "111" THEN COUT <= '1'ELSE COUT <= '0'END IF;CQ <= CQI;END P ROCESS;END BEHA V;发送开始前及发送（十四）在下面横线上填上合适的语句，完成序列信号发生器的设计。 说明：已知发送信号为” ”，要求以由高到低的序列形式一位一位的发送, 完为低电平。LIBRARY I

29、EEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY XULIE ISPORT (RES, CLK: IN STD_LOGIC;Y: OUT STD_LOGIC );END;ARCHITECTURE ARCH OF XULIE ISSIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINP ROCESS(CLK, RES)BEGINIF(CLK ' EVENT AND CLK=' 1' ) THENIF RES= ' 1' THENY<=' 0' REG<=48ELSE

30、 Y<=49;-同步复位，并加载输入-高位输出REG<=50-左移，低位补0END IF;END IF;END P ROCESS;END;（十五）在下面横线上填上合适的语句，完成数据选择器的设计。说明：采用元件例化的设计方法， 先设计一个2选1多路选择器，再使用3个2选1多路选 择器构成一个4选1多路选择器。LIBRARY IEEE;-2选1多路选择器的描述USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX21 ISP ORT(A,B,SEL : IN STD_LOGIC;Y : OUT STD_LOGIC);END MUX21;ISARCHITECTUR

31、E ART OF MUX21BEGINY<=A WHEN SEL='0' ELSEB；END ;-4选1多路选择器的描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX41 ISP ORT(A,B,C,D : IN STD_LOGIC;S1,S2 : IN STD_LOGIC;Y:OUT STD_LOGIC);END;ARCHITECTURE ART OF MUX41 ISCOMPO NENT MUX41P ORT(A,B,SEL : IN STD_LOGIC;Y : OUT STD_LOGIC);END COMPO

32、NENT;51 Y1,Y2:STD_LOGIC;BEGINU1: MUX21U2: MUX21U2: MUX21PORT MAP (A,B,S1,PORT MAP (C,D, _PORT MAP( Y1,Y2,525254）；，丫2）；，丫）；END ;（十六）在下面横线上填上合适的语句，完成8位奇偶校验电路的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY PC ISPORT ( A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);Y : OUT STD_LOGIC);END PC;ARCHITECTURE A OF P

33、C ISBEGINP ROCESS(A).VARIABLE TMP: STD_LOGIC;BEGINTMP55'0：FOR I IN 0 TO 7 LOOP5756TMP:=END LOOP;Y<=END P ROCESS;END;(十七)在下面横线上填上合适的语句，完成一个逻辑电路的设计, 其布尔方程为 Y=(A+B)(CO D)+(B ® F).LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY COMB ISP ORT(A, B,C,D,E,F,: IN STD_LOGIC;Y: OUT STD_LOGIC);END C

34、OMB;ARCHITECTURE ONE OF COMB ISBEGINY<=(A OR B) AND (C END ARCHITECTURE ONE;58D) OR (B59F);-十进制译码器的设计。(十八)在下面横线上填上合适的语句，完成一个带使能功能的二LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MY2TO10 ISPORT (EN: IN STD_LOGIC;60DIN: IN STD_LOGIC_VECTOR(60DOWNTO 0);PO UT: OUT STD_LOGIC_VECTOR(9 DOWNTO 0); END;A

35、RCHITECTURE ARCH OF MY2TO10 ISBEGINP ROCESS(EN, DIN)BEGINIF EN=' 1' THENCASE DIN ISWHEN "0000"WHEN "0001"WHEN "0010"WHEN "0011"WHEN "0100"WHEN "0101"P0UT<="0000000001"P0UT<="0000000010"P0UT<="000000

36、0100"P0UT<="0000001000"P0UT<="0000010000"P0UT<="0000100000"WHEN "0110"WHEN "0111"WHEN "1000"WHEN "1001"PO UT<="0001000000"PO UT<="0010000000"PO UT<="0100000000"PO UT<="1

37、000000000"WHEN OTHERS => PO UT<="0000000000"END CASE;END IF;END P ROCESS;END;D触发器的设计。（十九）在下面横线上填上合适的语句，完成下降沿触发的LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY DFF ISP ORT(D,CLK:IN STD_LOGIC;Q, QB: OUT STD_LOGIC);END DFF;ARCHITECTURE BEHAVE OF DFF ISBEGINP ROCESS(CLK)BEGINIF61AN

38、D CLK'EVENT THEN62Q <=QB<=N0T D;END IF;END P R0CESS;END BEHAVE;（二十）在下面横线上填上合适的语句，完成移位寄存器的设计。说明：4位串入-串出移位寄存器有有1个串行数据输入端（DI ）、1个串行数据输出输出端 （DO和1个时钟输入端（CLKLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SISO ISP ORT（DI: IN STD_LOGIC;CLK:IN STD_LOGIC;DO:OUT STD_LOGIC）;END SISO;ARCHITECTURE A OF

39、 SISO ISSIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINP ROCESS(CLK,DI)BEGINIF C LK' EVENT AND CLK' 1' THENQ(0)<=FOR6364LOOP65（二十一）在下面横线上填上合适的语句，完成同步22进制计数器的设计。Q(I)<= _END IF;END P ROCESS;DO<=Q(3);END A;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY

40、 COUNTER22 ISP ORT( CLK: IN STD_LOGIC;CH, C: OUT STD_LOGIC;QB1, QA1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE BEHAV OF COUNTER22 ISSIGNAL QB, QA: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL CIN: STD_LOGIC;BEGINQB1<=QB;QA1<=QA;P ROCESS(CLK)BEGINIF CLK'EVENT AND CLK='1' THENIF (QA=E

41、LSIF QA=66)OR(QB=2 ANDQA=1) THENQA<="0000" CIN<='0'67THEN CIN<='1' QA<=QA+1;ELSE QA<=68CIN<='0' END IF;END IF;END P ROCESS;P ROCESS(CIN, CLK)BEGINIF CLK'EVENT AND CLK='1' THENIF (QB=2 AND QA=1) THEN QB<=ELSE C<=70;69;C<='1&

42、#39;END IF;IF CIN='1' THEN QB<=71END IF;END IF;END P ROCESS;CH<=CIN;END;（二十二）在下面横线上填上合适的语句，完成一个“01111110'序列发生器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY SENQGEN ISP ORT(CLK,CLR,CLOCK:IN STD_LOGIC;ZO:OUT STD_LOGI

43、C);END;ARCHITECTURE ART OF SENQGEN ISSIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL Z:STD_LOGIC:='0'BEGINP ROCESS(CLK,CLR)BEGINIF CLR='1' THEN COUNT<="000"ELSEIF CLK='1' AND CLK'EVENT THENIF COUNT=72THEN COUNT<="000"ELSE COUNT<=COUNT+1;END I

44、F;END IF;END IF;END P ROCESS;P ROCESS(COUNT)BEGINCASE COUNT ISWHEN "000"=>Z<='0'WHEN "001"=>Z<='1'WHEN "010"=>Z<='1'WHEN "011"=>Z<='1'WHEN "100"=>Z<='1'WHEN "101"=>Z&l

45、t;='1'WHEN "110"=>Z<='1'WHEN OTHERS=>Z<=END CASE;END P ROCESS;73P ROCESS(CLOCK,Z)BEGINIF CL0CK='1' AND CLOCK'EVENT THENZO<=74END IF;END P ROCESS;END ART;（二十三）在下面横线上填上合适的语句，完成一个“01111110'序列信号检测器的设计。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTIT

46、Y DETECT ISP ORT( DATAIN:IN STD_LOGIC;CLK:IN STD_LOGIC;Q:BUFFER STD_LOGIC);END DETECT;ARCHITECTURE ART OF DETECT ISTYPE STATET YPE IS (S0,S1,S2,S3,S4,S5,S6,S7,S8);BEGINP ROCESS(CLK)VARIABLE7576BEGINQ<='0'CASE PRESENT STATE ISWHEN S0=>IF DATAIN='0' THEN P RESENT_STATE:=S1;ELSE P

47、 RESENT_STATE:=S0; END IF;WHEN S1=>IF DATAIN='1' THEN P RESENT_STATE:=S2;ELSE P RESENT_STATE:=S1; END IF;WHEN S2=>IF DATAIN='1' THEN P RESENT_STATE:=S3;ELSE P RESENT_STATE:=S1; END IF;IF DATAIN='1' THEN P RESENT_STATE:=S4;WHEN S3=>ELSE P RESENT_STATE:=S1; END IF;WHEN

48、 S4=>IF DATAIN='1' THEN P RESENT_STATE:=S5;ELSE P RESENT_STATE:=S1; END IF;WHEN S5=>IF DATAIN='1' THEN P RESENT_STATE:=S6;ELSE P RESENT_STATE:=S1; END IF;WHEN S6=>IF DATAIN='1' THEN P RESENT_STATE:=S7;ELSE P RESENT_STATE:=S1; END IF;WHEN S7=>IF DATAIN='0'

49、THEN P RESENT_STATE:=S8;Q<='1' ELSE P RESENT_STATE:=S0; END IF;77WHEN S8=>IF DATAIN='0' THEN P RESENT_STATE:=ELSE P RESENT_STATE:=78;END IF;80END CASE;CLK='1'END P ROCESS;79END ART;（二十四）在下面横线上填上合适的语句，完成序列信号发生器的设计。说明：带异步复位为 CLR时钟端为CLK输出端为Q,串行输出指定序列（低位先出） 。LIBRARY IEEE;US

50、E IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SENQGEN ISP ORT(CLR,CLK:IN STD_LOGIC;Q:OUT STD_LOGIC);END SENQGEN;ARCHITECTURE BEHA OF SENQGEN ISSIGNAL Q_TE MP: STD_L0GIC_VECT0R(2 DOWNTO 0);P ROCESS(CLK,CLR)BEGINIF CLR='1' THENBEGINQ_TE MP <=&

51、quot;000"(CLK'EVENT AND CLK='1') THENIF Q_TE MP="111" THENQ_TE MP <="000"81Q_TE MP<=Q_TE MP+1;END IF;WHEN 0=> LEDSEG<="0111111"82END P ROCESS;P ROCESS(Q_TE MP)BEGINCASE Q_TE MP ISWHEN "000"=>Q<='0'WHEN "001"

52、=>Q<='1'WHEN "010"=>Q<='0'WHEN "011"=>Q<='1'WHEN "100"=>Q<='1'WHEN "101"=>Q<='1'WHEN "110"=>Q<='1'WHEN "111"=>Q<='0'WHEN OTHERS=> 83;END CA

53、SE;END P ROCESS;END BEHA;（二十五）在下面横线上填上合适的语句，完成七人表决器的设计。 说明：一个带输出显示的七人表决器（两种结果：同意，反对）。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BIA0JUE7 ISP ORT(D:IN STD_LOGIC_VECTOR(0 TO 6); RLED,GLED:OUT STD_LOGIC;LEDSEG:OUT STD_LOGIC_VECTOR( 6 DOWNTO 0) );END;ARCHITECTURE BEV OF BIAOJUE7 ISBEGINP ROCESS(D)V

54、ARIABLE COUNT:INTEGER RANGE 0 TO 7 ;BEGINCOUNT:=84FOR85LOOPIF D(I)='1' THEN COUNT:=ELSE COUNT:=COUNT;END IF;END LOOP;IF COUNT>8786THEN GLED<='1'RLED<='0'RLED<='1'ELSE GLED<='0'END IF;CASE COUNT ISWHEN 1=> LEDSEG<="0000110"WHEN 2=

55、> LEDSEG<="1011011"WHEN 3=> LEDSEG<="1001111"WHEN 4=> LEDSEG<="1100110"WHEN 5=> LEDSEG<="1101101"WHEN 6=> LEDSEG<="1111101"WHEN 7=> LEDSEG<="0100111"END CASE;END P ROCESS;END BEV;（二十六）在下面横线上填上合适的语句，完成有限状态

56、机的设计。 说明：状态转换图如右图，S0S3为状态号，圈内为输出。LIBRARY1EEE ；USE IEEE . STD_ LOGIC_1164 . ALL ;ENTITY S_ MACHINE ISPORT( CLK,RESET : IN STD_LOGIC;INPUTS : IN STD_LOGIC_VECTOR (0 TO 1)OUT PUTS : OUT INTEGER RANGE (0 TO 15 ) END S_ MACHINE ;ARCHITECTURE BEHAV OF S_MACHINE ISTYPE STATES IS(S0,S1, S2,S3);SIGNAL CURCEN

57、T_STA TE , NEXT_STATE : STATES; BEGINREG: PROCESS (RESET，CLK)-状态切换BEGINIF RESET = 1 'HEN CURRENT_ STA TEELSIF CLK= ' L' AND CLK EVENT<=S0；THENCURRENT_ STA TE <= NEXT_ STATE;END IF;END PROCESS ;COM:PROCESS(CURRENT_ STATE ,BEGININPUTS）-下一状态、CASECURRENT STATE ISWHENIFS0 => OUTPUTS&

58、lt;=INPUTS=” 00” THEN NEXT_ STA TE<=S0;88ELSE NEXT_ STATE<=SL ;END IF ;WHEN SL=> OUTPUTS<=8 ;IF INPUTS= 89 THEN NEXT_ STA TE<=ELSE NEXT_STATE<=S2 ；END IF ；WHEN S2=> OUTPU TS<=12;IF INPU TS= “11” THEN NEXT_STATE<=S0;ELSE NEXT_STATE<= S3;END IF;WHEN S3=> OUTPU TS<=14;NEXT_STATE<=S3;IF INPUTS =“11” THENELSE NEXT STATE <=S0;END IF ；END CASE;91;END BEHA V;74166的设计。(二十七)在下面横线上填上合适的语句，完成移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164