实验六Verilog设计分频器计数器电路答案

1、实验六一Verilog设计分频器计 数器电路答案实验六Verilog设计分频器/计数器电路一、实验目的1、进一步掌握最基本时序电路的实现方法;2、学习分频器/计数器时序电路程序的编写方 法;3、进一步学习同步和异步时序电路程序的编 写方法。二、实验内容1、用Verilog设计一个10分频的分频器，要求 输入为clock （上升沿有效），reset （低电平复 位），输出clockout为4个clock周期的低电平, 4个clock周期的高电平），文件命名为 fenpinqilO. v。2、用Verilog设计一异步清零的十进制加法计 数器，要求输入为时钟端CLK （上升沿）和异步 清除端CLR

2、 （高电平复位），输出为进位端C和4 位计数输出端Q，文件命名为couterlO. vo 3、用Verilog设计8位同步二进制加减法计数 器，输入为时钟端CLK （上升沿有效）和异步清 除端CLR （低电平有效），加减控制端UPD0WN, 当UPDOWN为1时执行加法计数，为0时执行减 法计数；输出为进位端C和8位计数输出端Q, 文件命名为couter8. v。4、用VERILOG设计一可变模数计数器，设计要 求:令输入信号Ml和M0控制计数模,当M1MO=OO 时为模18加法计数器；M1MO=O1时为模4加法 计数器；当MIMO=IO时为模12加法计数器； M1MO=11时为模6加法计数器

3、，输入elk上升沿 有效，文件命名为mcout5. V。5、VerilogHDL设计有时钟时能的两位十进制计 数器，有时钟使能的两位十进制计数器的元件符 号如图所示，CLK是时钟输入端，上升沿有效；ENA是时钟使能控制输入端，高电平有效，当ENA=1时，时钟CLK才能输入；CLR是复位输入 端，高电平有效，异步清零；Q3.0是计数器 低4位状态输出端，Q7.0是高4位状态输出 端；COUT是进位输出端。三、实验步投实验一：分频器1、建立工程2、创建Verilog HDL文件3、输入10分频器程月片代码并保存”二。一步«4 % 专一唱 SG一后=ar知7用|fefpin01O K 我/

4、0中学口>守功匕训®；*彳 g fe 叩标 1 Jj.v| 尊 CcirpiMcn Report -Flow Summoiyrocdule fenpinqilO_ljj(elk/reset/clkout); input clkrreset;output clkout;reg 3:0 cqc;req clkout;always ?( posedqe elk or neqedge reset)iff! reset)begincnt<=0;clkour<=0;endelseif(cnt=4)begincnt<=0;clkout<=lkout;endelsecn

5、t<=cntl;endmodule-apilation at Phu Dec 04 2L0L50 2014人 1 U 1 - ) 逐一 J,JJdf1 (Timm I人i4、进行综合编译? W 8 Ixfo:frxt cl-sk wrlk" :力 destinatioi pix rclx:,j：, thresh reps:er r:lx-xec3" is 6.4£： ns8 8 Ix£o; Qjaxtus II ?inirvj Analyz-i vas wccessful. 0 -rxors, 1 xsrnii"Itfo:。皿X。II P

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7、fetjn加L)jj刈山-Ihi Dec C4 2):讨: 2014Build 178 C4/27/2M6 SJ Full V«slOpinqilOrdrn!16 HIFk- StatusSueQuarts jI Versk<i6ErrisUn Ki»rferl(£rl£f/Q Ent 1 tv laia farQuartusIIi>issenbterimingAn 碍zer0 Full CoTpiteticn was successfbl (2 warnings)(< 1 X ) 1»)(Olj i ) )$2）的。【叼收|

8、 76Mloiile1?ul) Coiplhtlwi1rM“ i nibertsJitteriasfthler皿)Finns mMernH厂»5、新建波形文件NewDevice Design Files Other FilesAHDL Indude FileBlock Symbol FileChain Descripton File Hexadecimal (ntel-Formatj File Logic Analyzer Interiace File Memory Inilializstion File SignafTap II FileTd Script File Text Fi

9、leVector Waveform FileOK Cencel6、导入引脚Node Finder7、设置信号源并保存icnpirqiiv二V 7 飞注T 囚 tenprqilOJj.v| 哥 Corr(3itati3n Repcn-AowSimmofy| 弓 fenpmqiUJjj.vwf区 MesrlimeSer 1&与冲 山PcwB 100 ps 询同-18 35 reSMEndr , 0 psLO. 0 ns20.0 ns20.0 ns40.0 ns外 Falu ssJ：常世 刊,以45 ns；二nrLnnnnnnrJuwwLnjTnrLnjTnrLmrjTnjuwwLnjTri

10、rmnnjTnn reset Bnqil0_ljj.vwf lb saved in text format. You can ccaress Lz into Cccnpressed Vector Waveform File fomat in order to ret )X Waning人C而刈*&而/ Emr入Su卬汜$湖 /“卜灿笛cn | locere8、生成网表QuartusII翁 Functional Simulation Netlist Generation was successful (1-warnings)确定9、功能仿真lep< ticeima :ingrlar

11、y gs atioi atioiage igesSimulaiion WaveformsSlnulatlon xode： liningWaster Time BorIn 忸elkrcscBane1845n5JJ Pointer30.0 ns,40.0 ns.50. 0 ns60. 0 醯：cessful. 0 errors, 3 warnings10、仿真结果分析.0 errors/ 0 waminga 4nmg 入 Error 入 Suppressed /由仿真结果可以看出clockout输出5个clock 周期的低电平和5个clock的高电平达到10 分频的效果，设计正确。实验二：十进制加

12、法计数器（异步清零）1、 建立工程2、创建Verilog HDL文件3、输入加法计数器代码并保存网 3 counter! O_lij.v*| 母 CompldicnRepcri-Flaw Summoiy华：nodule counter 10_1 jj (uk,HkrQ,C);订input clr,elk;output3:0Q;室 output C;星 reg3:0 Q;reg C;always g ©sedge elk or posedge clr) beginif(clr) Q=0;else beginif(Q=9J Q=。；else 2=21;if(Q=C) C=l;else C

13、=0;endendencbodule4、进行综合编译1 |counter*C Ju3 cou他rlOJ仅 Zompilation Report§ Legal Notice3 Flow Summary3 Flow Settings3 Flow Non-Default3 Flow Elapsed Tim 目 Flow LogJ Analysis & Synthc Fitterj AssemblerJ Timing Analyzer备 Compilalinn Report - Flow SummatyIIIFlow SummarySuccessful - Sot Dec 06 09

14、:32:50 20146.0 Build 178 01/27/2006 SJ Full VersionJJ0/2(0%)Total ECLs(<1X)X )Flow StatusQuart: II Version5、新建波形文件6、导入引脚qNode Finder汉一4Mamod pzJFiller |F,ins dlzJCuomire.|U就OKXLook in: |1*血匝：讪*fl口hdudo subenmesConcel一Modes FoundSeteci-d I4cdes:-MamaAsaqrm . | Tvpp| OoeName| Assignm | Typo| Qae一n一

15、“cBCl OQD 5则 3Q2J“dk BdrUnossig.Unaseig.Unassig.UftD55ig.Uneseig.Unassig.Unos$ig.Unnssig.GuW OuWG. 0呻5 。邛X OU10K 。叩1/ lnp«/ InputUse Uee Use Use Uee UiQ U3 Use_dIcoumed OJiilC 砌 com 期1 (dig I>cDunterl OJjilk 3 |8UM8C(Uil 即Unokis. OutputUna笠Output G.Unassig . hpulUnaig. hpmUse Use Use Use一上J*

16、：=<ni><r*1一7、设置信号源并保存;ounter1OJ|2J算/3力$ 5 > V : 号 电 出A J bMetI。炉| 号 COrrpiltilicn Report-Hw Summer." | 日 counlerl OJj wf与 Simdolan Report- Simuloian& Waster TrneBerOps±|P 而斯 | TOps期询?0p3SitErd I"Me20.0 ns40. 0 ns60.0 mfelk clr C国Qmrnuuuinnn几nnnniuuinjinr皿皿innri皿nnnai皿n

17、nnjuinauinjifinwui川uuuuu8、生成网表sxclrCa |JLJLI!JLJUUU!JLJ；LJUULJULJU!JLJUUU!JLIUUU!JLIULJU!JLIUUULJ9、功能仿真BsrOps <|» Pointer:S1MEnd:3.k.rJTLIniBrvBJ:)PS3 PS20.0 nsInj"U"LrLTLTLJ"Lj"mj"LrLrLrLrLrLrI_|10、 仿真结果分析|counter10Jj三处，髻也等；与怔 323a)untfirlOJ|VI' Silation Wavefc4

18、ms：串 Corrpitelon Report - Acw Strnfrey | 四 coufiteflOjy号 Simdafion Report - Simulation . |a岳昌昌ii，日Sinulatica node: FurKtic-JulJJ Fierier533 ns 5©riEnd5 33 nsHb 伙3tMaster Time Bar由仿真结果可以看出异步清除端CLR高电平时，输出Q清零，CLR低电平则Q进行1至1|9的计数，超过9进位端C为1 , Q从0开始重 新计数如此循环。因此设计正确。实验三：8位同步二进制加减计数器1、建立工程2、创建Verilog HD

19、L文件3、输入同步8位加减法计数器程序代码并保存|tuuniciujj二 MF&v，w F v 1 0日 counter8Jjj.vmodule counterBJjj (cr3zcrload,ena；elk；clrjUpcl;input7:0 d;input lcadrenarclkrclirupdown;output regP：0 c;output reg c;always8(posedge elk )bsqinif(-clr)q=0;else if(load) c=l;else if (ena) beginif(updora) begin c=q+l;if(q=255)c=l;e

20、lse c=0;endelse begin q=q-l;15if(q=0)c=l;else c=0;endJ 17endendendmochile4、进行综合编译Revision WanecounterB.ljjTop-level Entity Kame cter 8(OK) 6 )5、新建波形文件二 a(0 % ) )(< 1 % %)Sat De* ? 04/27.3UC successful. 0 errors 3 warningsin6、导入引脚ftNode Finder"T ramiri力LLNonred:J Fih=roilLook in:隹眦也JUf jCusio

21、rrize.| Ll91 |OK | J 歹 Include subentrtes：|CancelNodes FoundSelected HadesNome| Assignm Type | C，Nome| Assignm | T冲8| Cree»dkUnasg.InputI-dr.InputU_1udUnaaag .mpMGroltd(0U2哙g .InputLl*dlUnasag .InputLid(2Unosg.InputU1l>d3Unacag .InputL曲jUn&sg.InputL»d5Unossig .InputL>i>d6Unesa

22、g .inputLi#d(7|Uftossig .Inputi.0>EcnaUnasag .InputL 一loodUnossig.InputL<iqUnacag . Output G . LAq0Un&s$4g.OutpvXL«>q1Unossig.OuipuLctqZUnas sig.OutpuL4>q(3|Uns包g.OuipulQqjdjUnassig.OutputL<>q(5Unossig.OutpULOq6Unacsig.Outputlq切Un&ssg“.OutpUI卬downUnossiQ.InputI <>

23、;|countjet8Jjj|cUnaig.OuipuiUsei|counrer8Jij|dkUngjigInpuiUsei>|counter8JH|dfUnassigInpuiUse*|counrer8Jij|ciUna铃 ig1 叩 uiGro.Uset5»|cDun»cr8Jjj|qUnasstgOtripul G .UseijcountefBJiilenaUnasiq.InpulUseE|countDr8Jjj|foadUnawigInpulUcqi>|counter8jji|updcr/.riUnasig.InpulUse，i-i>< 1i

24、n>Isssss1/7、设置信号源并保存:Q oourteraJjj.v| 尊 Cofnpiaibn R&poit-FSurnrrsan,'| 可 counter8Jjj.vwf8、生成网表9、功能仿真10、 仿真结果分析R ooLrrt=i6_(|.v| 好 Campialnn Report - Flcr* Summaf>> | 可 counterSJijvAl Sirrwlation Report - Simulation 一 |)1 S Hill '.7,-,vrfonrt'.).Si>alati'>n node: F

25、unctional>4astDrTmo BaiRaaeOEEngEBelk clrS d ena loadS QVa.10.0 ns624 ps htarvd:-318rc SledEnd日 counterBJjjvh Simulation Waveforms二 m y 中 z w n ” v p 五 n焙 COmpiltMicn Report - Flew Surnmwy | 弓 cour(ier3_ljjvv4号 Simulation Report - SimulationSiiulation rode: FunctionalMasierTirrieBsj10.0 ns1765 ns

26、Intend:166.5 nsSl81t1.0 usEaie130.0 nsI190.0 nsI21(1. 0 ns220.0 nselk clr国denaloadwdovnLr krLrLrLrTTTr LrLrLrLrLrLrLrLrLTLrLrLrLrLrLrLr(3 q?qK两XT丽丫所用彳X菽丫卮诉XT钾Y的圻用丽>2。1丘丽心而您”WYWYWXWW(则 <n(rije id 77.31 tr.ons in simulation is 41466 :rB_Ljj.3im.7xf is saved in VWF tex* format. You can ccaprcss i

27、t into CVWF foxi&nt order to reduce file size. For mi E由仿真波形图可以看出当时钟clock的上升沿到来时,clr为低电平时清零， 实现同步复位。当updown为低电平时，计数器做减法操作；当updown为低 电平时，计数器做加法操作。所以设计正确。实验四：可变模数计数器1、建立工程2、x、创建Verilog HDL文件s-r X-/1az 4 j * y J J *VC 4 / w J 一 一. 匚 - * -3、输入可变模数计数器程序代码并保存module mcout5_ljj (Ml, MO, CLK, out, c, CLR

28、);input M1,MO,CLK, CLR;output c;output5:0out;reg c;reg5:0M,N;reg5：0out;always9(posedge CLK or posedge CLR)beginif (CLR)beginout<=0;N<=0;endelsebeginN<=M;case (Ml, MO)'b00:M<=18;'bOl:M<=4;'biO:M<=12;'bll：M<=6;endcaseif(N=M)beginif (out= (M-l)beginout<=0;c=c;end

29、elsebeginout<=out+l;endendelsebeginout<=0;c<=0;endendendendmodule4、进行综合编译Flov Status Quartus II Version Revision Kan已Quartos IISuccessful - Thu Dec 11 09:05:12 2014 6.0 Euild 178 04/27/2006 SJ Full Version acout5 1JJI区IFull Compilation was successful (6 warnings)确定Total DLLs0/2(0%)5、新建波形文件N

30、ewDevice Design Files Other FilesAHDL Include Fil©Elod< Symbol FileChain Description FileHexadecimal (Iniel-Format) File Logic Anolyzer Interface File Memory Initialization Fil© SignalTap II File Tel Script FileText FileVector Waveform FileOKCancel6、导入引脚Node Finder汉Norred- p ； Fiter-Cus

31、tomizeLook in;f j 仔 Incbde suberfitiesCancelNodes Found,Selected NodesNameI Aseiqnm. I Type Cree Netre小LRO ttlol知眄何的灼 c c M M cOLouououo 10lcu IFB WAa 60HQth8s$ig“. hput6B6e e e e8B86e S0V8S s $ ssssss uuuuuuuuuuuu t ts ry r. kl bv u u u u u u p w V w u u u u u u o o o o o oIhessig. hputLessig. hput

32、Lhossig. hputLhossig. OutputLhossig. Output G咧 rrmu5iKLKUi8&9g. InputUsei|mccu5JjjClUiessig. InputUsei*|mcoiJ5JjM0IhBsWg. InputUseir|mcou5JiJMILhosag. InputUseO|mcoa5j|jcLhossjg. OutputUsemcoUSJijoulUiB5&g. OutputG.UseI As的rmType ； Cree7、功能仿真Mester Time B8r20 025 re4 HppmyI 6 4 ne Intel |-13

33、 63 reSWKmcE3用胃K R厂 L 1 B aIdlllc wax - n-ns 24。,p mQuortus 11320f m的0p ns 48Qp na 560.P ns640. 0 ns20.025 m仲uuiruumnn皿fuinnjmuyinjmnjmfuuuirumnfm皿fuiruinnrwuifuirifmnnauinjinnnwuuijL Functional Simulation Netlfct Generation was successful (5 warnings)in、仿真结果分析当M1MO=OO时波形图，此时为模18的加法计数器F g mcnufijjv

34、Corrpilaricri Aepoit -FhwSimmay 可 W&必om1 w/号 Simuhtion Report - SimdatioB |ljj.sbi.vwf 13 3a78d in TtE text format Yau can conpresa it into CT forxat in order to reduce file size. For当M1MO=O1时波形图，此时为模4加法计数器当M1MO=1O时波形图，此时为模12加法计数器3曲". Compilalicri Repcrt Flow Summo/y列 VZoictwLwl| Q Simulati

35、on Report-SimutalionSimulation WavufcxmsSiivlation nod: JunctloBalMnatafTirrieBar20.02S ns正 Po 在 r4359 nsIrign/d:23.57 nsStDfl：EM:50.0 ns,虬0 ns130.0 nsJ170. 0 ris.210.0 ns.250.0 ns290.0 nsjn_rLn_rLn_rLrLn_rLruri_n_rLn_rLrLn_rLn_rLrLrLrLrLnIDIrtI K c os当M1MO=O1时波形图，此时为模6加法计数器3 n)coul5Jj.v| 号 Corrpild

36、ionReport- HwSTinajy | 弓 WavEforml vM逊 Simulation Report - SifiwtelionLjj.aitn.vwf io saved in VXP 二ex二 format. You can comprcxs i* into CVWP format in order zc reduce file size. For rou* r waa duccesdful. 0 erxora, 0 warnings实验五：2位十进制计数器1、建立工程New Project Wizard: Directory, Name, Top-Level Entity pa

37、ge 1 of 5Whot is ihe working directory for this project?|DAQuartus IIWh8t is ihe name of th is project*?|counterjjj.What is Ihe name of the top-level design entb/for this projeci? This name is cose sensiiive ond must exadly match th© entity name in ihe design file.Use Existing Project Settings

38、.WextFinish取消2、创建Verilog HDL文件NewDevice Design Files | other Files |AHDLFileElock Diegram/S chematicFileEDIF FiloSOPC Builder SystemVerilog HDL FileVHDLFileCancel3、输入2位十进制计数器程序代码并保存module counters (elk, clr, ena, cout, ql, qh); input elk, clr, ena;output cout;output3:0 ql, qh;reg3:0qh, ql;reg cout;a

39、lways ©(posedge elk or posedge clr)beginif(clr)beginqh<=0;ql<=0;cout<=0;endelse if(ena)beginql<=ql+l;if(ql='bl010)beginql<=0;qh<=qh+l;if(qh='bl010)beginqh<=0;cout<=/vcout;endendendendmodule 4、进行综合编译口尾1 S $1cccmefjj刁&，守力中 岁七U998Prowct MWgFloSMcnmdryCCUlKfS'

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42、3，rror*.2 warning*5、新建波形文件NewDevice Design Files。砧er FilesAHDL Indude FileBlock Symbol FileChain Description FileHexadecmsl (Intel-Format) FileLogic Analyzer Interface FileMemo Initialisation FileSignolTop II FileTd Script FileText FileVeclor Wavef o rrn FileOK Cancel6、导入引脚: =Node FinderNonrugd, *Look in:|com 岭 ibHo 触