杭电计组实验四

1、杭电计组实验四实验报告2016 年4 月22日成绩：姓名学号班级专业信息安全课程名称计算机组成原理课程设计任课老师曾虹指导老师曾虹机位号实验序号实验名称寄存器堆实验时间2016.4.22实验地点1 教南实验设备号一、实验程序源代码module Reg(LED,RW_SW,AB,Reg_Addr_A,Reg_Addr_B,Write_Reg,clk,rst); input4:0 Reg_Addr_A,Reg_Addr_B;input Write_Reg;input1:0 RW_SW;input clk;input rst;output7:0 LED;input AB;reg31:0REG_;re

2、g7:0 LED;wire31:0 W_Data1 = 32'h00000001;wire31:0 W_Data2 = 32'h0000000A;wire31:0 W_Data3 = 32'h00000006;wire31:0 W_Data4 = 32'h00000003;wire31:0 A = REG_;wire31:0 B = REG_;integer i;always (posedge clk or posedge rst)beginif(AB)case(RW_SW)杭电计组实验四2'b00 : LED=A7:0;2'b01 : LED=

3、A15:8;2'b10 : LED=A23:16;2'b11 : LED=A31:24;default : LED=A7:0;endcaseelsecase(RW_SW)2'b00 : LED = B7:0;2'b01 : LED = B15:8;2'b10 : LED = B23:16;2'b11 : LED = B31:24;default : LED = B7:0;endcaseif(rst)for(i = 0; i < 32; i = i + 1) REG_Filei = 0;elsebeginif(Write_Reg)begini

4、f(AB)case(RW_SW)2'b00 : REG_=W_Data1;2'b01 : REG_=W_Data2;2'b10 : REG_=W_Data3;2'b11 : REG_=W_Data4;endcaseelsecase(RW_SW)2'b00 : REG_=W_Data1;2'b01 : REG_=W_Data2;2'b10 : REG_=W_Data3;杭电计组实验四2'b11 : REG_=W_Data4;endcaseendendendendmodule二、仿真波形杭电计组实验四三、电路图杭电计组实验四杭电计组实

5、验四四、引脚配置（约束文件）NET "Add4" LOC = "T5"NET "Add3" LOC = "V8"NET "Add2" LOC = "U8"NET "Add1" LOC = "N8"NET "Add0" LOC = "M8"NET "WR"LOC = "V9"NET "C1"LOC = "T9"NET &

6、quot;C0"LOC = "T10"NET "clk"LOC = "C9"NET "RS"LOC = "D9"NET "AB"LOC = "A8"杭电计组实验四NET "LED7" LOC = "T11"NET "LED6" LOC = "R11"NET "LED5" LOC = "N11"NET "LED4&quo

7、t; LOC = "M11"NET "LED3" LOC = "V15"NET "LED2" LOC = "U15"NET "LED1" LOC = "V16"NET "LED0" LOC = "U16"五、思考与探索寄存器地址写入数据读出数据$000000000_00000000_0000$000010000_00030000_0003$000117FFF_FFFF7FFF_FFFF$001117FFF_FFFF7

8、FFF_FFFF$011110000_00000000_0000$111110000_00030000_0003$100007FFF_FFFF7FFF_FFFF$110007FFF_FFFF7FFF_FFFF修改后的寄存器模块：time scale 1ns/1psMoudleRegister(R_Addr_A,R_Addr_B,R_Data_A,R_Data_B,W_Addr,W_Data,Write_Reg,Clk,Reset);input 4:0 R_Addr_A;input 4:0 R_Addr_B;input 4:0 W_Addr;input 31:0 W_Data;input Wri

9、te_Reg;input Clk;input Reset;output 31:0 R_Data_A;output 31:0 R_Data_B;integer i;杭电计组实验四reg31:0 REG_Files31:0;/ 定义寄存器assign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always (posedge Clk or posedge Reset)beginif(Reset)/ 清零beginfor(i=0;i<32;i+)REG_Filesi<=0;endelsebeginif(Write_Reg&&(W_Addr!=0)beginREG_FilesW_Addr<=W_Data;endendendEndmoudle（ 3）、读操作是时