数字电路课程设计

1、 数字电路课程设计一 设计思路：对工业控制中生产轧钢板厚度的测量，设计一个通过移动的滑动电阻，测量其在电路中的电压变化，再通过单片机等判断厚度，进行轧钢机的调整。做一个电压测量器，数据采样通过数据分配器输入ADC0809数模转换器，通过ADC0809转换为数字信号，并通过数码管显示十六进制显示。二 设计内容：模数转换器ADC0809 程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity ADC0809 is port ( d

2、: in std_logic_vector(7 downto 0); -ADC0809输出的采样数据 clk,eoc : in std_logic; -clk为系统时钟，eoc为ADC0809转换结束信号clk1,start, ale,en: out std_logic; -ADC0809控制信号 abc_in :in std_logic_vector(2 downto 0); -模拟选通信号abc_out :out std_logic_vector(2 downto 0); -ADC0809模拟信号选通信号 q : out std_logic_vector(7 downto 0); -送至8

3、个并排数码管信号 end ADC0809; architecture behav of ADC0809 is type states is ( st0,st1, st2, st3, st4,st5,st6); -定义各状态的子类型signal current_state, next_state:states:=st0;signal regl :std_logic_vector(7 downto 0); -中间数据寄存信号signal qq:std_logic_vector(7 downto 0):="00000000"begincom:process(current_sta

4、te,eoc) -规定各种状态的转换方式begin case current_state is when st0=>next_state<=st1;ale<='0'start<='0'en<='0' when st1=>next_state<=st2;ale<='1'start<='0'en<='0' when st2=>next_state<=st3;ale<='0'start<='1

5、9;en<='0' when st3=> ale<='0'start<='0'en<='0' if eoc='1' then next_state<=st3; -检测EOC的下降沿 else next_state<=st4; end if; when st4=> ale<='0'start<='0'en<='0' if eoc='0' then next_state<=st4; -

6、检测EOC的上升沿else next_state<=st5;end if; when st5=>next_state<=st6;ale<='0'start<='0'en<='1' when st6=>next_state<=st0;ale<='0'start<='0'en<='1'regl<=d; when others=> next_state<=st0;ale<='0'start<=&

7、#39;0'en<='0' end case;end process;clock:process(clk) -对系统时钟进行分频，得到ADC0809转换工作时钟begin if clk'event and clk='1' then qq<=qq+1; -在clk1的上升沿，转换至下一状态if QQ="11111111" THEN clk1<='1' current_state <=next_state; elsif qq<="01111111" then clk

8、1<='0' end if; end if;end process;q<=regl; abc_out<=abc_in; end behav; 1， 生成的工程编译：2，生成的原理图：3，RTL级电路：2， 仿真时序图：说明：设置clk信号，选择通道进行模拟信号作为输入进行A/D转换，sen信号为高电平时，ADC0809将8位数据送至Q输出。.八选一数据分配器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY select1_8 IS PORT(Q:IN STD_LOGIC; sel: IN STD_LOGIC_VE

9、CTOR(2 DOWNTO 0); D:OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );END select1_8;ARCHITECTURE abc OF select1_8 IS -81数据分配器 BEGIN PROCESS(sel) -进程语言使用 BEGIN CASE sel IS -使用case语句 WHEN "000"=> D(0)<=Q; WHEN "001"=> D(1)<=Q; WHEN "010" => D(2)<=Q; WHEN "011"

10、;=> D(3)<=Q; WHEN "100"=> D(4)<=Q; WHEN "101" => D(5)<=Q; WHEN "110"=> D(6)<=Q; WHEN OTHERS=>D(7)<=Q; END CASE; END PROCESS;END abc;1，通过编译产生正确的8选一数据分配器项目：,2，通过建立原理图产生原理图八选一数据分配器：Sel输入选择的信号，Q为输入数据引脚，D7.0为分配时输出输入的数据Q的引脚。3， 生成的RTL级电路4，数据分配器的时序

11、仿真波形：设置Q为随机的1,0信号输入，sel为二进制000111循环的选择信号，D0D7为输出信号，仿真中有延时的原因，部分输出收到上一状态的影响。led7段数码管：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity ymp is port(num:in std_logic_vector(3 downto 0);seg_r:out std_logic_vector(7 downto 0);end ymp;architecture

12、 a1 of ymp isbeginprocess(num)begincase num iswhen "0000" => seg_r <= "11000000" -1when "0001" => seg_r <= "11111001" -2when "0010" => seg_r <= "10100100" -3when "0011" => seg_r <= "10110000" -4wh

13、en "0100" => seg_r <= "10011001"when "0101" => seg_r <= "10010010"when "0110" => seg_r <= "10000010" -.when "0111" => seg_r <= "11111000"when "1000" => seg_r <= "10000000"

14、;when "1001" => seg_r <= "10010000"when "1010" => seg_r <= "10001000"when "1011" => seg_r <= "10000011"when "1100" => seg_r <= "10100110"when "1101" => seg_r <= "10100001"

15、;when "1110" => seg_r <= "10000110" -fwhen "1111" => seg_r <= "10001110" -0end case;end process;end a1;仿真：Num输入，seg_r输出相应的16进制RTL级电路6.例化设计顶层元器件：顶层设计：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.a

16、ll;entity lihua isport ( -顶层文件对于引脚的声明定-义 d:in std_logic; -数据输入引脚 s:in std_logic_vector(2 downto 0); -分配选通引脚 led1 : out std_logic_vector(7 downto 0); led2 : out std_logic_vector(7 downto 0); clk,eoc : in std_logic -时钟和使能 );end lihua;architecture structure of lihua iscomponent select1_8 -八选一数据分配器元件声明

17、port ( Q:IN STD_LOGIC; sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); end component; component ADC0809 port ( d : in std_logic_vector(7 downto 0); -ADC0809输出的采样数据 clk,eoc : in std_logic; -clk为系统时钟，eoc为ADC0809转换结束信号clk1,start, ale,en: out std_logic; -ADC0809控制信号 abc_in :i

18、n std_logic_vector(2 downto 0); -模拟选通信号abc_out :out std_logic_vector(2 downto 0); -ADC0809模拟信号选通信号 q : out std_logic_vector(7 downto 0); end component;component ymp -数据分配器 port( num:in std_logic_vector(3 downto 0); seg_r:out std_logic_vector(7 downto 0);end component;signal a:std_logic_vector(2 downto 0); -中间信号的声明signal b:std_logic_vector(7 downto 0);signal d1:std_logic_vector(3 downto 0);signal d2:std_logic_vector(3 downto 0);begin -引脚的声明，调用u0:ADC0809 port map(d=>b,clk=>clk,eoc=>eoc,abc_in=>s,q(0)=>d1(0),q(1)=>d1(1),q(2)=