电子电路设计训练（北航）数字系统设计7

1、【例1】调用门元件实现的1位半加器 module ha丄f_addl(a,bz sum,cout); input a,b;output sum,cout;and (cout,a,b);xor (sum,az b);endmodule【例2】数据流方式描述的1位半加器 module half_add2(a,bz sum,cout); inputoutput sum,cout;assign sum=aab;assign cout=a&b;endmodule【例3】采用行为描述的1位半加器 module half_add3(a,bz sum,cout); input a,b;output s

2、um,cout;reg sum,cout;always (a or b)b egincase (-2,b)/真值表描述2fb00:beginsum=0;cout=0;end2-b01:beginsum=l;cout=0;end2-blo:beginsum=l;cout=0;end2fbll:b eginsum=0;cout=l;endendcaseendendmodule【例4】采用行为描述的1位半加器 module ha丄f_add4(a,bz sum,cout); input a,b;output sum,cout;reg sum,cout;always (a or b)beginsum=

3、 aab;cout=u&b;endendmodule【例5】调用门元件实现的1位全加器 module full_addl(a,bz cin,sum,cout); input,cin;output sum,cout;wire sl,mlzm2,m3;and (ml,a,b),(m2, b, cin),(m3, a, cin);xor (si,a,b),(sum,slz cin);or (cout,ml,m2,m3);endmodule【例6】数据流描述的1位全加器module full_add2(af b,cinz sum,cout);input a,bz cin;output sum,

4、cout;assign sum = a a b a cin;assign cout = (3 & b) i (b & cin) | (cin & a);endmodule【例7】1位全加器module full_add3(a,bz cin,sum,cout);input a,bz cin;output sum,cout;assign cout,sum=a+b+cin;endmodule【例8】行为描述的1位全加器module full_add4(a,b,cin,sum,cout);input a,bz cin;output sum,cout;reg sum, cout;

5、 /在always块中被賦值的变量应定狡为reg型reg ml,m2,m3;always (a or b or cin)b eginsum =(a a b) a cin;ml = a& b;m2 = b& cin;m3 = a& cin;cout =end(ml|m2)|m3;endmodule40 b(o5um 0sum ijsum 3sum 2【例9】结构描述的4位级连全加器include n full_addl.vnmodule add4_l(sum,cout,a,b,cin);output3:0 sum;output cout;input3:0 j a,b;in

6、put cin;full_addl f0 (a 0 , b 0 , oinz sum0 , cinl) ; /级连描述full._addl fl (al ,bl , oinl, suml ,cin2);full._addl f2 (a2 zb2 z cin2z sum 2 , cin3);full._addl f 3 (a 3, b 3, cin3, sum3 , cout);endmodule【例10】数据流描述的4位全加器module add4_2 (cout, sum, a,output3:0 sum;output cout;input3:0 a,b;input cin;assign (

7、cout,sum=a+b+cin; endmodule【例11】行为描述的4位全加器 module add4_3(cout,sum,a,bz cin); output3:0 sum;output cout;input3:0 a,b;input cin;reg3:0 sum;reg cout;always (a or b or cin)b egincout,sum=a+b+cin;end endmodule【例12】非流水线方式8位全加器module adder8(cout,sum,inaz inb,cin,elk); output7:0 sum;output cout;input7:0 ina

8、,inb;input cin,elk;reg7:0 tempa,tempb,sum;reg cout;reg tempc;always (posedge elk)b egintempa=ina; tempb=inb; tempc=cin; /输入数据锁存endalways (posedge elk)b egincout,sum=tempa+tempb+tempc;endendmodulea一位全加器3-第2级数据锁存第2级数据倾存一位全加器位全加器i位全加器【例13】4级流水方式的8位全加器module pipeline(cout,sum,ina,inb,cin,elk);output7:0

9、sum;output cout;input7:0 ina,inb;input cinz elk;reg(7:0 tempa,tempb,sum;reg tempci,firstcoz secondco,thirdco,cout;reg1:0 firsts,thirda,thirdb;reg3:0 seconds,secondb,seconds;reg5:0 firsta,firstb,thirds;always (posedge elk)begintempa=ina; tempb=inb; tempci=cin; /输入数据缓存endalways (posedge elk)beginfirst

10、co,firsts=tempa1:0+tempb1:0+tempci;/第一级加(低2位)firsta=tempa 7:2; /未参加计算的数据缓存firstb=tempb7:2;endalways (posedge elk)beginsecondco,seconds = firsta1:0+f irstb1:0+firstco,firsts;/第二级加(第2、3位相加)seconda=f irsta 5:2 ; /数据缓存secondb=firstb5:2;endalways (posedge elk)beginthirdco,thirds=seconda1:0+secondb1:0+sec

11、ondco,seconds;/第三级加(第4、5位相加)thirda=seconda 3:2; /数据缓存thirdb=secondb3:2;endalways (posedge elk)begincout,sum=thirda1:0+thirdb1:0+thirdco,thirds;/第四级加(高两位相加)endendmodule【例14】用函数实现简单的处理器module mpc(instr,out);input 17:0 instr; /instr 为扌俞入的指令output 8:0 out; /输出纟吉果reg8:0 out;reg func;reg7:0 opl, op2; /从指令

12、中提取的两个操作数function 16:0 code_add; /函数的定狡input17:0 instr;reg add_func;reg7:0 code,oprl,opr2;begincode=instr 17:16 ; /输入指令instr的高2位是操作码 oprl = instr 7:0; /输入指令instr的低8位是操作数oprl case(code)2fb00:beginadd_func=l;opr2=instr15:8; /从instr 中取第二个操作数end2fb01:beginadd_func=0;opr2=instr15:8; /从instr 中取第二个操作数end2f

13、bl0:beginadd_func=l;opr2=8,dl; /第二个操作数取为1,实现+1操作enddefault:b eginadd_func=o;opr2=8'dl; /实现-1 操作endendcasecode_add=add_funcr opr2r oprl;endendfunctionalways (instr)begin func, op2z opl =code_add (instr) ; /调用函数if (func=l) out=opl+op2; /实现两数相加、操作数1加.操作 else out=opl-op2; /实现两数相减、操作数1减1操作endendmodule【例15】微处理器的测试代码、timescale 10ns/lns、include ,mpc. vumodule mpc_tp;reg17:0 instr;wire8:0 out;parameter dely=10;mpc ml (instr, out) ; /调用待测试模块initial begininstr=181do;#dely instr=18 oo.oloollol.oolollll;#dely instr=18fb00_11001101_ll101111;#dely instr=18fb01_01001101_l1101111;#dely i