实验五 数字时钟的设计

1、 实验五 数字时钟的设计实验性质：综合性 实验级别： 开课单位：信息与通信工程学院通信工程系 学时：4学时一、实验目的：1、学习用vhdl语言实现比较大型的电路的方法。 2、继续巩固cpld技术层次化设计方法。二、实验器材：计算机、quartus ii软件三、实验内容：设计一数字时钟，要求具有时、分、秒、计数显示功能，以24小时循环计时；具有清零，调节小时，分钟功能；具有整点报时功能。四、实验步骤：1、根据电路特点，用层次设计的概念，将此任务分成若干模块，规定每一模块的功能和各模块之间的接口。让几个学生分作和调试其中之一，然后再将各模块合起来联试。以培养学生之间的合作精神，同时加深层次化设计概

2、念。2、了解软件的元件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一设计，如何融合。3、模块说明： 各种进制的计数及时钟控制模块（10进制、6进制、24进制） 扫描分时显示，译码模块 各模块都用vhdl语言编写五、实验模块：秒模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport(clk, reset,setmin : instd_logic;enmin : outstd_logic;da0out: out std_logic_vector (

3、6 downto 0);end entity second;architecture fun of second issignal count: std_logic_vector( 6 downto 0);begin da0out <= count; process ( clk , reset , setmin) begin - enmin<=k; if (reset='0') then count <= "0000000" elsif (setmin='0') then enmin <= clk; elsif (cl

4、k 'event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#60#) then if (count="1011001") then enmin<='1' count<="0000000" else count<=count+7; end if; else count<="0000000" end if; elsif (count < 16#60#)

5、then count <= count+1; enmin<='0' after 100 ns; else count<="0000000" end if; end if; end process;end fun;分析： 脉冲从0计数至59，向前进1，enmin由低电平变至高电平。分模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute isport(clk, reset,sethour : instd_logic;enh

6、our : outstd_logic;da1out: out std_logic_vector (6 downto 0);end entity minute;architecture fun of minute issignal count: std_logic_vector( 6 downto 0);begin da1out <= count; process ( clk , reset , sethour) begin - enmin<=k; if (reset='0') then count <= "0000000" elsif (s

7、ethour='0') then enhour <= clk; elsif (clk 'event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#60#) then if (count="1011001") then enhour<='1' count<="0000000" else count<=count+7; end if; else count<=&

8、quot;0000000" end if; elsif (count < 16#60#) then count <= count+1; enhour<='0' after 100 ns; else count<="0000000" end if; end if; end process;end fun;分析： 脉冲从0计数至59，向前进1，enhour由低电平变至高电平。时模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;en

9、tity hour isport(clk, reset,setweek : instd_logic;enweek : outstd_logic;da2out: out std_logic_vector (6 downto 0);end entity hour ;architecture fun of hour issignal count: std_logic_vector( 6 downto 0);begin da2out <= count; process ( clk , reset , setweek) begin - enmin<=k; if (reset='0&#

10、39;) then count <= "0000000" elsif (setweek='0') then enweek <= clk; elsif (clk 'event and clk='1') then if (count(3 downto 0)="1001") then if (count <16#23#) then if (count="00100011") then enweek<='1' count<="0000000&quo

11、t; else count<=count+7; end if; else count<="0000000" end if; elsif (count < 16#23#) then count <= count+1; enweek<='0' after 100 ns; else count<="0000000" end if; end if; end process;end fun;分析： 脉冲从0计数至23，复位从0重新开始。显示模块低位显示数码管library ieee;use ieee.std_lo

12、gic_1164.all;entity shumaguan is port(a:in std_logic_vector (6 downto 0); y:out std_logic_vector (6 downto 0); end shumaguan;architecture beh of shumaguan isbegin process (a) begin case a(3 downto 0) is when "0000"=>y<="1111110" when "0001"=>y<="0110000

13、" when "0010"=>y<="1101101" when "0011"=>y<="1111001" when "0100"=>y<="0110011" when "0101"=>y<="1011011" when "0110"=>y<="1011111" when "0111"=>y<=&

14、quot;1110000" when "1000"=>y<="1111111" when "1001"=>y<="1111011" when others=>y<="0000000" end case; end process; end beh;高位显示数码管library ieee;use ieee.std_logic_1164.all;entity shumaguanhigh is port(a:in std_logic_vector (6 do

15、wnto 0); y:out std_logic_vector (6 downto 0); end shumaguanhigh;architecture beh of shumaguanhigh isbegin process (a) begin case a(6 downto 4) is when "000"=>y<="1111110" when "001"=>y<="0110000" when "010"=>y<="1101101" w

16、hen "011"=>y<="1111001" when "100"=>y<="0110011" when "101"=>y<="1011011" when others=>y<="0000000" end case; end process; end beh; 小时高位显示数码管library ieee;use ieee.std_logic_1164.all;entity shumaguanhour is

17、port(a:in std_logic_vector (6 downto 0); y:out std_logic_vector (6 downto 0); end shumaguanhour;architecture beh of shumaguanhour isbegin process (a) begin case a(6 downto 4) is when "000"=>y<="1111110" when "001"=>y<="0110000" when "010"

18、=>y<="1101101" when others=>y<="0000000" end case; end process; end beh;分析： 将8421bcd码转化成7段码。 整点报时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std

19、_logic_vector(6 downto 0); speak:out std_logic);end entity speaker;architecture fun of speaker isbeginprocess(clk,speakmin)begin if(clk 'event and clk='1')then if(speakmin="0000000" and speaksec="0000000")then speak<='1'else speak<='0'end if; end

20、 if;end process;end fun;分析： 当时钟计数到整点，即秒和分都等于0时蜂鸣器报警，以实现整点报时功能。输入：clk计数时钟信号，speaksec秒输出信号，speakmin分输出信号输出：报警信号输出转换模块1. 六转一library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;- uncomment the following lines to use the declarations that are- provided fo

21、r instantiating xilinx primitive components.-library unisim;-use unisim.vcomponents.all;entity sixtozero is port ( d:in std_logic_vector(6 downto 0); out6 : out std_logic; out5 : out std_logic; out4 : out std_logic; out3 : out std_logic; out2 : out std_logic; out1 : out std_logic; out0 : out std_log

22、ic); end sixtozero;architecture behavioral of sixtozero isbeginprocess(d)beginout6<=d(6);out5<=d(5); out4<=d(4); out3<=d(3); out2<=d(2); out1<=d(1); out0<=d(0);end process;end behavioral;2. 二转一3. library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_

23、logic_unsigned.all;- uncomment the following lines to use the declarations that are- provided for instantiating xilinx primitive components.-library unisim;-use unisim.vcomponents.all;entity twotozero is port ( d:in std_logic_vector(2 downto 0); out2 : out std_logic; out1 : out std_logic; out0 : out std_logic);end twotozero;architecture behavioral of twotozero isbeginprocess(d)begin out2<=d(2); out1<=d(1);