数字模块实例-Verilog

1、一、加、减法器21、半加器22、全加器23、串行进位加法器（行波进位加法器）44、超前进位加法器（先行进位加法器）45、进位链加法器、跳跃进位加法器76、进位旁路加法器、线性进位选择加法器等97、减法器9二、乘法器101、定点原码乘法器102、加法树乘法器123、查找表乘法器134、布尔乘法器14三、CORDIC数字计算机18四、Johnson计数器21五、移位寄存器221、串并转换模块222生成伪随机数及伪随机序列应用设计243桶形移位寄存器（循环移位寄存器）27六、编码译码器291、差错控制编码292、HDB3编码与译码373曼彻斯特编译码器39RS（204,188）译码器464、Gray

2、码与二进制码的转换465、NRZI编码46七、加密解密模块481、DES加密模块48一、加、减法器1、半加器半加器：输入为两个二进制数，输出产生两个二进制数，一个和位、一个进位，不包括来自低位的进位。逻辑表达式为：，其电路符号为：2、全加器在将两个多位二进制数相加时，除了最低位以外，每一位都应该考虑来自低位的进位，这种运算为全加，其电路为全加器。逻辑表达式为： 电路图：由半加器组成的结构如下： Verilog模型或3、串行进位加法器（行波进位加法器）依次将低位全加器的进位输出端CO接到高位全加器的进位输入端CI，就可以构成多位加法器。/ 二进制行波进位加法器module ripple_carr

3、y_adder(x, y, cin, sum, cout);parameterN = 8;inputcin;input N-1:0 x, y;output N-1:0sum;outputcout;regcout;reg N-1:0sum;reg qN:0;always (x or y or cin)begin:ADDERinteger i;q0 = cin;for(i=0; i<=N-1; i=i+1)beginqi+1 = (xi&yi) | (xi&qi) | (yi&qi);sumi = xi yi qi;endcout = qN;endendmodule4

4、、超前进位加法器（先行进位加法器）产生进位输出的情况是AB=1、A+B=1且CI=1，则得：即高位的进位输入不用等到低位计算完后就可得到，提高了计算速度，其电路结构如下：其电路符号Verilog描述： GP生成器：使用两个一位加法器与一个生成器设计两位的超前进位加法器同样可以进行继续扩展5、进位链加法器、跳跃进位加法器module carry_chain_adder(x, y, cin, sum, cout);parameterDSIZE = 8;inputcin;input DSIZE-1:0 x, y;output DSIZE-1:0sum;outputcout;regcout, qDSI

5、ZE:0, pDSIZE-1:0, gDSIZE-1:0;reg DSIZE-1:0sum;always (x or y or cin)begin:ADDERinteger i;q0 = cin;for(i=0; i<DSIZE; i=i+1)beginpi = xiyi;gi = yi;qi+1 = (pi)?qi:gi;sumi = piqi;endcout = qDSIZE;endendmodule/ 二进制跳跃进位加法器module carry_skip_adder(x_in, y_in, c_in, sum, c_out);parameterDSIZE = 12;paramet

6、erS = 4;inputc_in;input DSIZE-1:0 x_in, y_in;output DSIZE-1:0sum;reg DSIZE-1:0 sum;outputc_out;regc_out;integer i, j;reg DSIZE:0 q;always (x_in or y_in or c_in)beginq0 = c_in;begincarry_skip_add_cell(x_inS-1:0, y_inS-1:0,q0, qS:1);for(j=0; j<=S-1; j=j+1)sumj = x_inj y_inj qj;carry_skip_add_cell(x

7、_in2*S-1:S, y_in2*S-1:S,qS, q2*S:S+1);for(j=0; j<=S-1; j=j+1)sumS+j = x_inS+j y_inS+j qS+j;carry_skip_add_cell(x_in3*S-1:2*S, y_in3*S-1:2*S,q2*S, q3*S:2*S+1);for(j=0; j<=S-1; j=j+1)sum2*S+j = x_in2*S+j y_in2*S+j q2*S+j;endc_out = qDSIZE;end/ S比特分组进位链task carry_skip_add_cell;input S-1:0 x, y;in

8、put cin;output S:1 cout;regqS:0, pS-1:0, gS-1:0, accumulator, generalized_p;integer i;beginq0 = cin;for(i=0; i<=S-1; i=i+1)beginpi = xiyi;gi = yi;qi+1 = (pi)?qi:gi;endaccumulator = p0;for(i=1; i<=S-1; i=i+1)accumulator = accumulator & pi;generalized_p = accumulator;coutS = (generalized_p)

9、? c_in : qS;for(i=1; i<=S-1; i=i+1)couti = qi;endendtaskendmodule6、进位旁路加法器、线性进位选择加法器等7、减法器Verilog模型如下：二、乘法器1、定点原码乘法器乘数与被乘数分别载入两个寄存器R1与R2中。此外，还有一个寄存器A，A的初始值为0。运算时，控制逻辑每次读乘数的一位。若R1的最低位为1，则被乘数与A寄存器相加，并将结果存于A寄存器。然后，A、R1这两个寄存器整体右移一位，A的最高位变成0，且A0进入R1的最高位，而R1的最低位丢弃。若R1的最低位是0，则只需进行移位，不进行加法。产生的2n位乘积存于A与R1

10、寄存器中。32位定点原码一位乘法流程图如下：Verilog 参考代码：module mult(start,resten,x,y,z,);inputresten;inputstart;reg busy;input 2:0x;input2:0y;output 5:0 z; reg 5:0 z; reg2:0 reg_x; reg2:0 reg_y; reg3:0 A; reg2:0 temp_x;integeri;always(x or y or resten or start)beginif(!resten)beginA= 4'b0;reg_x = 3'b0;reg_y = 3&

11、#39;b0;temp_x= 3'b0;z= 6'b0;busy= 0;endelse if(start) beginreg_x = x;reg_y = y;busy= 1;A=4'b0; endelse beginif(busy)for (i=0;i<3;i=i+1) beginif(yi)temp_x = x;else temp_x = 3'b000;A=A+1'b0,temp_x;reg_y=A0,reg_y2:1;A=A>>1;endz=A,reg_y;busy=0;endendendmodule2、加法树乘法器module a

12、dd_tree_mult (out,a,b,clk);output15:0 out;input7:0 a,b;input clk;wire15:0 out;wire14:0 out1,c1;wire12:0 out2;wire10:0 out3,c2;wire8:0 out4;reg14:0 temp0;reg13:0 temp1;reg12:0 temp2;reg11:0 temp3;reg10:0 temp4;reg9:0 temp5;reg8:0 temp6;reg7:0 temp7;function7:0 mux8_1; input7:0 operand;input sel;begin

13、mux8_1= (sel) ? (operand) : 8'b00000000; endendfunctionalways (posedge clk)begintemp7<=mux8_1(a,b0);temp6<=(mux8_1(a,b1)<<1);temp5<=(mux8_1(a,b2)<<2);temp4<=(mux8_1(a,b3)<<3);temp3<=(mux8_1(a,b4)<<4);temp2<=(mux8_1(a,b5)<<5);temp1<=(mux8_1(a,b6)

14、<<6);temp0<=(mux8_1(a,b7)<<7);endassign out1 = temp0 + temp1;assignout2 = temp2 + temp3; assignout3 = temp4 + temp5;assignout4 = temp6 + temp7;assign c1 = out1 + out2;assign c2 = out3 + out4;assign out = c1 + c2;endmodule3、查找表乘法器查找表乘法器是将乘积直接存放在存储器中，将操作数作为地址访问存储器，得到的输出数据就是乘法器的结果。查找表乘法器

15、的速度只局限于所使用存储器的存取速度。module lookup_mult(out,a,b,clk);output7:0 out;input3:0 a,b;input clk;reg7:0 out;reg1:0 firsta,firstb;reg1:0 seconda,secondb;wire3:0 outa,outb,outc,outd;always (posedge clk) beginfirsta = a3:2; seconda = a1:0;firstb = b3:2; secondb = b1:0;endlookup m1(outa,firsta,firstb,clk), m2(ou

16、tb,firsta,secondb,clk), m3(outc,seconda,firstb,clk), m4(outd,seconda,secondb,clk);always (posedge clk)beginout = (outa << 4) + (outb << 2) + (outc << 2) + outd;endendmodulemodule lookup(out,a,b,clk);output3:0 out;input1:0 a,b;input clk;reg3:0 out;reg3:0 address;always (posedge clk)

17、begin address = a,b; case(address) 4'h0 : out = 4'b0000;4'h1 : out = 4'b0000;4'h2 : out = 4'b0000;4'h3 : out = 4'b0000;4'h4 : out = 4'b0000;4'h5 : out = 4'b0001;4'h6 : out = 4'b0010;4'h7 : out = 4'b0011;4'h8 : out = 4'b0000;4

18、9;h9 : out = 4'b0010;4'ha : out = 4'b0100;4'hb : out = 4'b0110;4'hc : out = 4'b0000;4'hd : out = 4'b0011;4'he : out = 4'b0110;4'hf : out = 4'b1001;default : out='bx; endcaseendendmodule4、布尔乘法器Booth算法通过以移位代替某些运算来提高乘法的运算速度。Booth算法是补码乘法的算法，基本公式为：X

19、*Y补=X补*Yn-1Yn-2.Y0-X补*Yn。公式说明如果乘数为正，则将乘数的尾数与被乘数相乘即可，如果乘数为负，那么在乘法运算之后，还要再减去被乘数才能得到最后的乘积。公式变形为X*Y补=X补*2n(Yn-1-Yn)+2n-1(Yn-2-Yn-1)+20(0-Y0)。从变形公式中可以看出，如果在乘数Y的末位Y0之后再增设一个附加位Y-1，其初始值为0，对乘数Y的值并无影响，则（Yi-1,Yi）X补就是每一次的部分积，该部分的位权就是2i。这种方法即为补码一位乘，即每次只处理一位乘数。运算流程：乘数与被乘数分别载入Q和M寄存器内，同时，还有一个1位寄存器，位于Q寄存器最低位Q0的右边，成为

20、Q。乘法的结果出现在A和Q寄存器中。A与Q初始值为0。控制逻辑也是每次扫描乘数的一位，但同时它也要检查右边的一位。若两位相同，则A、Q和Q寄存器的所有位向右移一位。若两位不同，则根据两位是1-0还是0-1，决定被乘数加到A寄存器，还是有A寄存器减去被乘数，加减之后再右移一位。也就是说，右移总是要进行的。右移是A,Q,Q的右移且是算术右移（算术移位：算术左移时，右端（低位）补0，左端（高位）部分舍去；右移保证符号位不改变）。设计流程图为：示例：Verilog 示例代码：module booth_mult(product,ready,word1,word2,start,clock,reset);p

21、arameter L_word=4;parameter L_brc=2;parameter All_Ones=4'b1111;parameter All_Zeros=4'b0000;output 2*L_word-1:0product;output ready;input L_word-1:0word1,word2;input start,clock,reset;wire load_words,shift,add,sub,ready;wire L_brc-1:0brc;Datapath_Booth m1(product,m0,word1,word2,load_words,shi

22、ft,add,sub,clock,reset);Controller_Booth m2(load_words,shift,add,sub,read,m0,start,clock,reset);endmodule/控制模块module Controller_Booth(load_words,shift,add,sub,ready,m0,start,clock,reset);parameter L_word=4;parameter L_state=4;parameter L_brc=2;output load_words,shift,add,sub,ready;input start,clock,

23、reset;input m0;reg L_state-1:0state,nextstate;parameter S_idle=0,S_1=1,S_2=2,S_3=3,S_4=4,S_5=5,S_6=6,S_7=7,S_8=8;reg load_words,shift,add,sub;wire ready=(state=S_idle)&&!reset)|(state=S_8);reg m0_del;wire L_brc-1:0brc=m0,m0_del;always(posedge clock or posedge reset)if(reset)state<=S_idle;

24、else state<=nextstate;always(posedge clock or posedge reset)if(reset)m0_del<=0;else if(load_words)m0_del<=0;else m0_del<=m0;always(state or start or brc)beginload_words=0;shift=0;add=0;sub=0;case(state)S_idle: if(start)begin load_words<=1;nextstate<=S_1;end else nextstate<=S_idl

25、e;S_1: if(brc=0)|(brc=3)begin shift=1;nextstate<=S_3;end else if(brc=1)begin add=1;nextstate<=S_2;end else if(brc=2)begin sub=1;nextstate<=S_2;endS_3: if(brc=0)|(brc=3)begin shift=1;nextstate<=S_5;end else if(brc=1)begin add=1;nextstate<=S_4;end else if(brc=2)begin sub=1;nextstate<

26、=S_4;endS_5: if(brc=0)|(brc=3)begin shift=1;nextstate<=S_7;end else if(brc=1)begin add=1;nextstate<=S_6;end else if(brc=2)begin sub=1;nextstate<=S_6;endS_7: if(brc=0)|(brc=3)begin shift=1;nextstate<=S_8;end else if(brc=1)begin add=1;nextstate<=S_8;end else if(brc=2)begin sub=1;nextsta

27、te<=S_8;endS_2: begin shift=1;nextstate=S_3;endS_4: begin shift=1;nextstate=S_5;endS_6: begin shift=1;nextstate=S_7;endS_8: if(start) begin load_words=1;nextstate=S_1;end else nextstate=S_8;default:nextstate=S_idle;endcaseendendmodule/数据路径模块module Datapath_Booth(product,m0,word1,word2,load_words,

28、shift,add,sub,clock,reset);parameter L_word=4;output 2*L_word-1:0product;output m0;input L_word-1:0word1,word2;input load_words,shift,add,sub,clock,reset;reg 2*L_word-1:0product,multiplicand;reg L_word-1:0mult;wire m0=mult0;parameter All_Ones=4'b1111;parameter All_Zeros=4'b0000;always(posedg

29、e clock or posedge reset)beginif(reset)begin mult<=0;multiplicand<=0;product<=0;endelse if(load_words)beginif(word1L_word-1=0)multiplicand<=word1;else multiplicand<=All_Ones,word1L_word-1:0;mult<=word2;product=0;endelse if(shift)beginmult<=mult>>1;multiplicand<=multipli

30、cand<<1;endelse if(add)begin product<=product+multiplicand;endelse if(sub)begin product<=product-multiplicand;endendendmodule三、CORDIC数字计算机module cordic(clk, phi, cos, sin);parameter W = 13, W_Z = 14;input clk;input W_Z-1:0 phi;outputW-1:0 cos, sin;reg W-1:0 cos, sin;reg W-1:0 x8:0, y8:0;

31、reg W_Z-1:0 z7:0;always (posedge clk)beginx0 <= 13'h4D; / 修正CORDIC算法的比例因子，An的倒数y0 <= 13'h00;z0 <= phi;/ 旋转45度if(z0W_Z-1) begin x1 <= x0 + y0;y1 <= y0 - x0;z1 <= z0 + 14'h65;endelse begin x1 <= x0 - y0;y1 <= y0 + x0;z1 <= z0 - 14'h65;end/ 旋转26.57度if(z1W_Z-1)

32、begin x2 <= x1 + 1y1W-1, y1W-1:1;y2 <= y1 - 1x1W-1, x1W-1:1;z2 <= z1 + 14'h3B;endelse begin x2 <= x1 - 1y1W-1, y1W-1:1;y2 <= y1 + 1x1W-1, x1W-1:1;z2 <= z1 - 14'h3B;end/ 旋转14.04度if(z2W_Z-1)begin x3 <= x2 + 2y2W-1, y2W-1:2;y3 <= y2 - 2x2W-1, x2W-1:2;z3 <= z2 + 14'

33、;h1F;endelse begin x3 <= x2 - 2y2W-1, y2W-1:2;y3 <= y2 + 2x2W-1, x2W-1:2;z3 <= z2 - 14'h1F;end/ 旋转7.13度if(z3W_Z-1)begin x4 <= x3 + 3y3W-1, y3W-1:3;y4 <= y3 - 3x3W-1, x3W-1:3;z4 <= z3 + 14'h10;endelse begin x4 <= x3 - 3y3W-1, y3W-1:3;y4 <= y3 + 3x3W-1, x3W-1:3;z4 <=

34、 z3 - 14'h10;end/ 旋转3.58度if(z4W_Z-1)begin x5 <= x4 + 4y4W-1, y4W-1:4;y5 <= y4 - 4x4W-1, x4W-1:4;z5 <= z4 + 14'h8;endelse begin x5 <= x4 - 4y4W-1, y4W-1:4;y5 <= y4 + 4x4W-1, x4W-1:4;z5 <= z4 - 14'h8;end/ 旋转1.79度if(z5W_Z-1)begin x6 <= x5 + 5y5W-1, y5W-1:5;y6 <= y5 -

35、 5x5W-1, x5W-1:5;z6 <= z5 + 14'h4;endelse begin x6 <= x5 - 5y5W-1, y5W-1:5;y6 <= y5 + 5x5W-1, x5W-1:5;z6 <= z5 - 14'h4;end/ 旋转0.90度if(z6W_Z-1)begin x7 <= x6 + 6y6W-1, y6W-1:6;y7 <= y6 - 6x6W-1,x6W-1:6;z7 <= z6 + 14'h2;endelse begin x7 <= x6 - 6y6W-1, y6W-1:6;y7 &l

36、t;= y6 + 6x6W-1, x6W-1:6;z7 <= z6 - 14'h2;end/ 旋转0.45度if(z7W_Z-1)begin x8 <= x7 + 7y7W-1, y7W-1:7;y8 <= y7 - 7x7W-1, x7W-1:7;endelse begin x8 <= x7 - 7y7W-1, y7W-1:7;y8 <= y7 + 7x7W-1, x7W-1:7;endcos <= x8;sin <= y8;endendmodule四、Johnson计数器Johnson计数器的行为类似链波计数器，但不同于链波计数器的异步特性

37、。Johnson计数器为一种同步计数器，它的特性是每次只变化一个位，类似格雷码，且Johnson计数器有最精简的组合逻辑电路。综合以上两点，Johnson计数器是节省功率消耗的计数器，不过Johnson计数器在高数值计数时会使用更多位而显得不经济，图为电路结构：代码：module johnson(/inputclk,nrst,start, /outputcntr);inputclk,nrst,start;output 3:0cntr;reg3:0cntr;always(posedge clk or negedge nrst)if(nrst) cntr <= 0;else if(start

38、) begincntr3:1 <=cntr2:0;cntr0 <=cntr3;endendmodule五、移位寄存器1、串并转换模块当移位使能为真时，在每个移位时钟，移位比特移入移位寄存器2生成伪随机数及伪随机序列应用设计define bw 8define tap88b1000_1110module lfsr(/inputclk,nrst,oen,/outputdout);input clk,nrst;input oen;output bw-1:0 dout;parameter bw-1:0 taps=tap8;integer i;reg 7:0 pre_lfst;reg 7:0

39、lfst_reg;wire b0=lfsr_regbw-1|lfsr_regbw-2:0;always (posedge clk or negedge nrst)if(nrst) lfsr_reg <= 0;else if (oen)beginbeginfor (i=0;i<=(bw-2);i=i+1)beginif(tapsi)pre_lfsri+1=lfsr_regib0;else pre_lfsri+1=lfsr_regi;endpre_lfsr0=b0;endlfsr_reg <= pre_lfsr;endwire 7:0 dout=lfst_reg;endmodul

40、e3桶形移位寄存器（循环移位寄存器）桶形移位寄存器所占的面积较大，但是如果某个应用需要大量的多位比特移位，则采用桶形移位寄存器还是有必要的，即循环移位寄存器。如果load有效，则输入data_in输出到data_out，不执行任何操作；如果右移位控制信号rshift_ctrl有效，则输出数据data_out右移位；如果左移位控制信号lshift_ctrl有效，则输出数据data_out左移位；移位的个数由shiftnum来决定；整个设计为同步设计，一切操作均在时钟clk的上升沿执行。Verilog 代码实例：module barrel_shift(inputclk,inputload,inpu

41、trshift_ctrl,inputlshift_ctrl,input2:0shiftnum,inputbit_in,input7:0data_in,output reg7:0data_out);always(posedge clk)beginif(load)data_out<=data_in;elseif(rshift_ctrl)begincase(shiftnum)3'h0:data_out<=data_in;3'h1:data_out<=bit_in,data_out7:1;3'h2:data_out<=bit_in,bit_in,data

42、_out7:2;3'h3:data_out<=bit_in,bit_in,bit_in,data_out7:3;3'h4:data_out<=bit_in,bit_in,bit_in,bit_in,data_out7:4;3'h5:data_out<=bit_in,bit_in,bit_in,bit_in,bit_in,data_out7:5;3'h6:data_out<=bit_in,bit_in,bit_in,bit_in,bit_in,bit_in,data_out7:6;3'h7:data_out<=bit_in,b

43、it_in,bit_in,bit_in,bit_in,bit_in,bit_in,data_out7;endcaseendelseif(lshift_ctrl)begincase(shiftnum)3'h0:data_out<=data_out;3'h1:data_out<=data_out6:0,bit_in;3'h2: data_out<=data_out5:0,bit_in,bit_in;3'h3:data_out<=data_out4:0,bit_in,bit_in,bit_in;3'h4:data_out<=dat

44、a_out3:0,bit_in,bit_in,bit_in,bit_in;3'h5:data_out<=data_out2:0,bit_in,bit_in,bit_in,bit_in,bit_in;3'h6:data_out<=data_out1:0,bit_in,bit_in,bit_in,bit_in,bit_in,bit_in;3'h7:data_out<=data_out0,bit_in,bit_in,bit_in,bit_in,bit_in,bit_in,bit_in;endcaseendendendmodule六、编码译码器1、差错控制编码

45、1）奇偶校验、奇偶发生器在原始数据字节的最高位增加一个附加比特位，使结果中1的个数为奇数（奇校验）或偶数（偶校验）。增加的位称为奇偶校验位。奇偶校验只能检测出奇数个比特位错，对偶数个比特位错则无能为力。发送时，该模块在发送数据后加一个奇校验位；接受时，进行校验端口说明如下对于奇校验核心代码为：Pa_out=data_in7 data_in6 data_in5 data_in4 data_in3 data_in2 data_in1 data_in0 1b1;对于偶校验，核心代码为：Pa_out=data_in7 data_in6 data_in5 data_in4 data_in3 data_i

46、n2 data_in1 data_in0;Verilog代码实例，能够产生同时能够校验moduleparity_check(input7:0data_in,inputpa_in,/ 输入的校验位inputeven_odd,/控制信号，选择奇还是选择偶outputpa_out,/产生的奇偶校验位outputerror/校验结果);assignpa_out = even_odd?data_in:data_in;assignerror = even_odd?data_in,pa_in:data_in,pa_in;endmodule2）汉明码编码解码汉明码是一种能纠正单比特差错的线性分组码。设线性分组

47、码（n,k）,有k个信息位，r=n-k个监督位，为了能确定n种位置上的差错及线性无差错，要求r的值为2r-r>=k+1。在汉明码中，比特位从最左边（位号为1）开始编号。位号为2的幂的位（1,2,4,8等）是r个监督位（汉明码比特），其余位是k个信息位。汉明码码位排列如下：用S1、S2、S3、S4表示在这四个校验关系中的校验子，如下关系：表中可得校验关系为故监督位为：接收端收到每个码组后，先按校验关系计算出S1、S2、S3和S4，再按表排毒按错码情况。模2加求和如下：解码按码为1的位的码位号表示成二进制码，再按模2加求和：b为解码无错，C为有错。Verilog 代码实例：1、编码器：接受的

48、输入数据为8位，产生的码位为4位，汉明码码位排列如下：112：ham_out3:2,D7, ham_out1,D6,D5,D4, ham_out0,D3,D2,D1,D0,P1=ham_out 3,P2=ham_out2, P3=ham_out1, P4=ham_out0moduleham_en(/编码完成后最终的汉明码码位号112为/ham_out3:2,data_in7,ham_out1,data_in6:4,ham_out0,data_in3:0input7:0data_in,output3:0ham_out);assignham_out3= data_in7data_in1data_i

49、n3 data_in6data_in4;assignham_out2= data_in7data_in1 data_in5data_in4data_in2;assignham_out1= data_in6data_in0 data_in5data_in4;assignham_out0= data_in1data_in0 data_in2data_in3;2、解码器：由接受的输入数据重新产生纠错码，并与原纠错码异或，得到校验子，如果相同，则得到0，不同则为1.Verilog实现代码为：moduleham_dec(/编码排列：码位112：P1P2D7P3D6D5D4P4D3D2D1D0:h3h2D7h1D6D5D4h0D3D2D1D0in