数字逻辑实验报告

1、北京邮电大学数字电路与逻辑设计实验报告实验题目：掷骰子游戏电路的设计与实现学生姓名： 班级：学号： 序号：目录一、 设计课题的任务要求二、 系统设计三、 仿真波形及波形分析四、 源程序五、 功能说明及资源利用情况六、 故障及问题分析七、 总结和结论一、 设计课题的任务要求设计并实现一个掷骰子游戏电路。 基本要求： 1、 电路可供甲乙二人游戏，游戏者甲使用的按键为 BTN0，游戏者乙使用的按键为 BTN1。2、 每按一次按键，代表掷一次骰子，可随机得到 16 范围内的两个数字。 3、 甲乙按键产生的随机数字分别用数码管 DISP0-DISP1、DISP2-DISP3 显示,并用 DISP7 显示

2、比赛局数，比赛结束用 8×8 点阵显示获胜方，并伴有声音效果。4、 具体游戏规则如下： （1） 第一局比赛，甲乙依次各按一次按键，按键所得两数之和为7或11者胜；若无 人取胜，则进行第二局比赛； （2） 第二局比赛，甲乙每人各按一次按键，按键所得二数之和与第一局比赛相同者获 胜，若无人获胜，则进行第三局比赛，重复进行步骤（2），直到出现胜者为止。 （3） 游戏局数最多进行六局。在第六局比赛时，若重复进行步骤（2）仍未出现胜者， 以按键所得两数之和最大者为获胜方。 提高要求： 1、 增加多人游戏的功能，数码管可分时记录显示每个游戏者的骰子点数。 2、 点阵显示增加游戏开机动画、结束动画

3、，并伴有乐曲播放。 3、 自拟其它功能。二、系统设计1、设计思路：按照实验要求，使用状态机分别表示游戏的不同状态；使用分频器来控制时钟；控制器实现具体的游戏规则；8*8LED点阵来显示胜负；数码管显示局数和甲乙掷出的随机数；随机数用一到六的循环产生。在编译时采用元件例化来生成各自的模块。流程图如下 显示2、总体框图：控制器分频器防抖器输入3、分块设计：分别包括分频器、防抖器、随机数的产生、判断器、译码器和显示器等模块，综合起来实现所要求的功能。分频器：防抖器：随机数的产生： 判断器： 译码器： 显示器：三、 仿真波形及波形分析根据甲先乙后的顺序进行仿真如下：从仿真中可以看出随机数的产生，若时间

4、轴向后移可以将游戏看得更加清楚。四、 源程序分频器：library ieee;use ieee.std_logic_1164.all;entity fenpingqi is port (clk:in std_logic;clktmp:out std_logic); end fenpingqi;architecture a of fenpingqi is signal tmp: integer range 0 to 499:=0;signal clktmp1: std_logic;beginp3:process(clk) -frequent timebeginif clk'event a

5、nd clk='1'thenif tmp=499 then tmp<=0;clktmp1<= not clktmp1;elsetmp<=tmp+1;end if;end if;end process p3;clktmp<=clktmp1;end a ;防抖器：library ieee;use ieee.std_logic_1164.all;entity fangdouqi is port (clk,btn1, btn2 :in std_logic; btn1_en,btn2_en :out std_logic); end fangdouqi;archit

6、ecture a of fangdouqi is signal tempcount1:integer range 0 to 5 :=0;signal tempcount2:integer range 0 to 5 :=0;begin p5:process(clk,btn1,btn2) beginif clk'event and clk='1' thenif btn1='1' thenif tempcount1=5 then tempcount1<=tempcount1;else tempcount1<=tempcount1+1; end if

7、;if tempcount1=4 then btn1_en<='1'else btn1_en<='0'end if;else tempcount1 <=0; end if;if btn2='1' thenif tempcount2=5 then tempcount2<=tempcount2;else tempcount2<=tempcount2+1; end if;if tempcount2=4 then btn2_en<='1'else btn2_en<='0'end i

8、f;else tempcount2 <=0; end if;end if;end process p5;end a;计数器library ieee;use ieee.std_logic_1164.all;entity jishuqi is port (clktmp:in std_logic; randnum2:out integer range 1 to 12; randnum :out integer range 1 to 12); end jishuqi;architecture a of jishuqi issignal randnum1: integer range 1 to 1

9、2;signal randnum3: integer range 1 to 12;beginp4:process(clktmp) -counter1 beginif clktmp'event and clktmp='1' thenif randnum1= 6 thenrandnum1<=1;elserandnum1<=randnum1+1;end if;if randnum3= 7 thenrandnum3<=1;elserandnum3<=randnum3+1;end if;end if;if randnum3=7 thenrandnum2&l

10、t;=1;elserandnum2<=randnum3;end if;randnum<=randnum1;end process p4;end a;掷骰子结果的产生：library ieee;use ieee.std_logic_1164.all;entity creaters is port (clk:in std_logic;clktmp:in std_logic;btn1_en,btn2_en :in std_logic;randnum,randnum1:in integer range 1 to 12;count:in integer range 0 to 5;sgn11,

11、sgn22 :out std_logic;a1,a2,b1,b2:out integer range 1 to 12;a3,a4,b3,b4:out integer range 1 to 12); end creaters;architecture a of creaters is signal a11,a22,b11,b22: integer range 1 to 12:=1;signal a33,a44,b33,b44: integer range 1 to 12;signal sgn1,sgn2:std_logic:='0'beginp1:process (a11,a22

12、,a33,sgn1,sgn2,b11,b22,b33,btn1_en,btn2_en,clktmp)begin if clktmp'event and clktmp='1'thenif sgn1='1'and sgn2='1'thensgn1<='0'sgn2<='0' end if;if btn1_en='1' and sgn1='0' thensgn1<='1'a11<=randnum;-get rand num;a22<=r

13、andnum1;a33<=randnum1+randnum;if count=0 thena44<=randnum1+randnum;end if;end if;if btn2_en='1' and sgn1='1'and sgn2='0' thensgn2<='1'b11<=randnum;b22<=randnum1;b33<=randnum1+randnum;if count=0 thenb44<=randnum1+randnum;end if;end if; end if;a1<

14、;=a11;a2<=a22;a3<=a33;b1<=b11;b2<=b22;b3<=b33;a4<=a44;b4<=b44;sgn11<=sgn1;sgn22<=sgn2;end process p1; end a ;判断器：library ieee;use ieee.std_logic_1164.all;entity panduanqi is port (sgn1,sgn2 :in std_logic; clk:in std_logic; a3,a4,b3,b4: in integer range 1 to 12; disp77: out

15、 integer range 1 to 6; count1:out integer range 0 to 5; winsgn :out std_logic_vector(1 downto 0); end panduanqi; architecture a of panduanqi is signal count : integer range 0 to 5:=0;signal disp7 : integer range 0 to 5:=1; begin p7:process(clk,a3,a4,b3,b4,sgn1,sgn2) -judgmentbeginif clk'event an

16、d clk='1' thenif sgn1='1'and sgn2='1'then 规定甲先掷乙后掷if count=0 then if (a3=11 or a3=7) then winsgn<="10" disp7<=disp7+1 ;count<=0;elsif (b3=11 or b3=7) then winsgn<="01" disp7<=disp7+1 ;count<=0;else count<=count+1;end if; elsif count=5

17、then if (a3=11 or a3=7 ) then winsgn<="10" elsif (b3=11 or b3=7) then winsgn<="01"elsif a3>b3 then winsgn<="10"else winsgn<="01"end if; disp7<=disp7+1 ;count<=0;else if a3=a4 then winsgn<="10"disp7<=disp7+1 ;count<=0;els

18、if b3=b4 then winsgn<="01"disp7<=disp7+1 ;count<=0;else count<=count+1;end if;end if;end if;end if;count1<=count;if (disp7=7)thendisp77<=1;elsedisp77<=disp7;end if;end process p7;end a;译码器：library ieee;use ieee.std_logic_1164.all;entity yimaqi is port (clktmp:in std_lo

19、gic; a1,a2,b1,b2:in integer range 1 to 12; disp7: in integer range 1 to 6; num : out std_logic_vector(6 downto 0); cat : out std_logic_vector(5 downto 0); end yimaqi; architecture a of yimaqi is signal tempcat: std_logic_vector(5 downto 0); signal tempnum: integer range 0 to 6:=1; signal num1: std_l

20、ogic_vector(6 downto 0);signal cycle :integer range 0 to 4:=0; begin p6:process(clktmp) -translate the num1 to right num;beginif clktmp'event and clktmp='1' thenif(cycle=4)thencycle<=0;elsecycle<= cycle+1;end if;end if;case cycle iswhen 0 => tempnum<=a1; tempcat<="111

21、110"when 1 => tempnum<=a2;tempcat<="111101"when 2 => tempnum<=b1;tempcat<="111011"when 3 => tempnum<=b2;tempcat<="110111"when 4 => tempnum<=disp7;tempcat<="011111"end case;case tempnum iswhen 0=>num1<="111111

22、0"when 1=>num1<="0110000"when 2=>num1<="1101101"when 3=>num1<="1111001"when 4=>num1<="0110011"when 5=>num1<="1011011"when 6=>num1<="1011111"end case;num<=num1;cat<=tempcat;end process p6; end a

23、;显示器：library ieee;use ieee.std_logic_1164.all;entity xianshiqi is port (clk:in std_logic;winsgn: in std_logic_vector(1 downto 0);row: out std_logic_vector(7 downto 0);col: out std_logic_vector(7 downto 0); end xianshiqi;architecture a of xianshiqi is signal cyc :integer range 0 to 7:=0;signal row1 :

24、std_logic_vector(7 downto 0);signal col1 :std_logic_vector(7 downto 0);begin p8:process(clk)begin if clk'event and clk='1' thenif cyc=7 thencyc<=0;elsecyc<=cyc+1; end if;if winsgn="10"thencase cyc is when 0=>row1<="01111111"col1<="01111100"whe

25、n 1=>row1<="10111111"col1<="01010100"when 2=>row1<="11011111"col1<="01111100"when 3=>row1<="11101111"col1<="01010100"when 4=>row1<="11110111"col1<="01111100"when 5=>row1<="1

26、1111011"col1<="00010000"when 6=>row1<="11111101"col1<="00010000"when 7=>row1<="11111110"col1<="00010000"end case;elsif winsgn= "01"thencase cyc is when 0=>row1<="01111111"col1<="11111111&quo

27、t;when 1=>row1<="10111111"col1<="01000000"when 2=>row1<="11011111"col1<="00100000"when 3=>row1<="11101111"col1<="00010000"when 4=>row1<="11110111"col1<="00001000"when 5=>row1<="11111011"col1<="00000100"when 6=>row1<="11111101"col1<="10000010"when 7=>row1&l