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1、目录一、设计要求:1二、设计方案:1三、执行过程:21、顶层文件程序JTKZQ22、交通控制模块JTDKZ63、显示控制模块XIANSHIKZ84、译码器程序模块YMQ85、5s计时译码模块CNT05S106、25s计时译码模块CNT25S117、45s计时译码模块CNT45S138、2位二进制计数器COUNT2159、四选一数据选择器SHUX1610、设定管脚1711、下载程序1812、电路实物图18四、实验分析:19五、实验感想19六、参考文献19交通灯控制器一、设计要求:设计一个由一条主干道和一条支干道的十字路口的交通灯控制器,具体要求如下:1、 主、支干道各设有一个绿、黄、红指示灯,2

2、个显示数码管。2、 主干道处于常允许通行状态,而支干道有车来才允许通行。当主干道允许通行亮绿灯时,支干道亮红灯。当支干道允许通行亮绿灯时,主干道亮红灯。3、 当主、支干道均有车时,两者交替允许通行,主干道每次放行45s,支干道每次放行25s,由亮绿灯变成亮红灯转换时,先亮5s的黄灯作为过渡,并进行减计时显示。二、设计方案:1、 基本原理:交通灯是城市交通中不可缺少的重要工具,是城市交通秩序的重要保障。本实例就是实现一个常见的十字路通灯功能。读者通过学习这个交通灯控制器,可以实现一个更加完整的交通灯。例如实现实时配置各种灯的时间,手动控制各个灯的状态等。一个十字路口的交通一般分为两个方向,每个方

3、向具有红灯、绿灯和黄灯3种,可以为每一个灯的状态设置一个初始值,灯状态改变后,开始按照这个初始值倒计时。倒计时归零后,灯的状态将会改变至下一个状态。值得注意的是,交通灯两个方向的灯的状态是相关的。也就是说,每个方向的灯的状态影响着另外一个方向的灯的状态,这样才能够协调两个方向的车流。如果每个方向的灯是独立变化的,那么交通灯就没有了意义。2、设计框图:状态转移图模块结构图交通灯控制器原理框图包括置数模块、计数模块、主控制模块和译码器模块。置数模块将交通灯的点亮时间预置到置数电路中,计数模块以秒为单位倒计时,当计数值减为零时,主控电路改变输出状态,电路进入下一个状态的倒计时。其中,主控制模块是核心

4、部分。三、执行过程:1、顶层文件程序JTKZQlibrary ieee;use ieee.std_logic_1164.all;entity JTKZQ isPORT(CLK,CLK1,SM,SB:IN STD_LOGIC; MR,MYO,MGO,BR,BYO,BGO:OUT STD_LOGIC;DOUT1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);SEL:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);end ENTITY JTKZQ;architecture ART of JTKZQ isCOMPONENT JTDKZ ISPORT(CLK,SM,

5、SB:IN STD_LOGIC; MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);END COMPONENT JTDKZ;COMPONENT XIANSHIKZ IS PORT(EN45,EN25,EN05M,EN05B:IN STD_LOGIC; AIN45M,AIN45B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT XIA

6、NSHIKZ;COMPONENT CNT25S ISPORT(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT CNT25S;COMPONENT CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT CNT45S;COMPONENT CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LO

7、GIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END COMPONENT CNT05S;COMPONENT YMQ ISPORT(AIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT YMQ;COMPONENT COUNT2 IS PORT(CLK:IN STD_LOGIC; S1:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); END COMPONENT COUNT2;COMPONENT SHUX IS

8、 PORT(I0,I1,I2,I3:IN STD_LOGIC_VECTOR(6 DOWNTO 0); S:IN STD_LOGIC_VECTOR(1 DOWNTO 0); CHU:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT SHUX;-END COMPONENT;-COMPONENT CSKZ IS-PORT(INA:IN STD_LOGIC;- OUTA:OUT STD_LOGIC);-END COMPONENT CSKZ;SIGNAL EN1,EN2,EN3,EN4:STD_LOGIC;SIGNAL S45M,S45B,S05,S25M,S

9、25B:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL YM1,YM2,YM3,YM4:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL IN_A,IN_B,IN_C,IN_D,IN_E:STD_LOGIC_VECTOR(6 DOWNTO 0);SIGNAL IN_F:STD_LOGIC_VECTOR(1 DOWNTO 0);beginU1:JTDKZ PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,MR=>MR,MY0=>EN2,MG0=>EN1,BR=>BR,BY0=>EN4,BG

10、0=>EN3);-U2:CSKZ PORT MAP(INA=>EN1,OUTA=>MG);-U3:CSKZ PORT MAP(INA=>EN2,OUTA=>MY);-U4:CSKZ PORT MAP(INA=>EN3,OUTA=>BG);-U5:CSKZ PORT MAP(INA=>EN4,OUTA=>BY);U6:CNT45S PORT MAP(CLK=>CLK,SB=>SB,EN45=>EN1,DOUT45M=>S45M,DOUT45B=>S45B);U7:CNT05S PORT MAP(CLK=>C

11、LK,EN05M=>EN2,DOUT5=>S05,EN05B=>EN4);U8:CNT25S PORT MAP(CLK=>CLK,SM=>SM,SB=>SB,EN25=>EN3,DOUT25M=>S25M,DOUT25B=>S25B);U9:XIANSHIKZ PORT MAP(EN45=>EN1,EN05M=>EN2,EN25=>EN3,EN05B=>EN4, AIN45M=>S45M,AIN45B=>S45B,AIN25M=>S25M,AIN25B=>S25B,AIN05=>S05,

12、 DOUTM(3 DOWNTO 0)=>YM1,DOUTM(7 DOWNTO 4)=>YM2, DOUTB(3 DOWNTO 0)=>YM3,DOUTB(7 DOWNTO 4)=>YM4);U10:YMQ PORT MAP(AIN4=>YM1,DOUT7=>IN_A);U11:YMQ PORT MAP(AIN4=>YM2,DOUT7=>IN_B);U12:YMQ PORT MAP(AIN4=>YM3,DOUT7=>IN_C);U13:YMQ PORT MAP(AIN4=>YM4,DOUT7=>IN_D);U14:SHUX

13、PORT MAP(IN_A,IN_B,IN_C,IN_D,IN_F,IN_E); U15:COUNT2 PORT MAP (CLK1,IN_F);MYO<=EN2;MGO<=EN1;BYO<=EN4;BGO<=EN3;DOUT1<=IN_E;SEL<=IN_F;end ARCHITECTURE ART;2、交通控制模块JTDKZLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JTDKZ IS PORT(CLK,SM,SB:IN STD_LOGIC; MR,MY0,MG0,BR,BY0,BG0:OUT STD_L

14、OGIC);END ENTITY JTDKZ;ARCHITECTURE ART OF JTDKZ IS TYPE STATE_TYPE IS(A,B,C,D); SIGNAL STATE:STATE_TYPE; BEGIN CNT:PROCESS(CLK)IS VARIABLE S:INTEGER RANGE 0 TO 45; VARIABLE CLR,EN:BIT; BEGIN IF(CLK'EVENT AND CLK='1')THEN IF CLR='0'THEN S:=0; ELSIF EN='0'THEN S:=S; ELSE S

15、:=S+1; END IF; CASE STATE IS WHEN A=>MR<='0'MY0<='0'MG0<='1'BR<='1'BY0<='0'BG0<='0' IF(SB AND SM)='1' THEN IF S=45 THEN STATE<=B;CLR:='0'EN:='0' ELSE STATE<=A;CLR:='1'EN:='1' END IF; EL

16、SIF(SB AND(NOT SM)='1'THEN STATE<=B;CLR:='0'EN:='0' ELSE STATE<=A;CLR:='1'EN:='1' END IF; WHEN B=>MR<='0'MY0<='1'MG0<='0'BR<='1'BY0<='0'BG0<='0' IF S=5 THEN STATE<=C;CLR:='0'

17、EN:='0' ELSE STATE<=B;CLR:='1'EN:='1' END IF; WHEN C=>MR<='1'MY0<='0'MG0<='0'BR<='0'BY0<='0'BG0<='1' IF(SM AND SB)='1'THEN IF S=25 THEN STATE<=D;CLR:='0'EN:='0' ELSE STATE<=C

18、;CLR:='1'EN:='1' END IF; ELSIF SB='0' THEN STATE<=D;CLR:='0'EN:='0' ELSE STATE<=C;CLR:='1'EN:='1' END IF; WHEN D=>MR<='1'MY0<='0'MG0<='0'BR<='0'BY0<='1'BG0<='0' IF S=5 T

19、HEN STATE<=A;CLR:='0'EN:='0' ELSE STATE<=D;CLR:='1'EN:='1' END IF; END CASE; END IF;END PROCESS CNT;END ARCHITECTURE ART;3、显示控制模块XIANSHIKZLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XIANSHIKZ IS PORT(EN45,EN25,EN05M,EN05B:IN S

20、TD_LOGIC; AIN45M,AIN45B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); AIN25M,AIN25B,AIN05:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTM,DOUTB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END XIANSHIKZ;ARCHITECTURE ART OF XIANSHIKZ IS BEGIN PROCESS(EN45,EN25,EN05M,EN05B) IS BEGIN IF EN45='1' THENDOUTM<=AIN45M(7 DOWNTO 0

21、);DOUTB<=AIN45B(7 DOWNTO 0); ELSIF EN05M='1' THEN DOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0); ELSIF EN25='1' THEN DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0); ELSIF EN05B='1' THENDOUTM<=AIN05(7 DOWNTO 0);DOUTB<=AIN05(7 DOWNTO 0); END IF; EN

22、D PROCESS;END ARCHITECTURE ART;4、译码器程序模块YMQLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY YMQ IS PORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END ENTITY YMQ; ARCHITECTURE ART OF YMQ IS BEGIN PROCESS(AIN4) IS BEGIN CASE (AIN4) IS -WHEN "0000"=>DOUT

23、7<="1000000" -WHEN "0001"=>DOUT7<="1111001" -WHEN "0010"=>DOUT7<="0100100" -WHEN "0011"=>DOUT7<="0110000" -WHEN "0100"=>DOUT7<="0011001" -WHEN "0101"=>DOUT7<="001

24、0010" -WHEN "0110"=>DOUT7<="0000010" -WHEN "0111"=>DOUT7<="1111000" -WHEN "1000"=>DOUT7<="0000000" - WHEN "1001"=>DOUT7<="0010000" -WHEN OTHERS=>DOUT7<="1111111" WHEN "00

25、00"=>DOUT7<="0111111" WHEN "0001"=>DOUT7<="0000110" WHEN "0010"=>DOUT7<="1011011" WHEN "0011"=>DOUT7<="1001111" WHEN "0100"=>DOUT7<="1100110" WHEN "0101"=>DOUT7&l

26、t;="1101101" WHEN "0110"=>DOUT7<="1111101" WHEN "0111"=>DOUT7<="0000111" WHEN "1000"=>DOUT7<="1111111" WHEN "1001"=>DOUT7<="1101111" WHEN OTHERS=>DOUT7<="0000000" END CAS

27、E; END PROCESS; END ARCHITECTURE ART;5、5s计时译码模块CNT05SLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT05S ISPORT(CLK,EN05M,EN05B:IN STD_LOGIC; DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT05S;ARCHITECTURE ART OF CNT05S IS SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0);

28、BEGIN PROCESS(CLK,EN05M,EN05B)IS BEGIN IF(CLK'EVENT AND CLK='1')THEN IF EN05M='1'THEN CNT3B<=CNT3B+1; ELSIF EN05B='1'THEN CNT3B<=CNT3B+1; ELSIF EN05B='0'THEN CNT3B<=CNT3B-CNT3B-1; END IF; END IF; END PROCESS; PROCESS(CNT3B) BEGIN CASE CNT3B IS WHEN"0

29、00"=>DOUT5<="00000101" WHEN"001"=>DOUT5<="00000100" WHEN"010"=>DOUT5<="00000011" WHEN"011"=>DOUT5<="00000010" WHEN"100"=>DOUT5<="00000001" WHEN OTHERS=>DOUT5<="0000

30、0000" END CASE; END PROCESS;END;6、25s计时译码模块CNT25SLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT25S IS PORT(SB,SM,CLK,EN25:IN STD_LOGIC; DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY CNT25S;ARCHITECTURE ART OF CNT25S IS SIGNAL CNT5B:STD_LOGIC_VE

31、CTOR(4 DOWNTO 0); BEGINPROCESS(SB,SM,CLK,EN25)ISBEGIN IF SB='0'THEN CNT5B<=CNT5B-CNT5B-1; ELSIF SM='0'THEN CNT5B<=CNT5B-CNT5B-1; ELSIF(CLK'EVENT AND CLK='1')THEN IF EN25='1'THEN CNT5B<=CNT5B+1; ELSIF EN25='0'THEN CNT5B<=CNT5B-CNT5B-1; END IF; E

32、ND IF; END PROCESS; PROCESS(CNT5B)IS BEGIN CASE CNT5B IS WHEN"00000"=>DOUT25B<="00100101"DOUT25M<="00110000" WHEN"00001"=>DOUT25B<="00100100"DOUT25M<="00101001" WHEN"00010"=>DOUT25B<="00100011"DOU

33、T25M<="00101000" WHEN"00011"=>DOUT25B<="00100010"DOUT25M<="00100111" WHEN"00100"=>DOUT25B<="00100001"DOUT25M<="00100110" WHEN"00101"=>DOUT25B<="00100000"DOUT25M<="00100101&quo

34、t; WHEN"00110"=>DOUT25B<="00011001"DOUT25M<="00100100" WHEN"00111"=>DOUT25B<="00011000"DOUT25M<="00100011" WHEN"01000"=>DOUT25B<="00010111"DOUT25M<="00100010" WHEN"01001"=&g

35、t;DOUT25B<="00010110"DOUT25M<="00100001" WHEN"01010"=>DOUT25B<="00010101"DOUT25M<="00100000" WHEN"01011"=>DOUT25B<="00010100"DOUT25M<="00011001" WHEN"01100"=>DOUT25B<="0001001

36、1"DOUT25M<="00011000" WHEN"01101"=>DOUT25B<="00010010"DOUT25M<="00010111" WHEN"01110"=>DOUT25B<="00010001"DOUT25M<="00010110" WHEN"01111"=>DOUT25B<="00010000"DOUT25M<="00

37、010101" WHEN"10000"=>DOUT25B<="00001001"DOUT25M<="00010100" WHEN"10001"=>DOUT25B<="00001000"DOUT25M<="00010011" WHEN"10010"=>DOUT25B<="00000111"DOUT25M<="00010010" WHEN"1001

38、1"=>DOUT25B<="00000110"DOUT25M<="00010001" WHEN"10100"=>DOUT25B<="00000101"DOUT25M<="00010000" WHEN"10101"=>DOUT25B<="00000100"DOUT25M<="00001001" WHEN"10110"=>DOUT25B<=&qu

39、ot;00000011"DOUT25M<="00001000" WHEN"10111"=>DOUT25B<="00000010"DOUT25M<="00000111" WHEN"11000"=>DOUT25B<="00000001"DOUT25M<="00000110" WHEN OTHERS=>DOUT25B<="00000000"DOUT25M<="00

40、000000"END CASE;END PROCESS;END;7、45s计时译码模块CNT45SLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT45S IS PORT(SB,CLK,EN45:IN STD_LOGIC; DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END CNT45S;ARCHITECTURE ART OF CNT45S IS SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOW

41、NTO 0); BEGIN PROCESS(SB,CLK,EN45) IS BEGIN IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1; ELSIF(CLK'EVENT AND CLK='1')THEN IF EN45='1'THEN CNT6B<=CNT6B+1; ELSIF EN45='0'THEN CNT6B<=CNT6B-CNT6B-1; END IF;END IF;END PROCESS;PROCESS(CNT6B)ISBEGINCASE CNT6B ISWHEN&quo

42、t;000000"=>DOUT45M<="01000101"DOUT45B<="01010000"WHEN"000001"=>DOUT45M<="01000100"DOUT45B<="01001001"WHEN"000010"=>DOUT45M<="01000011"DOUT45B<="01001000"WHEN"000011"=>DOUT45M&

43、lt;="01000010"DOUT45B<="01000111"WHEN"000100"=>DOUT45M<="01000001"DOUT45B<="01000110"WHEN"000101"=>DOUT45M<="01000000"DOUT45B<="01000101"WHEN"000110"=>DOUT45M<="00111001"DOU

44、T45B<="01000100"WHEN"000111"=>DOUT45M<="00111000"DOUT45B<="01000011"WHEN"001000"=>DOUT45M<="00110111"DOUT45B<="01000010"WHEN"001001"=>DOUT45M<="00110110"DOUT45B<="01000001&quo

45、t;WHEN"001010"=>DOUT45M<="00110101"DOUT45B<="01000000"WHEN"001011"=>DOUT45M<="00110100"DOUT45B<="01101001"WHEN"001100"=>DOUT45M<="00110011"DOUT45B<="00111000"WHEN"001101"=&g

46、t;DOUT45M<="00110010"DOUT45B<="00110111"WHEN"001110"=>DOUT45M<="00110001"DOUT45B<="00110110"WHEN"001111"=>DOUT45M<="00110000"DOUT45B<="00110101"WHEN"010000"=>DOUT45M<="0010100

47、1"DOUT45B<="00110100"WHEN"010001"=>DOUT45M<="00101000"DOUT45B<="00110011"WHEN"010010"=>DOUT45M<="00100111"DOUT45B<="00110010"WHEN"010011"=>DOUT45M<="00100110"DOUT45B<="00

48、110001"WHEN"010100"=>DOUT45M<="00100101"DOUT45B<="00110000"WHEN"010101"=>DOUT45M<="00100100"DOUT45B<="00101001"WHEN"010110"=>DOUT45M<="00100011"DOUT45B<="00101000"WHEN"01011

49、1"=>DOUT45M<="00100010"DOUT45B<="00100111"WHEN"011000"=>DOUT45M<="00100001"DOUT45B<="00100110"WHEN"011001"=>DOUT45M<="00100000"DOUT45B<="00100101"WHEN"011010"=>DOUT45M<=&qu

50、ot;00011001"DOUT45B<="00100100"WHEN"011011"=>DOUT45M<="00011000"DOUT45B<="00100011"WHEN"011100"=>DOUT45M<="00010111"DOUT45B<="00100010"WHEN"011101"=>DOUT45M<="00010110"DOUT45B<

51、;="00100001"WHEN"011110"=>DOUT45M<="00010101"DOUT45B<="00100000"WHEN"011111"=>DOUT45M<="00010100"DOUT45B<="00011001"WHEN"100000"=>DOUT45M<="00010011"DOUT45B<="00011000"WHEN&

52、quot;100001"=>DOUT45M<="00010010"DOUT45B<="00010111"WHEN"100010"=>DOUT45M<="00010001"DOUT45B<="00010110"WHEN"100011"=>DOUT45M<="00010000"DOUT45B<="00010101"WHEN"100100"=>DOUT4

53、5M<="00001001"DOUT45B<="00010100"WHEN"100101"=>DOUT45M<="00001000"DOUT45B<="00010011"WHEN"100110"=>DOUT45M<="00000111"DOUT45B<="00010010"WHEN"100111"=>DOUT45M<="00000110"DOUT45B<="00010001"WHEN"101000"=>DOUT45M<="00000101"DOUT45B<="00010000"WHEN"101001"=>DOUT45M<="00000100"DOUT45B<="

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