分享豪威精选笔试题

1、分享豪威精选笔试题1 logic design1.supposedly there is acombinational circuit between two registersdriven by a clock.what will you do if the delay of the combinationalcircuit is greater than the clock signal?a.to reduce clock frequency b.to increase clock frequencyc.to make it pipelining d to make it multi_cy

2、cle2 .there is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at 80mhz.the inputdata is a fix pattern .800 input clocks carry in800 datacontinuously,and the other 200 clocks carry in no data.how big the fifoshould be in order to avoid data o

3、ver/under_run?please select theminimum depth below to meet the requirement.a.160 b.200 c.800 d .10003 .which of the follow circuits can generate gitch free gated_clk?a.always(posedgeclk) gatedassign gated_clk=gatedclk;b.always(negedgeclk) gated assign gated_clk=gated7clk;c.always(posedgeclk)gatedass

4、igngated_clk=gated卜clk;d.always(negedgeclk) gatedassigngated_clk=gated卜clk;4 .you re working on a specification of a system with some digitalparameters.each parameter has min,typ and max columns.which columnwould you put setup and hold time?a.setup time in max,hold time in minb.setup time in min,hol

5、d time in maxc.both in maxd.both in min5 .there are 3 ants at 3corners of a triangle. they randomly startmoving towards another corner.what is the probability that won tcollide?a.0b.1/8c/1/4d.1/36 .if you look at a clock and the time is 3:15.what is angle between the hour and the minute hand?a.0b.36

6、0/483.360/12d.360/47.how many times per day a clock s hands overlap?a.11b.22c.24d.268.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q=1ns.whatis the max clock frequency the circuit can handle?a.200mhzb.250mhzc.500mhzd.1ghz2.physical design1 .before tape-out,which routine check should be performed fo

7、r your layout database in 0.18 um process?a.drcb.lvsc.drc antennae.simulation2 .how to fix antenna effect?a.make the wire wider and shorterb.change lower metal to upper metalc.connect with diode of metal and diffusiond.change upper metal to lower metale.b c3 .please expain lvsa.logic versus schemati

8、cb.layout versus schematicc.layout via synthesisd.logic via synthesis4 .how to control clock skew?a.get balanced clock treeb.decrease the fanoutc.add clock buffer evenlyd.decrease clock latency5 .how to avoid hold_time violation?a.lower the clock speedb.the clock arrive laterc.the clock arrive earli

9、erd.the data arrive latere.the data arrive earlier6 .what kinds of factors reflect good floor plan?a.easy routingb.easy timing metc.enough power supplyd.a be.a b c7 .what cause cell delay?a.input-pin transition timeb.output-pin capacitance.c.output-pin resistanced.a be.b c8 .why need i/o pads for ea

10、ch chip?a.esd protectionb.voltage level shiftc.latch-up preventiond.a ce.a b c9 .which one is worse-case in 0.18um process?1.1.8v,25c2.1.98v,125c3.1.62v,-40c4.1.62v,125c5.1.98v,-40c10.if power plan is not good,what ll happen to the chip?a.hot-spotb.voltage dropc.timing not metd.routing is toughe.all

11、 of above3.architecture design1.1. ompare two images,the first image has a person in front of ablackboard in a classroom and the second image has a person in front ofa lush garden.the two images are compressed using the jpeg algorithm.a.the first image will have larger file size.b.the second image w

12、ill have a larger file size.2 .how would you round a 10b number,x,at the 3rd(上 角)bit?a.(x 2) 2.b.(x 3) 3.c.(x+4) 2) 2d.(x+4) 2) 3e.(x+8) 2) 3f.(x+8) 3) 33 .what happens if the number in 2 is negative?a ignoreb.make it absolute ,do the operation in 2,and add sign backc.none of the above4 .how would y

13、ou multiply a 4 in hardware?a.use 4 adders each is offset from the provious adder by 1bit.b.use a booth multip;ier with 4b coefficient.c.use wires.d.use a barrel shifter.5 .how would you design a barrel shifter?a.use multiple stages of 2 乘 2 multiplexersb.use a crossbar switch that can switch any inputs to anyoutputsc.use a clos networkd.have muxes to switch between all combinations of hardwired shif