EDA技术与应用讲义-第3章-原理图输入设计方法-QUARTUS-II版本PPT课件

1、2021/6/71 第第3章章 原理图输入设计方法原理图输入设计方法 Quartus II 版操作版操作 课程讲义课程讲义 上一章 下一章 2021/6/72 本章内容 v何时使用 原理图设计输入 v常用文件介绍 v设计步骤 v元件库 和 Altera 宏的使用 v如何将VHDL代码文件生成 图形 符号 2021/6/73 何时使用 原理图设计输入 ？ v符合 传统的 电路设计 习惯 v一般只是在 “top-level”(顶层)文件中使用？ 2021/6/74 Quartus II常用文件介绍 文件扩展名称用 途MAX+PLUS II 中的名称 .vhdVHDL代码源文件.vhd .bdf图形

2、输入源文件.gdf .qsf器件 引脚 与编译配置指 配文件 .qsf .pofCPLD,EEPROM 器件 编程文件 .pof .sofFPGA器件的SRAM 文件 配置 .sof 2021/6/75 一般步骤 v电路的模块划分 v设计输入 v器件和引脚指配 v编译与排错 v功能仿真和时序仿真 v编程与配置，设计代码的芯片运行 2021/6/76 电路的模块划分 v人工人工 根据电路功能 进行 模块划分模块划分 v合理的模块划分 关系到 电路的性能 实现的难易程度 v根据模块划分和系统功能 确定确定： PLD芯片型号芯片型号 模块划分后，就可以进行模块划分后，就可以进行 具体设计具体设计 了

3、了 2021/6/77 设计输入 一般EDA软件允许3种设计输入： HDL语言 电路图 1.波形输入 2021/6/78 图形设计输入的过程 + + 2021/6/79 图形设计:图元 2021/6/710 图形设计:端口 2021/6/711 如何编写一个新的图形文件？ vFILE-NEW出现以下对话窗，选择如下： 2021/6/712 如何调入元件？ vEdit-Insert Symbol 出现下面窗口 将将 自己编写的自己编写的 符号调入符号调入 从从 标准库中标准库中 调入调入 2021/6/713 将符号之间连线 2021/6/714 调入I/O端口元件符号 2021/6/715 2

4、类 标准库 vMegafunctions/LPM 宏模块 功能复杂、参数可设置的模块 vPrimitives 基本图元 简单的、功能固定的逻辑元件，不可调 整参数 2021/6/716 如何将VHDL设计编程Symbol vVHDL文件编译后，自动生成同名的符号文件 v符号文件的扩展名称（*.bsf） v调入过程如下： 2021/6/717 何为 ？ 器件和引脚指配 v器件指配 F为设计输入 选择合适的PLD器件型号 v何谓引脚指配 F将设计代码（图形）中的端口（端口（PORT） 和 PLD芯片的引脚芯片的引脚 （PIN） 对应起来的. v指配文件 FMAX+PLUS II： “ *.acf

5、” FQuartus II： “ *.qsf ” 2021/6/718 器件和引脚指配的方法 方法有2种 v在软件的菜单界 面中指配 1.修改指配文件 （是文本文件） 2021/6/719 菜单界面中 指 配 2021/6/720 修改指配文件 vCHIP io_2d_lock vBEGIN v|iVD :INPUT_PIN = 7; v|iHD :INPUT_PIN = 8; v|iDENA :INPUT_PIN = 6; v|iCLK : INPUT_PIN = 211; v|oCLK : OUTPUT_PIN = 237; v|oVD :OUTPUT_PIN = 234; v|oHD :

6、 OUTPUT_PIN = 233; v|oDENA :OUTPUT_PIN = 235; v. vDEVICE = EPF10K30AQC240-2; vEND; v. 2021/6/721 编译与排错 编译过程有2种，作用分别为： 语法编译：只是综合并输出网表 F编译设计文件，综合产生门级代码 F编译器只运行到综合这步就停止了 F编译器只产生估算的延时数值 完全的编译：包括编译，网表输出，综合，配置器件 F编译器除了完成以上的步骤，还要将设计配置到ALTERA的器件 中去 F编译器根据器件特性产生真正的延时时间和给器件的配置文件 2021/6/722 功能仿真和时序仿真 v仿真的概念： 在

7、设计代码下载到芯片前，在EDA软件中对设计的输 出进行波形仿真。 v常用的2种仿真模式 v功能仿真 对设计的逻辑功能进行仿真 v时序仿真 对设计的逻辑功能和信号的时间延时进行仿真。 v仿真前还要做的工作 输入信号的建立 Quartus II软件中软件中 关于仿真的原文关于仿真的原文 2021/6/723 2种 仿真文件 v矢量波形文件： v a Vector Waveform File (.vwf) v文本矢量文件 v a text-based Vector File (.vec), 2021/6/724 编程与配置 最后，最后， 如果仿真如果仿真 也正确也正确 的话，的话， 那我们就可以那我

8、们就可以 将设计代码将设计代码 配置或者编程配置或者编程 到到 芯片芯片 中了中了 v编程的文件类型 对于CPLD或者EPC2，ECS1等配置芯片，编程文件扩展名为： “ *.POF “ v配置的文件类型 对于FPGA芯片，配置文件扩展名为：“ *.SOF “ 2021/6/725 硬件设计和软件设计的时间协调 v软件模块划分，器件的初步信号确定（主要 是根据需要的I/O引脚的数量） v软件设计，硬件外围电路设计和器件选择 v软件仿真 v仿真完成后，器件信号的重新审核，进行硬 件电路图设计 v综合调试 v完成 2021/6/726 设计的几个问题 v如何组织多个设计文件的系统？，项目的概 念。

9、 v时钟系统如何设计？ v电路的设计功耗 v高速信号的软件和硬件设计 2021/6/727 The end. 2021/6/728 以下内容以下内容 为为 正文的引用，正文的引用， 可不阅读。可不阅读。 2021/6/729 常用EDA工具软件 vEDA软件方面，大体可以分为两类： PLD器件厂商提供的EDA工具。较著名的如： vAltera公司的 Max+plus II和Quartus II、 vXilinx公司的Foundation Series、 vLatice-Vantis公司的ispEXERT System。 第三方专业软件公司提供的EDA工具。常用的有： vSynopsys公司的F

10、PGA Compiler II、 vExemplar Logic公司的LeonardoSpectrum、 vSynplicity公司的Synplify。 1.第三方工具软件是对CPLD/FPGA生产厂家开发软件的补 充和优化，如通常认为Max+plus II和Quartus II对 VHDL/Verilog HDL逻辑综合能力不强，如果采用专用的 HDL工具进行逻辑综合，会有效地提高综合质量。 2021/6/730 ALTERA 公司的公司的EDA合作伙伴合作伙伴 2021/6/731 硬件描述语言：起源 v是电子电路的文本描述。 v最早的发明者：美国国防部，美国国防部，VHDL,1983 v

11、大浪淘沙，为大者二： VHDL 和 Verilog HDL v其他的小兄弟： ABEL、AHDL、System Verilog、System C。 2021/6/732 一个D触发器的VHDL代码例子 v- VHDL code position: p83_ex4_11_DFF1 v- v- LIBARY IEEE; v- USE IEEE.STD_LOGIC_1164.ALL; vENTITY DFF1 IS vPORT (CLK:INBIT; vD:INBIT; vQ:OUTBIT v); vEND ENTITY DFF1; vARCHITECTURE bhv OF DFF1 IS vBEG

12、IN vPROCESS(CLK) vBEGIN vIF CLKEVENT AND (CLK=1) AND ( CLKLAST_VALUE = 0) THEN v- 严格的CLK信号上升沿定义 vQ 2021/6/738 Compiler Netlist Extractor （编译器网表提取器）（编译器网表提取器） vThe Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename

13、(s) of the CNF(s) are based on the project name. Example vThe Compiler Netlist Extractor also creates a single HIF that documents the hierarchical connections between design files. vThis module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that

14、translate ADFs and SMFs for use with MAX+PLUS II. vDuring netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together. v返回 2021/6/739 Database Builder(数据库构建器 ): vThe Compiler module that builds a si

15、ngle, fully flattened project database that integrates all the design files in a project hierarchy. vThe Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the data

16、base as many times as it is used within the original hierarchical project. The database thus preserves the electrical connectivity of the project. vThe Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the full

17、y optimized project. In the beginning, the database contains only the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. vAs it creates the database, the Database Builder examines the logical comp

18、leteness and consistency of the project, and checks for boundary connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing. v返回 2021/6/740 Logic Synthesizer vThe Compiler module that sy

19、nthesizes the logic in a projects design files. vUsing the database created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. vFor projects that use JK or SR flipflops, the Logic Synthes

20、izer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly. vThe Logic Synthesizer also synthesizes equations for flipflops to implement state regi

21、sters of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the

22、 state machine. These encodings are chosen to minimize the resources used. v返回 2021/6/741 Fitter（适配器） vThe Compiler module that fits the logic of a project into one or more devices. vUsing the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the avai

23、lable resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate interconnection paths and pin assignments. vThe Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a

24、fit, the Fitter allows you to override some or all of your assignments or terminate compilation. vThe Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project com

25、piles successfully, the Fit File is overwritten. You can back- annotate the assignments in the file to preserve them in future compilations. v返回 2021/6/742 Timing SNF Extractor(时序SNF文件提取器) vThe Compiler module that creates a timing SNF containing the logic and timing information required for timing

26、simulation, delay prediction, and timing analysis. vThe Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). Th

27、e Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF Extractor. vA timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices

28、, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional tes

29、ting is available only for a single-device project. v返回 2021/6/743 Assembler（汇编器） vThe Compiler module that creates one or more programming files for programming or configuring the device(s) for a project. vThe Assembler module completes project processing by converting the Fitters device, logic cel

30、l, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX

31、8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Optio

32、ns dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After compilation, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu). vThe programm

33、ing files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several other programming hardware manufacturers also provide programming support for Altera devices. v返回 2021/6/744 Simulation Mode vFunctional Simulates the behavior of flattened n

34、etlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of logic level cha

35、nges, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). vTiming Uses a fully compile

36、d netlist that includes estimated or actual timing information. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec). This type of simulation also allows you t

37、o check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). vTiming using Fast Timing Model Performs a timing simulation using the Fa

38、st Timing Model to simulate fastest possible timing conditions with the fastest device speed grade 2021/6/745 Megafunctions/LPM vArithmetic Components vGates vI/O Components vMemory Compiler vParallel Flash Loader Megafunction vSignalTap II Logic Analyzer Megafunction 1.Storage Components 2021/6/746

39、 Arithmetic Components valtaccumulate divide* valtfp_add_sub lpm_abs valtfp_mult lpm_add_sub valtmemmult lpm_compare valtmult_accum lpm_counter valtmult_add lpm_divide valtsqrt lpm_mult 1.altsquare parallel_add 2021/6/747 Gates vbusmuxlpm_inv vlpm_andlpm_mux vlpm_bustri lpm_or vlpm_clshift lpm_xor vlpm_constant mux vlpm_decode 2021/6/748 I/O Components valtcdr_rxaltdqs valtcdr_tx altgxb valtclkctrl altlvds_rx valtclklock altlvds_tx valtddio_bidir altpll valtddio_in altpll_reconfig valtddio_out altremote_update valtdq altufm_osc v 2021/6/749 Memory Compiler valtcsmem