EDA数字钟设计

1、数字钟程序设计本设计在实验箱上验证，使用电路模式7，用动态扫描方式显示，“ds8使能”开关上推；动态位扫描时，时、分、秒之间间隔点亮；tmode：12/24进制模式切换，接键8；scan：动态扫描时钟信号，接clock0，跳线选16384hz；minute：分校时，接键1（单脉冲）；hour：小时时校时，接键4（单脉冲）；exchge：计时/校时切换，接键5；clk:：时钟脉冲，接clock2,跳线选1hz；ret：清零，接键7（单脉冲）；en：计数使能，接键3；clk1024：蜂鸣输入信号，接clock5,跳线选1024hz；sg6.0：段选信号，接pio49到pio43；bt7.0：位选信

2、号，接pio41到pio34；speaker：蜂鸣输出信号，接speaker。程序模块【1】60进制模块cnt60 library ieee; -clk时钟输入，ret清零，en计数使能，use ieee.std_logic_1164.all; - cql分或秒的个位输出，use ieee.std_logic_unsigned.all; -cqh分或秒的十位输出,entity cnt60 is - cout1进位输出port (clk,rst,en : in std_logic;cql: out std_logic_vector(3 downto 0);cqh: out std_logic_v

3、ector(3 downto 0);cout1 : out std_logic); -向外部的进位end cnt60;architecture behav of cnt60 issignal cqi0: std_logic_vector (3 downto 0);signal cqi1: std_logic_vector (3 downto 0);signal cout0 : std_logic; -低位向高位的进位begin process(clk,rst,en) -十进制beginif rst=1 then cqi0 0);elsif clkevent and clk=1 thenif e

4、n =1 thenif cqi0 9 then cqi0 =cqi0+1;else cqi0 0);end if;end if;if cqi0 = 9 then cout0 = 1;else cout0=0;end if;end if;end process;cql=cqi0;process(cout0,rst) -六进制beginif rst=1 then cqi1 0);elsif cout0event and cout0=1 thenif cqi15 then cqi1=cqi1+1;else cqi10);end if;if cqi1=5 and cqi0=9 then cout1=1

5、;else cout1=0;end if;end if;end process;cqh=cqi1;end behav;【2】24|12进制模块cnt24 library ieee; -clk输入分的进位信号，ret清零，en计数使能,use ieee.std_logic_1164.all; -mode为12和24进制的切换，use ieee.std_logic_unsigned.all; - cql小时的个位输出，cqh小时的十位输出entity cnt24 isport (clk,rst,en,mode: in std_logic;cql: out std_logic_vector(3 do

6、wnto 0);cqh: out std_logic_vector(3 downto 0);end cnt24;architecture behav of cnt24 issignal cqi0: std_logic_vector (3 downto 0);signal cqi1: std_logic_vector (3 downto 0);signal cqi2: std_logic_vector (3 downto 0);signal cqi3: std_logic_vector (3 downto 0); beginp1: process(clk,rst,en) -24进制模式 begi

7、n if rst=1 then cqi0 0);cqi1 0); elsif clkevent and clk=1 then if en =1 then if cqi12 then if cqi09 then cqi0=cqi0+1;else cqi00);cqi1=cqi1+1;end if;elsif cqi03 thencqi0=cqi0+1;else cqi00);cqi10); end if; end if; end if; end process p1; p2: process(clk,rst,en) -12进制模式 begin if rst=1 then cqi2 0);cqi3

8、 0); elsif clkevent and clk=1 then if en =1 then if cqi31 then if cqi29 then cqi2=cqi2+1;else cqi20);cqi3=cqi3+1;end if;elsif cqi22 thencqi2=cqi2+1;else cqi2=0001;cqi30);end if; end if; end if; end process p2; p3: process(mode) -mode=1为24进制，mode=0为12进制 begin case mode is when 1= cql=cqi0;cqh cql=cqi

9、2;cqhnull; end case; end process p3;end behav;【3】控制逻辑模块control library ieee; -exchge校时与计时模式控制，use ieee.std_logic_1164.all; -minute手动分校时use ieee.std_logic_unsigned.all; -hour手动时校时entity control is -cy0,cy1分别接受秒和分的进位信号port (minute,hour,exchge,cy0,cy1: in std_logic; -clk0,clk1分别控制分和小时的时钟脉冲clk0: out std

10、_logic;clk1: out std_logic);end control;architecture behav of control issignal a0: std_logic;signal a1: std_logic;beginp1: process(exchge,minute,hour) begin if exchge=1 then a0=minute; a1=hour; end if;end process p1;p2: process(exchge,cy0,cy1) -exchge=1校时模式，exchge=0为计时模式 begin if exchge=1 then clk0=

11、a0;clk1=a1; else clk0=cy0;clk1=cy1; end if;end process p2;end architecture behav;【4】动态扫描模块scan_led library ieee; -scan动态扫描时钟信号use ieee.std_logic_1164.all; -din接受时、分、秒数据use ieee.std_logic_unsigned.all; -sg输出段选信号entity scan_led is -输出位选信号 port(scan : in std_logic;din:in std_logic_vector(23 downto 0);s

12、g:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0);end;architecture one of scan_led is signal cnt6:std_logic_vector(2 downto 0); signal d:std_logic_vector(3 downto 0); beginp1:process(scan) begin if scanevent and scan=1 then if cnt65 then cnt6=cnt6+1; else cnt6 bt bt bt bt bt bt

13、null; end case;end process p2;p4: process(cnt6) begin case cnt6 iswhen000= d d d d d d null; end case; end process p4;p3:process(d) -段选 begin case d is when 0000 =sgsgsgsgsgsgsgsgsgsgnull; end case;end process p3;end architecture one;【5】整点报时模块alarmlibrary ieee;-ml输入分个位，mh输入分十位use ieee.std_logic_1164

14、.all; -sl输入秒个位，sh输入秒十位use ieee.std_logic_unsigned.all; -clk输入1024hz时钟脉冲entity alarm is -speaker输出报时信号 port (ml: in std_logic_vector(3 downto 0); mh: in std_logic_vector(3 downto 0); sl: in std_logic_vector(3 downto 0); sh: in std_logic_vector(3 downto 0);clk: in std_logic; speaker: out std_logic);en

15、d alarm;architecture behav of alarm issignal div2clk: std_logic;begin process(clk) begin -实验箱的可用时钟有限，1024hz作高音信号 if clkevent and clk=1 then -1024hz时钟脉冲2分频，产生蜂鸣低音信号 div2clk=not div2clk; end if; end process; process(mh,ml,sh,sl) begin if mh=5 and ml=9 then if sh=5 then if (sl=1 or sl=3 or sl=5 or sl=7

16、) then -51、53、55、57秒输出低音信号 speaker=div2clk; elsif (sl=9) then -59秒输出高音信号 speaker=clk; else speaker=0; end if; else speaker=0; end if; else speakerclk,rst=rst,en=en,cout1=m0, cqh=d(7 downto 4),cql=d(3 downto 0); u2: cnt60 port map(clk=m2,rst=rst,en=en,cout1=m1, cqh=d(15 downto 12),cql=d(11 downto 8); u3: cnt24 port map(clk=m3,rst=rst,en=en,mode=tmode, cqh=d(23 downto 20),cql=d(19 downto 16); u4: control port map(exchge=exchge,hour=hour,minute=minute, clk0=m2,clk1=m3,cy0=m0,cy1=m1); u5: scan_led port map(scan=scan,sg=sg,bt=bt, din(3 downto 0)=d(