智能小车毕业论文中英文资料外文翻译文献

1、 中英文资料外文翻译文献智能小车控制中模糊-pid控制的实现摘要：本文设计了一个自动智能小车控制系统和模糊-pid控制算法。 提出了一个设计模糊pid控制器的方案。通过matlab的仿真分析表明,模糊- pid控制算法的性能比一般的pid控制更好。智能小车的试验结果表明它会随黑色的引导线快速并且稳定的走完整个行程。关键词：模糊pid；智能小车；模糊控制器；模糊控制。 1简介近年来,许多国家正在研制无人驾驶的车辆技术。产生了许多新的理论和应用技术。文献1中提出了一个采用实时检测速度从而准确、动态改变小车转向的理论，从而实现转向完美特性的控制策略。文献2中采用边缘检测算法来提取道路信息，并采用了比

2、例控制。文献3提出了一种有效、具有良好抗干扰性的、适应性强的动态图像处理算法。这种算法有效的解决了由环境光线变化以及轨道变化所引起的小车偏离轨道现象。文献4利用非线性最优化重建了轨道和摄像调整间的空间关系，从而使它能够精确的测量出横向偏差。上述方案都从某种意义上改善了小车的性能，但他们都缺少以小车运动和大量实验为基础的小车的特性。这篇文章中提出了一个模糊控制算法以及模糊pid控制器的设计方法。在本文最后,给出了实验结果来证明模糊pid算法的有效性。2硬件系统设计要实现模糊pid控制算法的设计，有必要设计一个智能小车硬件系统。智能小车应该有由道路检测，转角检测，速度检测等构成的智能控制单元。详见

3、图1。图1 智能小车原理框图3模糊pid控制的基本原则用一般的pid控制算法来获得最好的响应是不容易的。因为参数kp、ki、kd不适应于不同的对象，或者同一个对象的不同状态。模糊控制是以模糊集合和模糊逻辑为机车的。不需要精确的数学模型，它可以由用经验建立起来的规则表来确定控制变量的大小。一般来说，模糊控制的输入变量基于系统的误差e和系统的误差变化量ec。这和比例微分控制相似。这样的控制可能可以获得较好的动态性能，但获得的静态性能不能让人满意。将模糊控制于pid控制结合起来，这就会使系统即具有模糊控制所具有的灵活的适应特性，又具有pid控制的所具有的较高的精确度。图2给出了模糊pid控制系统的结

4、构图，其中模糊控制器的作用是选择不同的pid参数来改善局部响应，进而改善整体的响应。图2 模糊pid控制仿真框图4模糊pid控制器的设计速度驱动电机控制器的设计和下面给出的转向机构控制器设计是相似的。模糊控制器由模糊化、模糊推理、去模糊化组成，这些都是以知识库为基础的。控制器输入为误差及误差变化量，输出为参数kp、ki、kd。假设误差e的模糊集合为nb nm ns no po ps pm pb;误差变化量ec、参数kp、ki、kd的模糊集合为nb nm ns zo ps pm pb。他们表示的意义为：nb=负大、nm=负中、ns=负小、no=负零、zo=零、po=正零、ps=正小、pm=正中、

5、pb=正大。得到模糊变量e、ec、kp、ki、kd的隶属度函数曲线如图3至图7所示：图3 kp隶属函数响应曲线图4 ki隶属函数响应曲线图5 kd隶属函数响应曲线图6 e隶属函数响应曲线图7 ec隶属函数响应曲线在模糊化完成后需要建立规则表，根据规则表的描述，可以总结出56个模糊条件语句，形式例如：如果(e 是 pb) 并且 (ec 是 pb)那么(kp 是 pb) (ki 是 zo) (kd是 pb)。详见表1表3。最后一个步骤是去模糊化和建立查询表。在模糊控制中查询表应该嵌入到程序中。假设输入的值是固定的那么可以在表中查出相应的输出值。实际上，这可以节省许多计算时间并使控制简化。表1 kp

6、规则表表2 ki规则表表3 kd规则表5实验结果分析图8 pid控制响应曲线图9 模糊pid控制响应曲线实验利用了文献7中的转向机构模型，它的仿真回路已经由图2给出。我们已经用matlab仿真出了一般pid控制算法和模糊pid控制算法，获得的响应曲线如图8、图9所示。实验结果表明，同一般得pid控制相比模糊控制的响应时间要短且没有超调的。系统的动态性能有了重大的提高。6总结和展望这篇文章给出了一个控制智能小车的设计方案，并且通过实验从实际上很好的验证了这个方案。无人驾驶智能小车是以计算机技术、模式识别以及智能控制技术的发展为基础的。许多国家和机构都在做这一方面的研究，但它是一个复杂的系统，它包

7、含了许多方面的技术，所以任何一个技术的发展都是重要的，这可能成为智能车发展的瓶颈。7s12xs系列装置概况71介绍新的s12xs系列16位微控制器是一个具兼容性的s12xe系列的简化版本。这些系列成员提供了一个简便的途径来开发通用平台的低端到高端化应用。将软件和硬件的重新设计降到最少。以通用汽车应用和can节点应用为目的，一些典型的应用如： 车身控制器，乘员检测，车门模块，rke接收器，智能制动器，照明模块和只能接线箱。s12xs系列保持了s12xe系列的一些特征包括闪存器纠错代码（eec），一个独立的用来存储代码和数据的数据闪存模块，提高电磁兼容性能的调频锁定环和一个快速atd转换器。s12

8、xs系列在保持了16位微处理器的所有优点和效率的同时保持了低成本低能耗、电磁兼容性和代码长度优势被目前飞思卡尔16位s12和s12x微处理器系列的使用者所喜爱。同s12x的成员一样s12xs系列运行16为存取，外设和记忆元件无需等待状态。s12xs可以选择112引脚薄型四侧封装，80引脚四列封装，64引脚薄型四侧封装进行封装并保持和s12xs系列一样的高引脚兼容性。除了每个模块可用的i/0端口，多达18个i/o端口具有中断能力允许从停止或等待状态被唤醒。外部设备包括：mscan（可扩展控制器区域网络），spi（串行外设接口），2个sci，8通道24位周期中断时钟，8通道16位定时器，8通道pw

9、m和12通道16位atd转换器。软件控制的外设-端口路由选择使得以更少的引脚线数封装来灵活混杂的使用外设模块成为可能。711特性s12xs系列的特征都在这里列出，表一列出了内存选项的特征，表二列出了外设特征，这个外设特征在其他系列中也是适用的。16位cpu12x向上兼容s12指令系统，但是除了已经被移除的五个模糊指令(mem, wav, wavr, rev, revw）加强了变址寻址获得大量的数据段而不依赖ppage中断模块七个层次嵌套的中断灵活的分配中断源到每一个中断水平外部非可屏蔽高优先级中断下一个输入可以做为唤醒中断中断请求和非可屏蔽中断请求总线接收引脚sci接受引脚模块映射控制（mmp

10、）调试模块（dbg）6464位圆形缓冲区采集流量变化信息或内存访问信息后台调试模块（bdm）osc_lcp (oscillator)振荡器低功率回路控制皮尔斯振荡器利用4mhzd到16mhz晶振良好的抗干扰度crg 时钟及复位发生器cop看门狗实施中断在自同步模式下快速从停止装态被唤醒内存选项64k, 128k 和 256k 字节闪存闪存的一般特点64个数据位和8个校验位允许一个校正位和两个检错位擦除扇形区1024位自动化程序和消除算法保护体制防止意外的擦除和程序保护选项防止越权存取4k和8k字节数据存储空间16通道12位模数转换器8 / 10 / 12 位分辨率数据结果向左或向右对齐为在停止

11、模式下转换的内部振荡器连续转换模式16位模拟输入通道多路转换器多通道scancs引脚可以用来做数字量输入或输出mscan(可扩展控制器区域网络)1mb每秒，can2.0a、b软件兼容模块标准和扩充的数据帧0-8字节数据长度可编程使位速率至1mbps5个先入先出存储接收缓冲区3个带有内部优先权的传输缓冲区单纯接听模式来监测can总线通过软件或自动恢复总线关闭传输或发送信息16位时间标示tim（标准时钟模块）输入捕捉或输出比较816位通道具有8位精度预分频器的16位自振荡计数器116位脉冲存储器pit（周期性中断定时器）升级至4个有超时期的定时器超时期在1224个总线时钟周期中选择升级至8通道*8

12、位或4通道*16位脉宽调制器中间对齐或左对齐的输出大范围频率的可编程时钟选择逻辑串行外围接口模块（spi）可配置8位或16位字长传输和接收双重缓冲主导或从属模式最高位有效或最低位有效移动串行时钟相位和极性的选择2个串行通信接口全双工或单线运行13位波特率选择可编程的字符长度可编程的传输和接收极性中断检测和传输碰撞检测片上稳压器2个带基准源的并行线性稳压器带低压中断的低压检测通电复位（por）电路低压重置（lvr）输入/输出多达91个一般用途的输入输出引脚所有输出引脚驱动强调可配置封装方式的选择112引脚薄型四侧扁平封装80引脚四列扁平封装64引脚薄型四侧扁平封装操作条件大范围单电源供电电压，从

13、3.135v至5.5v最大40mhz cpu总线频率环境温度从-40至125温度选择：-40至 85-40至 105-40 至 1258hcs12特点与mc68hc12是一样的并且以mc68hc11 cpu 为基础提供高效的内存访问提供满足程序需求的内存扩展了hc11指令系统增加了一些新的寻址方式允许外部辅助存储器下面是hcs12 cpu体系结构的概述，hcs12 cpu与mc68hc12相似并且在许多文献中被称为cpu12，另一方面cpu12 向上与mc68hc11 cpu兼容。mc68hc11 和mc68hc12分别被称为hc11和hc12。同hc12一样hcs12 cpu将所有暂存器和外

14、设编址到一个独立的线性地址空间，提供高效的存储访问。由于hcs12系列可寻址1mb地址空间，分页表被用来访问64-16k地址。这就为系统设计者提供了满足许多应用程序需要的内存空间。hcs12 cpu指令系统扩充了hc11的数据传送，数据操作指令，增强了算数运算，增加了分支和控制逻辑。此外，hcs12模块还增加了寻址方式，成为了17种寻址方式。尽管许多hcs12系列成员含有对于采用单一整合式驱动电路的程序来说是理想的片上闪存和随机存取存储器，用户还是可以安装装置访问外部存储器。还有更多特点：hcs12具有和m68hc11/m68hc12相同的程序模型没有新的寄存器没有改变中断保存顺序多路复用和非

15、多路复用的外部中断hcs12可以重新使用已存在的软件代码资源注意：定时回路的改变时因为有了新的时钟频率、字节计数和指令周期时间hcs12在用新的指令时体现更好的性能hcs12减少了中断等待时间hcs12提高了运算速度hcs12提高了性能指令队列数据提高了性能在保证准确性的前提下指令执行速度变快了参考文献1魏玉虎、石陈钰,姜健照张华。基于视觉的智能小车转向控制研究j.应用电子技术,2001(1)。2 李正建,黄丽佳、葛鹏飞,刘翔飞。基于ccd的智能小车自动跟踪系统j. 东华大学学报(自然科学).2008(6)。3,张云周，吴成东，施恩一，秦照冰 基于ccd的智能小车导航系统j.东北大学学报(自然

16、科学).2009(2)。4李旭章。 基于视觉研究的智能小车横向偏差测量方法j. 东南大学杂志(自然科学版),2007年(1)。5王朋。钢筋混凝土机器人的有趣的控制及应用j. 山东大学.2007。6王磊,王为民。模糊控制理论和应用。国防工业出版社。1997:197 魏新。机电驱动控制系统的设计和分析 南京理工大学2007附英文原文journal of measurement science and instrumentation supplement 2010implementation of fuzzy-pid in smart car controlabstractan unmanued s

17、mart car control system and the fuzzy-pid control algorithm are produced . a design scheme of fuzzy-pid controller is put forward. the simulation analysis from matlab indicated that the dynamic performance of fuzzy-pid control algorithm is better than that of usual pid. experimental result of smart

18、car show that it can follow the black guide line well and fast-stable complete running the whole trip.keywords fuzzy-pid; smart car; fuzzy controller; fuzzy control1 introductionin recent years, many countries are developing unmanned vehicle technology. this gives birth to many new theories and appl

19、ied technology. reference1 presents the theory of turn ahead which uses real-time monitoring speed to change the turn-in point dynamically, then it implements the control strategy to achieve a perfect characteristics of steering. reference2 uses edge detection algorithm to extract track information

20、and adopt p control. reference3 proposes a efficient, good anti-jamming and adaptive image processing dynamic algorithm which effectively solves the out of track caused by the changes of ambient light and track. reference4 reconstructs spatial relationships of track and calibrates camera using nonli

21、near optimization, then it can measure lateral deviation accurately. the above improve vehicle performance in one way but they are all lack of characteristics of car movement and based on lots of experiments. a fuzzy-pid control algorithm and a design scheme of fuzzy-pid controller are put forward i

22、n this paper. at last, the experimental result is given out to prove the validity of fuzzy-pid.2 hardware system designto implement the design of fuzzy-pid algorithm, its necessary to design a hardware system of smart car. smart car would have a smart control unite which contain detection of guide l

23、ine, steering angle value, speed value and so on. see details in fig.1.fig.1 the functional block diagram of smart car3 basic principle of fuzzy-pidits difficult for usual pid control algorithm to achieve the best effect. because, the parameters kp, ki, kd cant adjust to different object or differen

24、t state of the same object. fuzzy control is based on fuzzy set and fuzzy logic. without precise mathematical model it can determine the size of controlled variable according the rule table organized by experience. in general, fuzzy control input variables are based on system error e and error chang

25、e ec, which is similar to pd control. such control might have a good dynamic characteristic, but the static performance is not satisfactory.combining fuzzy control and pid control, this would make a system have both flexibility-adaptablity of fuzzy control and high accuracy of pid control.fig.2 show

26、s the structure diagram of fuzzy-pid control system, in which fuzzy controller is responsible for selecting a different pid parameter to improve the local performance thus increasing over all performance.4 design of fuzzy-pid controllerspeed drive motor controller design is similar to the following

27、example for steering gear controller design. fuzzy controller consists of fuzzification, fuzzy-inference and defuzzification, which are based on the knowledge base.6 controller input error and error change, output the parameters kp,ki,kd.suppose the fuzzy set for e isnb,nm,ns,no,po,ps，pm,pb; the fuz

28、zy set for ec、 kp、ki and kd isnb,nm,ns,zo,ps,pm,pb. the linguistic meanings are: nb = negative big, nm = negative middle, ns = negative small, no = negative zero, zo = zero, po = positive zero, ps = positive small, pm = positive middle, pb = positive big. so the membership function curves of fuzzy v

29、ariables e、ec、kp、ki and kd are shown in the fig.3-fig.7:its necessary to establish rule table after finishing fuzzification. according the description of rule table, 56 fuzzy conditional statements can be summed, which look like if (e is pb) and (ec is pb) then (kp is pb) (ki is zo) (kd is pb). see

30、details in tab.1-tab.3.then, the last step is defuzzification and making a lookup table. during fuzzy control, the lookup table would be embed into the program. suppose input value is fixed, the corresponding output value would be found in the table. actually, this would save much computing time, an

31、d the control would become simply.5 analysis of experimental resultsexperiment used the steering gear model provides by reference7. the simulation circuit were shown in fig.2. the usual pid and fuzzy pid algorithm were all simulinked in the matlab. responding curves obtained were shown in fig.8 and

32、fig.9. the experimental result show that compared with the usual pid, the responding time of fuzzy-pid algorithm is shorter without over swing. the system dynamic performance is improved significantly.6 conclusion and outlookthis paper provided a design scheme for controlling a smart car, which is p

33、roved practically and superlatively though experiments. unmanned smart car is due to the development of computer technology, pattern recognition and intelligent control technique. many countries and research groups are doing research in the area. but its a complicated system, which involves a number

34、 of technologies. so the development of each technology is important, for it would become the bottleneck of the development of smart car.device overview s12xs family1.1 introductionthe new s12xs family of 16-bit micro controllers is a compatible, reduced version of the s12xe family. these families p

35、rovide an easy approach to develop common platforms from low-end to high-end applications, minimizing the redesign of software and hardware. targeted at generic automotive applications and can nodes, some typical examples of these applications are: body controllers, occupant detection, door modules,

36、 rke receivers, smart actuators, lighting modules and smart junction boxes amongst many others.the s12xs family retains many of the features of the s12xe family including error correction code(ecc) on flash memory, a separate data-flash module for code or data storage, a frequency modulated locked l

37、oop (ipll) that improves the emc performance and a fast atd converter.s12xs family delivers 32-bit performance with all the advantages and efficiencies of a 16-bit mcu while retaining the low cost, power consumption, emc and code-size efficiency advantages currently enjoyed by users of freescales ex

38、isting 16-bit s12 and s12x mcu families. like members of other s12xfamilies, the s12xs family runs 16-bit wide accesses without wait states for all peripherals and memories. the s12xs family is available in 112-pin lqfp, 80-pin qfp, 64-pin lqfp package options and maintains a high level of pin compa

39、tibility with the s12xe family. in addition to the i/o ports available in each module, up to 18 further i/o ports are available with interrupt capability allowing wake-up from stop or wait modes.the peripheral set includes mscan, spi, two scis, an 8-channel 24-bit periodic interrupt timer, 8-channel

40、 16-bit timer, 8-channel pwm and up to 16- channel 12-bit atd converter. software controlled peripheral-to-port routing enables access to a flexible mix of the peripheral modules in the lower pin count package options.1.1.1 featuresfeatures of the s12xs family are listed here. please see table d-1 f

41、or memory options and table d-2 for the peripheral features that are available on the different family members. 16-bit cpu12x upward compatible with s12 instruction set with the exception of five fuzzy instructions(mem, wav, wavr, rev, revw) which have been removed enhanced indexed addressing access

42、 to large data segments independent of ppage int (interrupt module) seven levels of nested interrupts flexible assignment of interrupt sources to each interrupt level. external non-maskable high priority interrupt (xirq) the following inputs can act as wake-up interrupts irq and non-maskable xirq ca

43、n receive pins sci receive pins mmc (module mapping control) dbg (debug module) 64 x 64-bit circular trace buffer captures change-of-flow or memory access information bdm (background debug mode) osc_lcp (oscillator) low power loop control pierce oscillator utilizing a 4mhz to 16mhz crystal good nois

44、e immunity crg (clock and reset generation) cop watchdog real time interrupt clock monitor fast wake up from stop in self clock mode memory options 64k, 128k and 256k byte flash flash general features 64 data bits plus 8 syndrome ecc (error correction code) bits allow single bit failurecorrection an

45、d double fault detection erase sector size 1024 bytes automated program and erase algorithm protection scheme to prevent accidental program or erase security option to prevent unauthorized access4k and 8k byte data flash space 16 data bits plus 6 syndrome ecc (error correction code) bits allow singl

46、e bit failurecorrection and double fault detection erase sector size 256 bytes automated program and erase algorithm 4k, 8k and 12k byte ram 16-channel, 12-bit analog-to-digital converter 8/10/12 bit resolution left or right justified result data internal oscillator for conversion in stop modes cont

47、inuous conversion mode multiplexer for 16 analog input channels multiple channel scans pins can also be used as digital i/o mscan (1 m bit per second, can 2.0 a, b software compatible module) 1 m bit per second, can 2.0 a, b software compatible module standard and extended data frames 0 - 8 bytes da

48、ta length programmable bit rate up to 1 mbps five receive buffers with fifo storage scheme three transmit buffers with internal prioritization listen-only mode to monitor can bus bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages tim (standa

49、rd timer module) 8 x 16-bit channels for input capture or output compare 16-bit free-running counter with 8-bit precision prescaler 1 x 16-bit pulse accumulator pit (periodic interrupt timer) up to four timers with independent time-out periods time-out periods selectable between 1 and 224 bus clock

50、cycles up to 8 channel x 8-bit or 4 channel x 16-bit pulse width modulator center- or left-aligned outputs programmable clock select logic with a wide range of frequencies serial peripheral interface module (spi) configurable for 8 or 16-bit data size double-buffered transmit and receive master or s

51、lave mode msb-first or lsb-first shifting serial clock phase and polarity options two serial communication interfaces (sci) full-duplex or single wire operation 13-bit baud rate selection programmable character length programmable polarity for transmitter and receiverbreak detect and transmit collis

52、ion detect on-chip voltage regulator two parallel, linear voltage regulators with bandgap reference low-voltage detect (lvd) with low-voltage interrupt (lvi) power-on reset (por) circuit low-voltage reset (lvr) input/outputup to 91 general-purpose input/output (i/o) pins configurable drive strength

53、on all output pins package options 112-pin low-profile quad flat-pack (lqfp) 80-pin quad flat-pack (qfp) 64-pin low-profile quad flat-pack (lqfp) operating conditions wide single supply voltage range 3.135 v to 5.5 v at full performance 40mhz maximum cpu bus frequency ambient temperature range 40c t

54、o 125c temperature options: 40c to 85c 40c to 105c 40c to 125chcs12 features is identical to the mc68hc12 and based on the mc68hc11 cpu provides efficient memory access provides memory needed to satisfy many applications extends the hc11 instructions has several new addressing modes added accesses a

55、dditional memories externallyhere is an overview of the hcs12 cpu architecture. the hcs12 cpu isidentical to the mc68hc12 and is referred to in most documents as cpu12.another factor to consider is that cpu12 is upward compatible with themc68hc11 cpu. the mc68hc11 and the mc68hc12 will be referred t

56、o asthe hc11 and hc12 respectively in this module.like the hc12, the hcs12 cpu maps all registers and peripherals into asingle linear address space, providing efficient memory access. since thehcs12 family supports up to 1 mega byte of address space, a pagingscheme has been implemented to access as

57、many as 64-16k page windows. this provides system designers with the memory needed to satisfymany applications.the hcs12 cpu instruction set extends the hc11 instructions for data movement, data manipulation, enhanced arithmetical operation, andbranching and control logic. in addition, the hcs12 model adds several n