CD74FCT541中文资料

1、CD74FCT541中文资料Data sheet acquired from Harris Semiconductor SCHS257Features?Buffered Inputs?Typical Propagation Delay: 6.4ns at V CC = 5V ,T A = 25o C, C L = 50pF ?CD74FCT540-Inverting ?CD74FCT541-Noninverting?SCR Latchup Resistant BiCMOS Process and Circuit Design?Speed of Bipolar FAST?/AS/S ?64mA

2、Output Sink Current?Output Voltage Swing Limited to 3.7V at V CC = 5V ?Controlled Output Edge Rates ?Input/Output Isolation to V CC?BiCMOS Technology with Low Quiescent PowerDescriptionThe CD74FCT540and CD74FCT541octal buffers/line drivers use a small geometry BiCMOS technology.The output stage is a

3、 combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below V CC .This resultant lowering of output swing (0V to 3.7V)reduces power bus ringing (a source of EMI)and minimizes V CC bounce and ground bounce and their effects during simultaneous output switch

4、ing.The output configuration also enhances switching speed and is capable of sinking 64 milliamperes.The CD74FCT540is a three-state buffer having two active LOW output enables.The CD74FCT541is a noninverting three state buffer having two active LOW output enables.Ordering InformationPinoutsPART NUMB

5、ER TEMP.RANGE (o C)PACKAGE PKG.NO.CD74FCT540E 0 to 7020 Ld PDIP E20.3CD74FCT541E 0 to 7020 Ld PDIP E20.3CD74FCT540M 0 to 7020 Ld SOIC M20.3CD74FCT541M 0 to 7020 Ld SOIC M20.3CD74FCT541SM0 to 7020 Ld SSOPM20.209NOTE:When ordering the suffix M and SM packages, use the entire part number.Add the suffix

6、 96to obtain the variant in the tape and reel.CD74FCT540(PDIP , SOIC)TOP VIEWCD74FCT541(PDIP , SOIC, SSOP)TOP VIEW1112131415161718202110987654321OE1A0A1A2A3A4A6A5A7GND V CC Y0Y1Y2Y3Y4Y5Y6Y7OE21112131415161718202110987654321OE1A0A1A2A3A4A6A5A7GND V CC Y0Y1Y2Y3Y4Y5Y6Y7OE2January 1997CAUTION: These dev

7、ices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.CD74FCT540,CD74FCT541BiCMOS FCT Interface Logic,Octal Buffers/Line Drivers, Three-StateN O T R E C O M M E N D E D F OR N E W D E S I G N S U s e CM O ST e c h n o l o g y File Number2383.2元器件交易网Function

8、al DiagramIEC Logic SymbolTRUTH TABLE (Note 1)INPUTSOUTPUTSOE1OE2A n CD74FCT540CD74FCT541L L H L H H X X Z Z X H X Z Z LLLHLNOTE:1.H = HIGH Voltage Level L = LOW Voltage Level X = ImmaterialZ = HIGH Impedance2345678918171615141312Y0Y1Y2Y3Y4Y5Y6Y7A0A1A2A3A0A1A2A31GND = PIN 10V CC = PIN 2019OE1OE211Y0

9、Y1Y2Y3Y4Y5Y6Y7541540CD74FCT540CD74FCT54118171615EN123451413121167891918171615EN1234514131211678919Absolute Maximum Ratings Thermal InformationDC Supply Voltage (V CC). . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 6V DC Input Diode Current, I IK (For V I Operating Temperature Range (T A) . .

10、 . . . . . . . . . . . . . .0o C to 70o C Supply Voltage Range, V CC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, V I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V CC DC Output Voltage, V O. . . . . . . . . . . . . . . . . . . . . . . . . . .0 toV CC Inpu

11、t Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . .0 to 10ns/V Thermal Resistance (T ypical, Note 2)JA (o C/W) PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 SSOP Package .

12、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300o C (SOIC and SS

13、OP-Lead Tips Only)CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.N

14、OTE:2.JA is measured with the component mounted on an evaluation PC board in free air.Electrical Speci?cations Commercial Temperature Range 0o C to 70o C, V CC Max = 5.25V, V CC Min = 4.75V (Note 5)PARAMETER SYMBOL TEST CONDITIONSV CC (V)AMBIENT TEMPERATURE (T A)UNITS25o C0o C TO 70o CV I (V)I O (mA

15、)MIN MAX MIN MAXHigh Level Input Voltage V IH 4.75 to 5.252-2-V Low Level Input Voltage V IL 4.75 to 5.25-0.8-0.8V High Level Output Voltage V OH V IH or V IL-15Min 2.4- 2.4-V Low Level Output Voltage V OL V IH or V IL64Min-0.55-0.55V High Level Input Current I IH V CC Max-0.1-1A Low Level Input Cur

16、rent I IL GND Max-0.1-1A Three State Leakage Current I OZH V CC Max-0.5-10AI OZL GND Max-0.5-10A Input Clamp Voltage V IK V CC orGND-18Min-1.2-1.2VShort Circuit Output Current (Note 3)I OS V O = 0V CC orGNDMax-60-60-mAQuiescent Supply Current, MSI I CC V CC orGND0Max-8-80AAdditional Quiescent Supply

17、 Current per Input PinTTL Inputs High, 1 Unit Load ?I CC 3.4V(Note 4)Max- 1.6- 1.6mANOTES:3.Not more than one output should be shorted at one time. Test duration should not exceed 100ms.4.Inputs that are not measured are at V CC or GND.5.FCT Input Loading: All inputs are 1 unit load. Unit load is?I

18、CC limit specified in Static Characteristics Chart, e.g., 1.6mA Max. 70o C.Switching Speci?cations Over Operating Range FCT Series t r, t f = 2.5ns, C L = 50pF, R L (Figure 3) (Note 6)PARAMETER SYMBOL V CC (V)25o C0o C TO 70o CUNITS TYP MIN MAXPropagation Delays(Note 6)Data to OutputsCD74FCT540t PLH

19、, t PHL5 6.428.5ns CD74FCT541t PLH, t PHL5628ns Output Disable to Output t PLZ, t PHZ57.129.5ns Output Enable to Output t PZL, t PZH57.5210ns Power Dissipation Capacitance C PD(Note 7)CD74FCT540-37-pF CD74FCT541-40-pF Minimum (Valley) V OHV During Switching ofOther Outputs (Output Under Test Not Swi

20、tching)V OHV50.5-VMaximum (Peak) V OLP During Switching ofOther Outputs (Output Under Test Not Switching)V OLP51-V Input Capacitance C I-10pF Three-State Output Capacitance C O-15pF NOTES:6.5V: Min is at 5.25V for 0o C to 70o C, Max is at 4.75V for 0o C to 70o C, Typ is at 5V.7.C PD,measured per fli

21、p-flop,is used to determine the dynamic power consumption.P D (per package) = V CC I CC +(V CC2 f I C PD + V O2 f O C L + V CC?I CC D) where:V CC = supply voltage?I CC = flow through current x unit loadC L = output load capacitanceD = duty cycle of input highf O = output frequencyf I = input frequen

22、cyTest Circuits and WaveformsNOTE:8.Pulse Generator for All Pulses:Rate 1.0MHz;Z OUT 50?;t f , t r 2.5ns.FIGURE 1.TEST CIRCUITFIGURE 2.ENABLE AND DISABLE TIMING FIGURE 3.PROPAGATION DELAYNOTES:9.V OLP is measured with respect to a ground reference near the output under test. V OHV is measured with r

23、espect to V OH .10.Input pulses have the following characteristics:P RR 1MHz, t r = 2.5ns, t f = 2.5ns, skew 1ns.11.R.F.fixture with 700MHz design rules required.IC should be soldered into test board and bypassed with 0.1F capacitor.Scope andprobes require 700MHz bandwidth.FIGURE 4.SIMULTANEOUS SWIT

24、CHING TRANSIENT WAVEFORMS3V 0DUTPULSE Z O GEN 7V500?50pF500?V CCR TR T = Z OV 0C L R L R LV It r , t f = 2.5ns(NOTE 8)SWITCH POSITIONTESTSWITCH t PLZ , t PZL , Open Drain Closed t PHZ , t PZH , t PLH , t PHLOpenDEFINITIONS:C L = Load capacitance, includes jig and probecapacitance.R T =Termination re

25、sistance,should be equal to Z OUT ofthe Pulse Generator.V IN = 0V to 3V .Input:t r =t f =2.5ns (10%to 90%),unless otherwise specified3V 1.5V 0V CONTROL INPUTOUTPUTNORMALL Y LOWOUTPUTNORMALLY HIGHSWITCH OPENt PZL3.5V 1.5V1.5V 0Vt PLZt PHZt PZH0V3.5V 0.3V0.3VV OL V OH SWITCH CLOSED ENABLEDISABLE1.5V 3

26、V0V 1.5V 3V 0Vt PLHSAME PHASE INPUT TRANSITIONt PHLt PLHt PHLOPPOSITE PHASE INPUT TRANSITIONOUTPUT1.5V V OH V OLOTHER OUTPUTSOUTPUT UNDER TESTV OHV OLV OH V OHV V OLP V OLIMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

27、 any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of orde

28、r acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control technique

29、s are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHOR