Wm8731 音量调节程序

1、wm8731 i2c控制模块module x(clock_50m, i2c_sclk, i2c_sdat, reset_n, ack,tr_end,start,config_step,reg_index,key1,i2c_data,reg2_data,clock_20k,hex1,hex2,xs1,xs2); input clock_50m; input reset_n,key1; output i2c_sclk,ack,tr_end,start,clock_20k; output1:0 config_step; output3:0 reg_index; output23:0i2c_data;

2、 output15:0 reg2_data; /输出声道 output6:0 hex1,hex2; /七段码显示 output2:0 xs1; /led显示 output3:0 xs2; reg6:0 hex1,hex2; inout i2c_sdat; reg clock_20k; reg 15:0clock_20k_cnt; reg 1:0config_step; reg 3:0reg_index; reg 23:0i2c_data; reg 15:0reg_data; reg start,bz,bx; reg15:0 reg2_data; wire ack; wire tr_end; w

3、ire2:0 xs1; wire3:0 xs2; i2c u1(.clock_i2c(clock_20k), .reset_n(reset_n), .ack(ack), .i2c_data(i2c_data), .start(start), .tr_end(tr_end), .i2c_sclk(i2c_sclk), .i2c_sdat(i2c_sdat); assign xs1,xs2=reg2_data6:0; always(posedge clock_50m or negedge reset_n) /产生i2c控制时钟-20khz begin if(!reset_n) begin cloc

4、k_20k=0; clock_20k_cnt=0; end else if(clock_20k_cnt2499) clock_20k_cnt=clock_20k_cnt+1; else begin clock_20k=!clock_20k; clock_20k_cnt=0; end end always(posedge clock_20k or negedge reset_n) /配置过程控制 if(!reset_n) begin config_step=0; start=0; reg_index=0; reg2_data=16h054d; bz=1b0; bx=1b1; end else i

5、f(!key1) begin if(bx=1) begin bx=0; config_step=0; start=0; reg_index=0; begin if(bz=0) begin if(reg2_data6:0=7b1111111) bz=1b1; else reg2_data6:0=reg2_data6:0+5; end else if(bz=1) begin if(reg2_data6:0=7b0101111) bz=1b0; else reg2_data6:0=reg2_data6:0-5; end end end end else if(clock_20k) begin if(

6、key1=1) bx=1b1; if(reg_index10) begin case(config_step) 0:begin i2c_data=8h34,reg_data; start=1; config_step=1; end 1: if(tr_end) begin if(!ack) begin config_step=2; start=0; end else begin config_step=0; start=0; end end 2:begin reg_index=reg_index+1; config_step=0; end endcase end end always(reg_i

7、ndex) begin case(reg_index) 0:reg_data=16h001f; 1:reg_data=16h021f; 2:reg_data=16h067f; 3:reg_data=reg2_data; 4:reg_data=16h08c8; 5:reg_data=16h0a06; 6:reg_data=16h0c00; 7:reg_data=16h0e01; 8:reg_data=16h1002; 9:reg_data=16h1201; default:reg_data=4)&(cyc_count=30)?clock_i2c:0); assign i2c_sdat=reg_s

8、dat?1bz:0; always(posedge clock_i2c or negedge reset_n) begin if(!reset_n) cyc_count=6b111111; else begin if(start=0) cyc_count=0; else if(cyc_count6b111111) cyc_count=cyc_count+1; end end always(posedge clock_i2c or negedge reset_n) begin if(!reset_n) begin tr_end=0; ack1=1; ack2=1; ack3=1; sclk=1;

9、 reg_sdat=1; end else case(cyc_count) 0:begin ack1=1;ack2=1;ack3=1;tr_end=0;sclk=1;reg_sdat=1;end 1:reg_sdat=0; /开始传输 2:sclk=0; 3:reg_sdat=i2c_data23; 4:reg_sdat=i2c_data22; 5:reg_sdat=i2c_data21; 6:reg_sdat=i2c_data20; 7:reg_sdat=i2c_data19; 8:reg_sdat=i2c_data18; 9:reg_sdat=i2c_data17; 10:reg_sdat

10、=i2c_data16; 11:reg_sdat=1; /应答信号 12:begin reg_sdat=i2c_data15;ack1=0;end 13:reg_sdat=i2c_data14; 14:reg_sdat=i2c_data13; 15:reg_sdat=i2c_data12; 16:reg_sdat=i2c_data11; 17:reg_sdat=i2c_data10; 18:reg_sdat=i2c_data9; 19:reg_sdat=i2c_data8; 20:reg_sdat=1; /应答信号 21:begin reg_sdat=i2c_data7;ack2=0;end 22:reg_sdat=i2c_data6; 23:reg_sdat=i2c_data5; 24:reg_sdat=i2c_data4; 25:reg_sdat=i2c_data3; 26:reg_sdat=i2c_data2; 27:re