北邮数电实验VHDL源代码完整2013年汇总

1、北邮数电实验VHDL源代码完整版注：北邮信通院数电实验，大二下共四次实验，以下为四次实验的完整代码，仅供参考，希望学弟学妹在抄代码的时候了解每一行代码的含义。知识是自己的。别忘了，北邮的未来靠你们。注意事项：1学校部分电脑打不开07版word文件（后缀docx），建议大家准备一份TXT以防万一2运行出错时可能是你输入有误，比如中文和英文符号弄错了3数电实验很简单，但要心细，一定要按老师说的做4数电实验报告千万不要抄袭，老师判断力很强实验一：半加器老师会给出，全加器是画图，怎么画书上有，不用源代码。实验二：（1）3位二进制数比较器LIBRARY IEEE;USE IEEE.STD_LOGIC_1

2、164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY comp3 IS PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC);END comp3;ARCHITECTURE behave OF comp3 ISBEGIN PROCESS(A,B) BEGIN IF(AB)THEN YA=1;YB=0;YC=0; ELSIF(AB)THEN YA=0;YB=1;YC=0; ELSE YA=0;YB=0;YC Y=D0

3、;YB Y=D1;YB Y=D2;YB Y=D3;YB Y=Z;YB=Z; END CASE; END PROCESS;END behave;（3）8421码转换为格雷码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY trans1 ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END trans1;ARCHITECTURE trans_gray OF trans1 ISBEGI

4、NB(0)=A(0)XOR A(1);B(1)=A(1)XOR A(2); B(2)=A(2)XOR A(3);B(3) B B B B B B B B B B B=ZZZZ;END CASE;END PROCESS;END trans_ex3;（5）数码管译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sunyu_encoder ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(6 DOWNTO

5、0); C:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END sunyu_encoder;ARCHITECTURE encoder_arch OF sunyu_encoder ISBEGINPROCESS(A)BEGINC B B B B B B B B B B B=ZZZZZZZ;END CASE;END PROCESS;END encoder_arch;实验三：注：以下的AAA（1）（2）（3）（4）为课前做好的，但课上老师要求有了些变化，实际上机的代码在下面BBB中AAA（1）带异步复位的四位二进制减计数器LIBRARY IEEE;USE IEEE.STD_LOG

6、IC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_1 ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_1;ARCHITECTURE a OF count_1 ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset=0 THENq_temp =1111;ELSIF clkEVENT AND clk=1 THENq_temp =

7、q_temp-1;END IF;END PROCESS;q= q_temp;END a;（2）带异步复位的8421码十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,reset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWN

8、TO 0);BEGINPROCESS(clk,reset)BEGINIF reset=0 THENq_temp =0000;ELSIF clkEVENT AND clk=1 THENIF q_temp=1001 THENq_temp =0000;ELSE q_temp =q_temp+1;END IF;END IF;END PROCESS;q= q_temp;END a;（3）分频器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div_12 ISPORT(clk:IN STD_LO

9、GIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12;ARCHITECTURE a OF div_12 ISSIGNAL temp:INTEGER RANGE 0 TO 11;BEGINp1:PROCESS(clear,clk)BEGINIF clear=0THENtemp=0;ELSIF clkEVENT AND clk=1 THENIF temp=11 THENtemp=0;ELSE temp=temp+1;END IF;END IF;END PROCESS p1;p2:PROCESS(temp)BEGINIF temp6 THE

10、Nclk_out=0;ELSE clk_out=1;END IF;END PROCESS p2;END a;（4）带异步复位的四位环形计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(

11、3 DOWNTO 0);BEGINPROCESS(clk,reset) -0001-0010-0100-1000-0001BEGINIF reset=0 THEN nextcount nextcount nextcount nextcount nextcount=0001;END CASE;END IF;END PROCESS;countout=nextcount;END behave;BBBLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count_BCD ISPORT(clk,r

12、eset:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END count_BCD;ARCHITECTURE a OF count_BCD ISSIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk,reset)BEGINIF reset=1 THENq_temp =0000;ELSIF clkEVENT AND clk=1 THENIF q_temp=1001 THENq_temp =0000;ELSE q_temp =q_temp+1;END IF;END IF;END PRO

13、CESS;q= q_temp;END a;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ring ISPORT(clk,reset:IN STD_LOGIC;-clk_out:out STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ring;ARCHITECTURE behave OF ring ISSIGNAL nextcount:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL temp:ST

14、D_LOGIC;BEGINp1:PROCESS(clk)VARIABLE count:integer range 0 to ;BEGINIF( clkEVENT AND clk=1 )THENIF (count=) THENcount:=0;temp=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS p1;-clk_out=temp;p2:PROCESS(temp,reset) -0001-0010-0100-1000-0001BEGINIF reset=1 THEN nextcount nextcount nextcount nex

15、tcount nextcount=0001;END CASE;END IF;END PROCESS p2;countout=nextcount;END behave;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div_12new ISPORT(clk:IN STD_LOGIC;clear:IN STD_LOGIC;clk_out:OUT STD_LOGIC);END div_12new;ARCHITECTURE a OF div_12new ISSIGNAL temp:STD_L

16、OGIC;BEGINPROCESS(clear,clk)VARIABLE count:integer range 0 to 5;BEGINif (clear=1) thencount:=0;ELSIF( clkEVENT AND clk=1 )THENIF (count=5) THENcount:=0;temp=not temp;ELSE count:=count+1;END IF;END IF;END PROCESS;clk_out=temp;END a;实验四：这个稍有难度，而且书上没有多少参考代码，仔细研究哦（1）数码管显示library ieee;use ieee.std_logic_

17、1164.all;use ieee.std_logic_unsigned.all;entity nixietube1 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end nixietube1;architecture a of nixietube1 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signa

18、l tempclk: std_logic;signal count: integer range 0 to 50000;beginp1:process(clk)beginif(clkevent and clk=1)thenif count=50000 thencount=0;tempclk= not tempclk;elsecount cat=;part cat=;part cat=;part cat=;part cat=;part cat=;part cat=;part=; -0end case;end if;end process p2;catout=cat;partout=part;en

19、d a;（2）数码管滚动显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shiyan12new2 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiyan12new2;architecture a of shiyan12new2 issignal part: std_logic_vector(6 down

20、to 0);signal cat: std_logic_vector(5 downto 0);signal number: std_logic_vector(5 downto 0);signal tempclk: std_logic;-a clk(div 1)signal move: std_logic;-a clk(div 2)beginp1:process(clk)-div 1 (cat 0-5)variable count:integer range 0 to 50000:=0;beginif(clkevent and clk=1)thenif(count=50000)thencount

21、:=0;tempclkcatcatcatcatcatcat=;end case;end if;end process p2;catout=cat;p3:process(clk)-div 2 (one cat and change) about 1Hzvariable count:integer range 0 to :=0;beginif (clkevent and clk=1) thenif (count=) thencount:=0;movenumbernumbernumbernumbernumbernumbernumbernumbernumbernumbernumbernumberpar

22、tpartpartpartpartpartpart=;end case;end process p5;partout=part;end a;（3）数码管滚动显示，且用全灭的数码管填充右边，直至全灭library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shiyan12new3 isport(clk: in std_logic;partout:out std_logic_vector(6 downto 0);catout: out std_logic_vector(5 downto 0);end shiyan12new3;architecture a of shiyan12new3 issignal part: std_logic_vector(6 downto 0);signal cat: std_logic_vector(5 downto 0);signal nu