集成电路实验

电子科技大学微固学院电子科技大学微固学院 标标 准准 实实 验验 报报 告告 实验 课程名称 实验 课程名称 集成电路设计实验集成电路设计实验 电子科技大学教务处制表电子科技大学教务处制表 电电 子子 科科 技技 大大 学学 实实 验验 报报 告告 学生姓名 学生姓名 学学 号 号 指导教师 指导教师 实验地点 实验地点 实验时间 实验时间 一 实验室名称 一 实验室名称 集成电路设计中心集成电路设计中心 二 实验项目名称 工艺仿真二 实验项目名称 工艺仿真 三 实验学时 三 实验学时 4 四 实验目的与意义四 实验目的与意义 随着 IT 产业的迅猛发展 微电子集成电路在通讯 计算机及其他消费类电 子产品中的重要地位日益突出 而 IC 的生产和设计技术水平是决定 IC 芯片性 能的两大要素 目前 IC 设计主要沿正向和逆向设计两条技术路线继续发展 该实验为正向设计中的必须环节 使能基本掌握 IC 工艺仿真 本实验其目的在于 根据实验任务要求 综合运用课程所学知识自主完成 相应工艺仿真 通过该实验 使掌握工艺仿真流程 加深对课程知识的感性认识 增强的 设计与综合分析能力 进而为今后从事科研 开发工作打下良好基础 五 五 实验内容及步骤 第一步 生长常氧和栅氧 1 如图所示 TMA TSUPREM4 NMOS transistor simulation Part a Through field oxidation Define the grid MESH GRID FAC 1 5 METHOD ERR FAC 2 0 Read the mask definition file MASK IN FILE s4ex4m tl1 PRINT GRID Field Poly Initialize the structure INITIALIZEBORON 5E15 Initial oxidation DIFFUSION TIME 30 TEMP 1000 DRY HCL 5 Nitride deposition and field region mask DEPOSIT NITRIDE THICKNESS 0 07 SPACES 4 DEPOSIT PHOTORESIST POSITIVE THICKNESS 1 EXPOSE MASK Field DEVELOP ETCH NITRIDE TRAP ETCH OXIDE TRAP UNDERCUT 0 1 ETCH SILICON TRAP THICKNES 0 25 UNDERCUT 0 1 Boron field implant IMPLANT BORON DOSE 5E12 ENERGY 50 TILT 7 ROTATION 30 ETCH PHOTORESIST ALL Field oxidation METHOD PD TRANS COMPRESS DIFFUSION TIME 20 TEMP 800 T FINAL 1000 DIFFUSION TIME 180 TEMP 1000 WETO2 DIFFUSION TIME 20 TEMP 1000 T FINAL 800 ETCH NITRIDE ALL Unmasked enhancement implant IMPLANT BORON DOSE 1E12 ENERGY 40 TILT 7 ROTATION 30 Save structure SAVEFILE OUT FILE S4EX4AS Plot the initial NMOS structure SELECT Z LOG10 BORON TITLE LDD Process NMOS Isolation Region PLOT 2D SCALE GRID C GRID 2 Y MAX 2 0 PLOT 2D SCALE Y MAX 2 0 Color fill the regions COLOR SILICON COLOR 7 COLOR OXIDE COLOR 5 Plot contours of boron FOREACH X 15 TO 20 STEP 0 5 CONTOUR VALUE X LINE 5 COLOR 2 END Replot boundaries PLOT 2D AX CL Print doping information under field oxide SELECT Z DOPING PRINT 1D X VALUE 4 5 X MAX 3 第二步 局部氧化注入和生长栅极 2 程序如下 TMA TSUPREM4 NMOS transistor simulation Part b Through source drain metallization Set grid spacing and accuracy parameters MESH GRID FAC 1 5 METHOD ERR FAC 2 0 Read structure from initial simulation INITIAL IN FILE S4EX4AS Read the mask definition file MASK IN FILE s4ex4m tl1 Define polysilicon gate MATERIAL MAT POLY POLYCRYS DEPOSIT POLYSILICON THICK 0 4 SPACES 2 DEPOSIT PHOTORESIST THICK 1 0 EXPOSE MASK Poly DEVELOPETCH POLYSILICON TRAP THICK 0 7 ANGLE 79 ETCH PHOTORESIST ALL Oxidize the polysilicon gate DIFFUSION TIME 30 TEMP 1000 DRYO2 LDD implant at a 7 degree tilt IMPLANT ARSENIC DOSE 5E13 ENERGY 50 TILT 7 0 ROTATION 30 IMPL TAB ARSENIC Plot structure SELECT Z LOG10 BORON TITLE LDD Process After LDD Implant PLOT 2D SCALE Y MAX 2 0 Add color fill COLOR SILICON COLOR 7 COLOR OXIDE COLOR 5 COLOR POLY COLOR 3 Plot contours FOREACH X 15 TO 18 STEP 0 5 CONTOUR VALUE X LINE 5 COLOR 2 END SELECT Z LOG10 ARSENIC FOREACH X 16 TO 20 CONTOUR VALUE X LINE 2 COLOR 4 END Replot boundaries PLOT 2D AX CL Define the oxide sidewall spacer DEPOSIT OXIDE THICK 0 4 ETCH OXIDE THICK 0 45 TRAP Heavy S D implant at a 7 degree tilt IMPLANT DOSE 1E15 ENERGY 200 ARSENIC TILT 7 0 ROTATION 30 Anneal to activate the arsenic DIFFUSION TIME 15 TEMP 950 Deposit BPSG and cut source drain contact holes DEPOSIT OXIDE THICKNES 0 7 DEPOSIT PHOTORESIST POSITIVE THICKNESS 1 0 EXPOSE MASK Contact DEVELOP ETCH OXIDE THICKNESS 1 0 TRAP ANGLE 75 ETCH PHOTORESIST ALL Define the metallization DEPOSIT ALUMINUM THICKNESS 1 0 DEPOSIT PHOTORESIST POSITIVE THICKNESS 1 0 EXPOSE MASK Metal DEVELOP ETCH ALUMINUM TRAP THICKNESS 1 5 ANGLE 75 ETCH PHOTORESIST ALL Save the final structure SAVEFILE OUT FILE S4EX4BS Plot the half NMOS structure SELECT Z LOG10 BORON TITLE LDD Process Half of NMOS Structure PLOT 2D SCALE Y MAX 2 0 GRID C GRID 2 PLOT 2D SCALE Y MAX 2 0 Color fill COLOR SILICON COLOR 7 COLOR OXIDE COLOR 5 COLOR POLY COLOR 3 COLOR ALUM COLOR 2 Plot contours FOREACH X 15 TO 18 STEP 0 5 CONTOUR VALUE X LINE 5 COLOR 2 END SELECT Z LOG10 ARSENIC FOREACH X 15 TO 20 CONTOUR VALUE X LINE 2 COLOR 4 END Replot boundaries PLOT 2D AX CL Print doping through drain SELECT Z DOPING PRINT 1D LAYERS X VALUE 2 第三步 生长金属布线 3 程序如下 TMA TSUPREM4 NMOS transistor simulation Part c Formation of complete structure Read right half of structure INITIAL IN FILE S4EX4BS Reflect about the left edge to form the complete structure STRUCTURE REFLECT LEFT Plot the complete NMOS structure SELECT Z LOG10 BORON TITLE Example 4 Complete NMOS Structure PLOT 2D SCALE Y MAX 2 0 Y MIN 3 0 Color fill COLOR SILICON COLOR 7 LABEL X 4 1 Y 2 5 LABEL Silicon SIZE 3 C RECT 7 W RECT 4 H R 4 COLOR POLYSILI COLOR 3 LABEL X 1 8 Y 2 5 LABEL Polysilicon SIZE 3 C RECT 3 W RECT 4 H R 4 COLOR OXIDE COLOR 5 LABEL X 1 2 Y 2 5 LABEL Oxide SIZE 3 C RECT 5 W RECT 4 H R 4 COLOR ALUMINUM COLOR 2LABEL X 3 2 Y 2 5 LABEL Aluminum SIZE 3 C RECT 2 W RECT 4 H R 4 Plot contours FOREACH X 15 16 17 18 CONTOUR VAL X LINE 5 COLOR 2 END SELECT Z LOG10 ARSENIC FOREACH X 15 16 17 18 19 20 CONTOUR VAL X LINE 3 COLOR 4 END Replot boundaries PLOT 2D AX CL SAVEFILE OUT FILE S4EX4CS 4 程序如下 TSUPREM 4 Electrical Extraction Read structure from Example 4 INITIAL IN FILE S4EX4CS Part A Threshold voltage Extract the gate bias vs the sheet conductance in channel region VBS 0V ELECTRIC X 0 0 THRESHOLD NMOS V 0 2 0 1 OUT FILE S4EX4DS1 VBS 2 5V ELECTRIC X 0 0 THRESHOLD NMOS V 0 3 0 05 VB 2 5 OUT FILE S4EX4DS2 Plot the Vgs vs Ids Define the scale to convert the sheet conductance to the currentASSIGN NAME Lch N VAL 1 2 ASSIGN NAME Wch N VAL 25 0 ASSIGN NAME Vds N VAL 0 1 ASSIGN NAME Scale N VAL Vds Wch Lch Plot SELECT TITLE Vgs vs Ids VIEWPORT X MAX 0 5 PLOT 1D IN FILE S4EX4DS1 Y SCALE Scale Y LABEL I Drain Amps X LABEL V Gate Volts TOP 1E 4 BOT 0 RIGHT 3 5 COLOR 2 PLOT 1D IN FILE S4EX4DS2 Y SCALE Scale CL AX COLOR 3 LINE 2 LABEL LABEL Vbs 0 X 1 9 Y 8E 5 RIGHT LABEL LABEL Vbs 2 5 X 2 3 Y 0 2E 5 LEFT Part B C V plot for MOS capacitance Extract the capacitance High Frequency ELECTRIC X 0 0 MOSCAP NMOS V 5 5 0 2 OUT F S4EX4DS3 Low Frequency ELECTRIC X 0 0 MOSCAP NMOS V 5 5 0 2 LOW OUT F S4EX4