英文文献-基于FPGA的高速实时数据采集系统的设计与实现

THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONSVolume 13, Issue 4, December 20061WANG Xu-ying, LU Ying-hua, ZHANG Li-kunDesign and implementation of high-speed real-time data acquisition system based on FPGACLC number TP335 Document A Article ID 1005-8885 (2006) 04-0061-06Abstract The electromagnetic radiation will result in information leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect (PCI) bus and field programmable gate array (FPGA) for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.Keywords high-speed data acquisition, FPGA, PCI bus, veryhigh-speed integrated circuit, Hardware description language (VHDL), analog-to-digital converter (ADC)1 lntroductlonElectromagnetic radiation will be generated when an electric device, especially video display unit, works, and can give rise to electromagnetic leakage. When the electromagnetic leakage is recognized, the available information can be recovered. This will cause information leakage. The electromagnetic radiation is received through a broadband antenna first. Then, it is transformed to the digital form through synchrontzation, low-pass filtering, the ADC l. At last, the recovered information from the electromagnetic leakage can be obtained after the digital information is processed by software methods, phase locking, correlated filtering recognition, and reconstruction. In this article, the data acquisition system has to pick up the electromagnetic radiation of video signals and transform them into the digital form.According to the Nyquist theorem, to sample a sine waveReceived date: 2005-12-31WANG Xu-ying Office of Academic Committee, Beijing University of Posts andTelecommunications, Beijing 100876, ChinaE-mail: wangxuying 126.comLU Ying-huaSchool of Telecommunication and Network Technology, Beijing University of Posts and Telecommunications, Beijing 100876, ChinaWANG Li-kunThe Translation Department of the Second Artillery Troops of PLA,Beijing 100820, Chinaproperly through a digitization process, at least two data points per cycle needed. In this article, the video mode is 640480 75 Hz, and the pixel clock frequency is fp = 1.388rmn= 1.38875640480=32 (MHz). So the sampling rate must be 64 MHz. Conventionally, the role of a high speed data acquisition system is to accept data and transfer the input byte stream to the host memory using the direct memory access (DMA) mechanism. In recent years, with the rapid development of the FPGA 2 and PCI 3-4, it is possible to eliminate the need for special purpose hardware by providing a common hardware and host interface with a provision. Variety of application-specific features can be realized by simply reprogramming the FPGA on the data acquisition card 5-8. This article presents a data acquisition system using Altera Cyclone device and Plx PCI9052 The rest of this article is organized as follows: Section 2 gives a brief description of the system design. Section 3 introduces electromagnetic compatibility (EMC) technology being used in the printed circuit board design. Finally, the conclusions are drawn.2 Brief design of data acquisition system2.1 System block diagramThe design is based on an Altera Cyclone FPGA EPlC6, a block diagram of the overall system can be seen in Fig. 1. It operates on a 32 bits, 32 MHz PCI bus, and there are two on-board supports for 32 Mb of synchronous dynamic random access memory (SDRAM), used for storing the intermediate results. The data acquisition operates as follows: firstly, to initialize and configure PCI9052, FPGA, and SDRAM after power-on. Secondly, to start the ADCs, the sampled data from two ADCs are synchronized and stored into the dual-port random access memory (RAM) on the FPGA, so the bandwidth of data converts from 10 bits to 32 bits within the FPGA. Then the sampled data are stored into the SDRAM. Thirdly, the 32 bits data are read from the SDRAM and written in the FPGA, and transferred into the host computer via the PCI local bus. The following section describes the logical design of the system in detail.THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONSVolume 13, Issue 4, December 2006Fig. 1 The block diagram of the data acquisition system2.2 A/D convertThe analog signal is an electrical field of electromagnetic radiation caused by video display units in the system. According to the video mode (640x480 75 Hz) and the Nyquist theorem, the sampling rate must be 64 MHz, and precision in sampling value must be - 30 dB. But the greater the resolution of ADC, the smaller the conversion rate of ADC. To solve the problem, this article presents a time-interleaved ADC using two Maxim MAX1446 in parallelFig. 3 Single-ended to differential and magnifying circuit2.3 Transfer and cache of sampled dataThe sampled data from two ADCs can be transferred to host computer via PCI local bus directly, but the transfer speed of data must be higher than 64 MHzx2 B= 128 m/S according to the video mode. In fact, the transfer speed of PCI bus can seldom be up to the peak value (132 Mbis). Futhemore, to maintain backward compatibility, two Hynix SDRAM HY57V561620B(L)T are used as a buffer to store sampled data to overcome the bottle-neck of(see Fig. 2). Time interleaving more than one ADC is a well-known technique used to increase the maximum sample rate. Unfortunately, the performance of time-interleaved ADCs issensitive to offset and gain mismatches, as well as sample-time errors between the interleaved channels. This article presents a circuit for magnifying and single-ended to differential conversion (see Fig. 3), and uses clock from phase locked loop (PLL) within FPGA to avoid offset, gain, and sample-time errors between channels. Fig. 2 The timing diagram of the time-interleaved ADCstransfer data. The PCI 9052 is compliant with PCI specification v2.1. The PCI 9052 can be programmed to connect directly to multiplexed or non-multiplexed 8-, 16-, or 32-bit local bus. The PCI 9052 contains a read and write FIFO to speed match 32 bit THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONSVolume 13, Issue 4, December 2006wide, 33 MHz PCI bus to a local bus, which may be narrower or slower. Up to five local address spaces and up to four chip selects are supported. In this design the burst length of the local bus is eight. The local bus operates on a 32 bit, 32 MHz, three local address spaces, and two chip selects.2.4 Logic design within FPGAIn this article, the application-dependent controlled functions as well as SDRAM, ADC, and PCI interfacing are all handled by Fig. 4 Logic design within FPGA2.4.1 Clock moduleCyclone FPGA EPlC6 provides a global clock network and two PLLs for a complete clock management solution. Cyclone PLLs provide the general clocking with clock multiplication and division, programmable phase shifting, programmable duty cycle, as well as outputs for differential I/O support. Designers can use the Quartusn software automatically to set the phase shifting and duty cycle as well as to minimize jitter of the external clock outputs. As the performance of time-interleaved ADCs is sensitive to offset and gain mismatches between the interleaved channels, the signal used as a system clock should have the lowest phase jitter and noise. In this article, the clock module utilizes a PLL and drives the global clock networks to improve system performance. Figure 5 shows the block diagram of the clock module using the Quartus II software programmed in VHDL.Fig. 5 The block diagram of the clock moduleWhere inclk0, is input clock, the frequency is 32 MHz,FPGA logic. The overall logic design within FPGA, is shown in Fig. 4. The overall logic design includes clock module, SDRAM read-write module, and SDRAM controller module.which uses as ADC driving clock. co and cI are one multiplied frequencies, their phases are in reverse. eo is three multiplied frequency, which is 96 MHz used as SDRAM driving clock. 2.4.2 SDRAM read-write module The SDRAM read-write module consists of three main modules, the SDRAM write module, the SDRAM read module, and the SDRAM device initialization, and the SDRAM read-write command module. The SDRAM read-write module is the top level module and brings the whole design together. The SDRAM write module accepts sampled data from two ADCs, then converts them to 32 bits, and waits for the write SDRAM command from the SDRAM device initialization and SDRAM read-write command module, to write the SDRAM. The SDRAM read module waits for read SDRAM commands from the SDRAM device initialization and SDRAM read-write command module to read the SDRAM, and transfer the sampled data to host computer via PCI local bus. The SDRAM device initialization and SDRAM read-write command module generates initialization commands and configuration registers commands to the SDRAM controller, enables two ADCs to sample data, generates read SDRAM command to the SDRAM read module, generates write SDRAM command to the SDRAM write module, and provides the SDRAM addresses bus. In FPGA implementation, the overall design occupies logic elements 5%, one PLL and embedded THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONSVolume 13, Issue 4, December 2006memory 80%. A top-level system block diagram of the SDRAM read-write module is obtained in VHDL using the Quartus II software and shown in Fig. 6.Fig. 6 The block diagram of the SDRAM read-write moduleThe SDRAM write module and the SDRAM read module both consist of page address generator and dual-port RAM.Cyclone FPGA EPIC6 offers 20 blocks of M4K embedded RAM. The M4K blocks support the dual-port memory. The Quartus II software automatically implements larger memory by combining multiple M4K memory blocks. The page address generator is obtained in VHDL using the Quartus rI software.The code of the page address generator in VHDL is shown as follows:process(wclk,wen)-RAM written processbeginif (wen = 1) thenif wclkevent and wclk = 1thenif (wtmp=“1111111111”) thenwtmp = “0000000000”;elsewtmp =wtmp + 1; -wtpm is value of writeaddressend if;else null;end if;else null;end if;if( (“0000000000” = wtmp and wtmp = “0111111111”) or(“0000000000” = rtmp and rtmp = “0111111111”) )thenpage = 0;else page = 1;end if;if(wtmp =“0111111111” or wtmp =“1111111111”)thenpage_full = 1;else page_full = 0;end if;end process;process(rclk,en) - RAM read processbeginif (en = 1) then- if(page = 0)then rtmp = 0if ( rclkevent and rclk =1)thenif (rtmp =“1111111111”) then rtmp =“0000000000”elsertmp = rtmp + 1;end if;else null;end if;else null;end if;if(rtmp = “0111111111” or rtmp = “1111111111”)thenpage-empty = 1 ;else page-empty = 0;end if;end process;2.4.3 SDRAM controller moduleSDRAM is high-speed dynamic random access memory (DRAM) with a synchronous interface. The synchronous interface and fully pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently. SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals. SDRAM banks must be opened before a range of addresses can be written to or read from. The primary commands used to access SDRAM are read (RD) and write (WR). When the WR command is issued, the initial column address and data word is registered. When the RD command is issued, the initial address is registered. The initial data appears on the data bus 1-3 clock later. The auto-refresh command is issued periodically to nsure data retention. These functions are performed by the SDRAM controller. The SDRAM controller consists of four main modules, the SDRAM controller, control interface, command, and data path module. The control interface module ccepts commands and related memory addresses from the RAM THE JOURNAL OF CHINA UNIVERSITIES OF POSTS AND TELECOMMUNICATIONSVolume 13, Issue 4, December 2006device initialization and SDRAM read-write ommand module, decodes the commands, and passes the equests to the command module. The command module ccepts commands and addresses from the control interface module, and generates the proper commands to the SDRAM. The data path module handles the data path operations during write and read commands. The block diagram of the SDRAM controller is shown in Fig. 7.Fig. 7 The block diagram of the SDRAM controller moduleThe SDRAM controller module is designed using finite state machine (FSM) .The FSM of the SDRAM controller module is shown in Fig. 8. The SDRAM controller module is obtained in VHDL using the Quartus II software.Fig. 8 The FSM of the SDRAM controller3 EMC In printed crcuit board designThe high-speed real-time data acquisition system circuits consist of analog circuits and digital circuits. Electromagnetic radiation will be generated when the high-speed real-time data acquisition system works, which can give rise to electromagnetic interference (EMI) to degrade the system performance. In this article, the following EMC techniques are used in printed circuit board (PCB) design to reduce the EMI of the system 9.1) Four-layer boards with separated ground and power planes produce the highest level of signal integrity. Signal traces are routed on the top and bottom planes, and they are vertical to avoid EM1 caused by inducting each other.2) Split ground and power planes are arranged to match the physical location of the analog ground and the digital ground as well as the analog power and the digital power. Split the digital power planes are arranged to match the physical location of the 5 V and -5 V (PCI power supply pins), 3.3 V (FPGA, SDRAM, and ADC power supply pins), and 1.5 V (FPGA power supply pins). The two ground planes are joined at a single point, such that the noisy digital ground currents cannot interfere with the analog ground plane. High-speed digital signal traces are routed away from sensitive analog traces such as ADC reference input, inter reference voltage output, etc.3) All bypass capacitors, which, using surface mount devices, are located as close to the device as possible, and preferably on the same side as the ADCs for minimum inductance. Follow the same rules to bypass the digital supply to digital ground.4) Routing all parallel signal traces satisfy the 3W rule, by which the distance between two signal traces is three times the width of signal traces. Clock traces are routed away from sensitive analog traces, and along with protected traces, which shield the electromagnetic interference to sensitive traces.4 ConclusionThis article presents a high-speed real-time data acquisition system based on the PCI bus and FPGA for sampling electromagnetic radiation caused by video signal. For very-high-speed applications, time interleaving increases the overall sampling speed of a system by operating two ADCs in parallel. FPGA in this system plays an important role, the application-dependent controlled functions as well as SDRAM, ADC, and PCI interfacing, are all handled by FPGA logic. The system was tested, the sampling rate can reach 64 Msps and system transfers speed can be up to 128 MB/s. The system can continually work for 20 minutes.Acknowledgments This work is supported by the National Natural Science Foundation of China (6033l010,60271018).References1. Zhang Hong-xin, Lu Ying-hua, Qiu Yu-chun, et al. The study of the recognizability of electro- magnetic leakage information arising from computer. The Journal of China Universities of Posts and