Final Exam, Spring 2006B答案.doc

South China University of TechnologySchool of Electronic and information Engineering Integrated Circuits Design Final Exam, Spring 2006B答案 Please write your Name ,Class and SID in the first sheet. Use the space provided to answer all questions.Name: Class_ SID_ Grades_Problem 1. There are ten statements in this section, For each of the following statements, indicate it is true or false. (15 points)(T / F) (1) The depletion-region width will be increase under the forward-bias , corresponding to the change of space charge.(T / F) (2) Low-swing buses save power and reduce propagation delay at the same time .(T / F) (3) MOSFET is a minority carrier device.(T / F) (4) A fn-block dynamic gate will not have any charge sharing problems if only 01 transitions occur at its inputs during evaluation.(T / F) (5) Check the data of Vt is a type of diagnostic test .(T / F) (6) The main reason for using PMOS transistor in the PUN is that PMOS transistor produce “strong ones” (T / F) (7) The load capacitance of a static CMOS gate has no effect on its VTC.(T / F) (8) Decreasing supply voltage helps to alleviate the velocity-saturation problem. (T / F) (9) A NAND-based ROM structure is typically more compact and slower than a NOR-based one. (T / F) (10) The task of circuit synthesis is to translate a logic description of a circuit into a network of transistors that meets a set of timing constraints.答案：1F2.T3.T4.F5.F6T7.F8.F9.T10.TProblem 2: There are four answers marked a),b),c),d) beneath each question ,Choose the best answer. (15 points).(1). The pinched off condition at drain region is:a. VGS-VDS VTb. VGS-VDS VTc. VDS-VGS VT(2) In order to reduce the propagation delay, we shoulda. Reduce Kp and Knb. Reduce VDDc. Reduce CL d. Reduce W/L (3) The output transition probabilities for the two input static logic AND gate is:a. (1-PA)(1-PB)b. (1-PAPB)PAPBc. 1-PAPBd. (1-PA)(1-PB)1-(1-PA)(1-PB)(4) When generating and optimizing the circuit schematics or layout, we need use the following tools first:a. Implementation and synthesis b. Fault simulation c. Testability techniques d. Analysis and verification (5) What is the logic style of the following figure?a. PLAb. PALc. GALd. PROM答案：1a2.c3.b4.d5.aProblem 3: For each of the following statements, please a fill in the correct answer. (25 points)(1) ParameterFull ScalingGeneral ScalingFix-voltage ScalingW,L1/S1/S1/SVDD1/S1/U1tpPDP1/SU2答案:1/S,U/S2,1/S2,1/S3,1/S (2) SoC have the following Benefits: a._b._ c._ d._ e._答案: 从其中选5项 Functionality, Power Space Code density Liability Speed Time-To-Market Reuse Production (3)答案:NO,Yes,Yes,No,No(4) Please fill in the result of the following pipelining . Clock periodadderAbsolute valuelogarithm1a1+b1-2a2+b2( )-3a3+b3( )( )4a4+b4|a3+b3|( )5a5+b5|a4+b4|( )答案:| a1+b1 |,| a2+b2 |,log| a1+b1|, log| a2+b2|, log| a3+b3| (5) Bill want to make a ROM to store the following information , please design figure of the ROM.1010101101111101答案:Problem 4. The influence of fan-in and fan-out on the propagation delay of the complimentary CMOS gate can be summarized in the following formula: tp = a1FI+a2FI2+a3FOwhile FI and FO are the fan-in and fan-out of the gate, a1,a2 and a3 are weighting factors.Please explain the formula and why fan-in /fan-out have different impact on the propagation delay.(10 points)答案：tpHL: 增加输入同时增加电容CL和放电电阻 ,所以呈二次曲线增长tpLH: 增加输入只增加CL, 所以呈线性增长Problem 5. Please analyses each operation phase of the following dynamic logic circuit . (10 points)答案：Precharge: when f=0, the output node out is precharged to VDD by the PMOS transistor Mp. During that time, the NMOS transistor Me is off, so that no dc current flows regardless of the values of the input signals.Evaluationwhen f = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned on. Depending upon the values of the inputs and the composition of the PDN, a conditional path between out and GND is created.If above path exists, out is discharged, and a low output signal is obtained.If not, the precharged value remains stored on the output capacitance CL. A high output value is obtained.Problem 6. (10oints)a. What is the function of the following circuitb. Why it is insensitive to overlap.答案：C2MOS （register）Latch. (3 points)(1-1)时,只有PDN工作,输入不能传到输出,同样, (0-0)时,只有PUN工作,输入不能传到输出(7 points)Problem 7: What is the Properties of complementary logic circuit, Please design a circuit with the following function by complementary logic stytle.(15 points)答案： High noise margins. VOH and VOL