数字电路英文版第八单元.ppt

CHAPTER 8 FLIP-FLOPS AND RELATED EDVICES,Astable (非稳态的 ) Hold-time ( 保持时间 ) Asynchronous ( 异步 ) Bistable ( 双稳态 ) Clear ( 清零 ) D flip-flop ( D 触发器 ) Edge-triggered flip-flop ( 边沿触发器 ) Feed-back ( 反馈 ) Hysteresis ( 迟滞 ) J-K flip-flop ( JK触发器 ) Latch ( 锁存器 ) Master-slave flip-flop ( 主从触发器 ),Monostable ( 单稳态 ) One-shot ( 单稳 ) Preset ( 预置1 ) RESET ( 置0 ) SET ( 置1 ) Set-up time ( 设置时间 ) S-R flip-flop ( RS触发器 ) Synchronous ( 同步 ) Timer ( 计时器 ) Toggle ( 触发 , 计数 ),KEY TERMS,Astable Having no stable state. An astable multivibrator oscillates between two quasistable states. Asynchronous Having no fixed time relationship. Bistable Having two stable states. Flip-flops and latches are bistable multivibrators.,Clear An asynchronous input used to reset a flip-flop ( make the Q output 0 ). D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.,Edge-triggered flip-flop A type of flip-flop in which the data are entered and appear on the output on the same clock edge. Feedback The output voltage or a portion of it that is connected back to the input of a circuit.,Hold time The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the clock in order to reliably activate the device. Latch A bistable digital circuit used for storing a bit.,Hystersis A characteristic of a threshold-triggered circuit, such as the Schmitt trigger, where the device turns on and off at different input levels. J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.,Master-slave flip-flop A type of flip-flop in which the input data are entered into the device on the leading edges of clock pulses and apper at the output on trailing edges. Master-slave flip-flops have, for the most part, been replaced by edge-triggered types.,Monostable Having only one stable state. A monostable multivibrator, commonly called a one-shot, produces a single pulse in response to a triggering input. One-shot A monostable multivibrator. Preset An asynchronous input used to set a flip-flop ( make the Q output 1 ).,RESET The state of a flip-flop or latch when the output is 0; the action of producing a RESET state. SET The state of a flip-flop or latch when the output is 1; the action of producing a SET state.,Set-up time The time interval required for the control levels to be on the inputs to a digital circuit, such as a flip-flop, prior to the triggering edge of a clock pulse. S-R flip-flop A SET-RESET flip-flop.,Synchronous Having a fixed time relationship. Toggle The action of a flip-flop when it changes state on each clock pulse.,8.1 LATCHES,The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-flop.,2.,Latches are basically similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latches and flip-flop is in the method used for changing their state.,3.,The S-R (SET-RESET) Latch,R,S,Q,Q,Active-HIGH input S-R latch ( NOR S-R Latch ),4.,Q,Q,S,R,5V,R,R,R,R,R,R,5.,S,R,Q,Q,(b) Active-LOW input S-R latch ( NAND S-R Latch ),6.,S,R,Q,Q,When Q is HIGH, Q is LOW, and when Q is LOW, Q is HIGH.,7.,Input Outputs,S R Q Q Comments,1 1 NC NC No change.latch remains in present state.,0 1 1 0 Latch SET .,1 0 0 1 Latch RESET .,0 0 1 1 Invalid condition .,TABLE 8-1 Truth table for an active-LOW input S-R latch.,8.,Input Outputs,S R Q Q Comments,0 0 NC NC No change.latch remains in present state.,0 1 0 1 Latch RESET .,1 0 1 0 Latch SET .,1 1 0 0 Invalid condition .,TABLE 8-1 Truth table for an active-HIGH input S-R latch.,S,R,Q,Q,Active-HIGH input S-R latch,S,R,Q,Q,(b) Active-LOW input S-R latch,S,R,9.,EXAMPLE 8-1,S,R,Q,10.,EXAMPLE 8-1: Related Problem Determine the Q output of an active-HIGH input S-R latch if the waveforms in above are inverted and applied to the input.,S,R,Q,Although S remains LOW for only a very short time before the switch bounce, this is sufficient to set the latch.,The Gated S-R Latch,S,R,Q,Q,EN,S,R,EN,(a) Logic diagram,(b) Logic symbol,12.,The latch will not change until EN is HIGH, but as long as it remains HIGH, the output is controlled by the state of the S and R inputs.,EXAMPLE 8-2 Determine the output waveform if the inputs shown in Fig.8-9 are applied to a gated S-R latch that is initially RESET.,S,R,Q,EN,13.,Fig.8-9,(a),(b),EXAMPLE 8-2: Related Problem Determine the Q output of a gated S-R latch if the S and R inputs in Fig. 8-9 (a) are inverted.,S,R,Q,EN,13.,Fig.8-9,(a),(b),The Gated D Latch,D,Q,Q,EN,D,EN,(a) Logic diagram,(b) Logic symbol,14.,Q,Q,Qn+1 = D,( S ),( R ),EXAMPLE 8-3 Determine the Q output waveform if the inputs shown in Fig.8-11 (a) are applied to a gated D latch, which is initially RESET.,D,Q,EN,15.,Fig.8-11,(a),EXAMPLE 8-3 Related Problem Determine the Q output of the gated D latch, if the D input in Fig.8-11 ( a ) is reverted.,D,Q,EN,(a),Input Outputs,D EN Q Q Comments,0 1 0 1 RESET .,1 1 1 0 SET .,X 0 Q0 Q0 No change,Truth table,16.,Qn+1 = D,8.2 EDGE-TRIGGERED FLIP-FLOPS,Flip-flops are synchronous bistable devices, also known as bistable multivibrators. In this case, the term synchronous means that the output changes state only at a specified point on a triggering input called the clock( CLK ) which is designated as a control input C; that is, changes in the output occur in synchronization with the clock.,17.,Edge-triggered flip-flop:,S,R,Q,Q,C,D,Q,Q,C,J,K,Q,Q,C,S,R,Q,Q,C,D,Q,Q,C,J,K,Q,Q,C,Top: positive edge-triggered; bottom: negative edge-triggered.,18.,The Edge-Triggered S-R Flip-Flop:,S,R,Q,Q,C,Inputs Outputs,0 0 X Q0 Q0 No change,S R CLK Q Q Comments,0 1 0 1 RESET,1 0 1 0 SET,1 1 ? ? Invalid,19.,Qn+1 = S + RQn ( SR = 0 condition ),EXAMPLE 8-4,S,R,Q,Q,C,1,2,3,4,5,6,S,R,Q,CLK,20.,EXAMPLE 8-4 Determine Q for the S and R inputs in Fig. 8-16 ( a) if the flip-flop is a negative edge-triggered device.,1,2,3,4,5,6,S,R,Q,CLK,Pulse,transition,detector,Q,Q,S,R,CLK,0,1,HIGH (1),LOW (0),0,1,0,1,0,1,0,1,This gate is disabled Because R is LOW.,This gate is enabled.,G4,G3,G2,G1,HIGH,Fig. 8-18,21.,Pulse,transition,detector,Q,Q,S,R,CLK,0,1,HIGH (1),LOW (0),0,1,0,1,0,1,0,1,This gate is disabled because S is LOW.,This gate is enabled.,G4,G3,G2,G1,HIGH,Fig. 8-19,22.,The Edge-Triggered D Flip-Flop:,S,Q,Q,C,D,CLK,Inputs Outputs,1 1 0 SET(1),D CLK Q Q Comments,0 0 1 RESET(0),23.,R,EXAMPLE 8-5,D,Q,Q,C,1,2,3,4,Q,D,CLK,24.,1,2,3,4,Q,D,CLK,EXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig. 8-21 ( a ) is reversed.,1,2,3,4,Q,D,CLK,EXAMPLE 8-5 Related Problem Determine the Q output for the D flip-flop if the D input in Fig. 8-21 ( a ) is reversed.,The Edge-Triggered J-K Flip-Flop:,J,K,Q,Q,C,Inputs Outputs,0 0 Q0 Q0 No change,J K CLK Q Q Comments,0 1 0 1 RESET,1 0 1 0 SET,1 1 Q0 Q0 Toggle,25.,Qn+1 = J Qn + KQn,Inputs Output,0 0 0 0,J K Qn Qn+1,0 0 1 1,0 1 0 0,0 1 1 0,1 0 0 1,1 0 1 1,1 1 0 1,1 1 1 0,Qn+1 = J Qn + KQn,1,J,KQn,00,01,11,10,0,1,0,1,2,3,4,5,6,7,1,1,1,1,0,J= X K= 1,J= 1 K= X,J= X K= 0,J= 0 K= X,Inputs Output,0 0 0 0,S R Qn Qn+1,0 0 1 1,0 1 0 0,0 1 1 0,1 0 0 1,1 0 1 1,1 1 0 X,1 1 1 X,S,RQn,00,01,11,10,0,1,0,1,2,3,4,5,6,7,1,1,0,S= 0 R= 1,S= 1 R= 0,S= X R= 0,S= 0 R= X,1,1,X,X,Qn+1 = S + RQn ( SR = 0 condition ),Pulse,transition,detector,Q,Q,J,K,A simplified logic diagram for a positive edge-triggered J-K flip-flop.,G4,G3,G2,G1,CLK,26.,Pulse,transition,detector,Q,Q,J,K,Transitions illustrating the toggle when J=1 and K=1.,G4,G3,G2,G1,CLK,1,2,3,HIGH,HIGH,1,2,3,1,2,3,1,2,3,27.,EXAMPLE 8-6,1,2,3,4,5,CLK,J,K,Q,J,K,Q,Q,C,CLK,Toggle,No,change,Reset,Set,Set,28.,Fig. 8-24,( a ),EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig. 8-24 ( a ) are reversed.,1,2,3,4,5,CLK,J,K,Q,Fig. 8-24,EXAMPLE 8-6 Related Problem Determine the Q output for the J-K flip-flop if the J-K inputs in Fig. 8-24 ( a ) are reversed.,1,2,3,4,5,CLK,J,K,Q,Toggle,No,change,Reset,Set,Reset,Asynchronous Preset and Clear Inputs,J,K,Q,Q,C,PRE,CLR,Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.,29.,Pulse,transition,detector,PRE,CLR,Q,Q,J,K,CLK,Logic diagram for a basic J-K flip-flop with active-LOW preset and clear.,30.,J,K,Q,Q,C,PRE,CLR,EXAMPLE 8-8: For the positive edge-triggered J-K flip-flop, determine Q.,HIGH,31.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,Preset,Toggle,Clear,32.,EXAMPLE 8-8: Related Problem If you interchange the PRE and CLR waveforms in Fig. 8-28 ( a ), what the Q output look like.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,EXAMPLE 8-8: Related Problem If you interchange the PRE and CLR waveforms in Fig. 8-28 ( a ), what the Q output look like.,2,1,3,4,5,6,7,8,9,CLR,PRE,Q,Preset,Toggle,Clear,83 MASTER-SLAVE FLIP-FLOP,Another class of flip-flop is the pulse-triggered master-slave, which has largely been replaced by the edge-triggered devices. Although master-slave flip-flops are essentially becoming obsolete, you may encounter this type of flip-flop in some existing equipment.,33.,Data are entered into the flip-flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge. The pulse-triggered master-slave flip-flop does not allow data to change while the clock pulse is active.,34.,The Pulse-Triggered Master-Slave J-K flip-flop,G1,G2,S,R,Q,Q,G1,G2,S,R,Q,Q,C,J,K,CLK,Master,Slave,35.,Inputs Outputs,0 0 Q0 Q0 No change,J K CLK Q Q Comments,0 1 0 1 RESET,1 0 1 0 SET,1 1 Q0 Q0 Toggle,Truth table for the master-slaver flip-flop,36.,J,K,Q,Q,C,J,K,Q,Q,C,(a) Active-HIGH clock: Data are clocked in on positive-going edge of clock pulse and transferred to output on the following negative- going edge.,(b) Active-LOW clock: Data are clocked in on negative -going edge of clock pulse and transferred to output on the following positive- going edge.,37.,EXAMPLE 8-10: Determine the Q output of the master-slave J-K flip-flop for the input waveforms shown in Fig.,J,K,Q,Q,C,38.,5,6,7,8,9,2,1,3,4,K,J,Q,CLK,Ma S,Sla S,Ma NC,Sla NC,Ma RE,Sla RE,Ma NC,Sla NC,Ma S,Sla S,Ma RE,Ma RE,Sla RE,Sla RE,Ma S,Ma S,Sla S,Sla S,SET,NC,NC,Toggle,Reset,39.,85 FLIP-FLOP APPLICATIONS,Application Example,Parallel Data Storage: A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flop.,40.,D,D,D,D,Q1,Q0,Q2,Q3,D0,D1,D2,D3,CLK,CLR,R,R,R,R,D0,D1,D3,D2,0,0,1,1,CLK,CLR,Q1,Q0,Q2,Q3,0,0,0,0,41.,0,0,1,1,CLR,D stored,0,0,1,1,Frequency Division: Another application of a flip-flop is dividing the frequency of a periodic waveform.,J,K,Q,C,HIGH,CLK,2,1,3,4,5,6,7,8,9,CLK,Q,42.,J,K,QA,C,HIGH,CLK,2,1,3,4,5,6,7,8,9,CLK,QA,J,K,QB,C,HIGH,QB,43.,J,K,QA,C,1,CLK,2,1,3,4,5,6,7,8,CLK,QA,J,K,QB,C,1,QB,Counting,1,1,0,1,1,0,1,0,0,1,0,0,0,0,1,1,0,3,2,0,1,1,2,3,Binary sequence,Binary sequence,EXAMPLE 8-12: Determine the output waveforms in the relation to the clock for QA,QB,QC in the below circuit.,J,K,QA,C,1,J,K,C,CLK,J,K,C,QB,QC,QA,QB,QC,44.,1,CLK,QA,QB,QC,1,1,1,1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,45.,8.6 ONE-SHOTS,The one-shot is a monostable multivibrator, a device with only one stable state. A one-shot is normally in its stable state and will change to its unstable state only when triggered.,46.,Once it is triggered, the one-shot remains in its unstable state for a predetermined length of time and then automatically returns to its stable state. The time that the device stays in its unstable state determines the pulse width of its output.,47.,Trigger,t1,t1,t1,t1,t1,t2,t2,t2,t2,R,G1,G2,Q,+V,Apparent LOW,48.,Q,Q,Trigger,Q,Q,C,REXT,CEXT,Trigger,CX,RX/CX,+V,Basic one-shot logic symbols. CX and RX stand for external components.,49.,Nonretriggerable One-Shots : It will not respond to any additional trigger pulses from the time it is triggered into its unstable state until it returns to its stable state.,Trigger,Q,tw,(a),Trigger,Q,tw,These pulse are ignored by the one-shot.,(b),50.,The output pulse width is set by the values of the resistor (RINT = 2k, and REXT is selected) and the capacitor according to the following formula:,tw = 0.7RCEXT,R is either RINT or REXT,51.,Retriggerable One-Shots : It can be triggered before it times out.,Trigger,Q,tw,(a),Trigger,Q,tw,Retriggers,(b),52.,A general formula for calculating the values of these components for a specified pulse width (tw) is,tw = 0.32CEXT( 1+0.7/R),53.,8.7 THE 555 TIMER,The 555 timer is a versatile and widely used device because it can be configured in two different modes as either a monostable multivibrator (one-shot) or as an astable multivibrator (oscillator). An astable multivibrator has no stable states and therefore changes back and forth (oscillates) between two unstable states without any external triggering.,54.,+,_,+,_,R,S,Q,Q1,Comparator A,Comparator B,Threshold,Control,voltage,Trigger,Discharge,GND,Reset,Vcc,output,Discharge,transistor,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),55.,Monostable (One-Shot) Operation,tw = 1.1R1C1,DISCH,RESET,THRESH,TRIG,OUT,CONT,GND,Vcc,Vcc,(8),(4),(7),(6),(2),(1),(5),(3),R1,C1,C2,56.,+,_,+,_,R,S,Q,Q1,A,B,Vcc,output,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),LOW,LOW,H-T,H,0 V,LOW,(a) Prior to triggering,R1,ON,57.,+,_,+,_,R,S,Q,Q1,A,B,Vcc,R,R,R,(6),(8),(5),(2),(7),(1),(4),(3),LOW,0 V,(b) When triggered,t0,t0,t0,t0,Vc1,0,R1,OFF,58.,Output,+,_,+,_,R,S,Q,Q1,A,B,R,R,R,(6),(5),(2),(7),(1),(4),LOW,0 V,(c) At end of charging interval,t0,t0,t1,t0,VCC,0,R1,ON,t1,t1,t1,HIGH,2,3,59.,Astable Operation,DISCH,RESET,THRESH,TRIG,OUT,CONT,GND,Vcc,Vcc,(8),(4),(7),(6),(2),(1),(5),(3),R1,C1,C2,60.,R2,+,_,+,_,R,S,Q,Q1,A,B,R,R,R,(6),(5),(2),(7),(1),(4),(3),0 V,Operation of the 555 timer in the astable mode,R1,ON,Charging,Discharging,R2,61.,2/3 Vcc,1/3 Vcc,(1),(1), , ,The frequency of oscillation is given by the following formula.,f =,1.44,(R1+ 2R2)C1,(8-4),The time that the output is HIGH (tH) is how long it takes C1 to charge from 1/3Vcc to 2/3Vcc.,tH =0.7(R1+ R2)C1,(8-5),62.,The time that the output is LOW (tL) is how long it takes C1 to discharge from 1/3Vcc to 2/3Vcc.,tL =0.7R2C1,(