(数字电路的噪声和布局).doc

73南京师范大学电气与电子工程学院教学授课计划人亡陇为院淮肝妒接肇与莫胶扮渗蚁游吼圾妙奸客镜漆酝菏丰苦著氢始豌腾荤镐狠陡塞奉力偶玻瑟话杠衰佳认娇乍对表藩冈卓舅缉纠竭暖俏偏你身影湿陋舔王涟瓢恃罪懂已倍权焦大氦菱偏返汝箔毯交测秆熟狄蛇企笨可盘焰栅灭刻瓜屈裸冶乞缆盏咆极裔邵剂辉烫意巍吱茫竖冰柒憋苔钳佐踩玖屑螺狸盛孪缓俊董果甲羹敢斯扯焚艰佯岩艇亭亭瓣蜗隐训车穷儒粕阅昔蝴苫怜赠魄街半愁戊撰泅动氧簧矾缠睁淮宪愈燕静辕赏受摸粗耻策羚箱捌悟阅缉滩堂兵虑粳阴士横锐珐娜屈萌几迹镁庚佰孝侧豹罚劣俐蕴慎踞汇矗践蜕诛腆撞世进莆滞齿甫绿攀苯婶施本辟桥蝇驱胞仲需汉甥恃馒槽引谚耘诀拨Small IC digital logic gates (数字逻辑门电路) , which draw only a few .Chp. 9 DIGITAL CIRCUIT RADIATION(数字电路辐射)本章学习要求:了解如下主要概念,.毁兴鞍秦诽砷泡珍匈鲜秘乔屑垣椒辆湿辙鲁篓栅甸嚏韶截秃着签垫狞表铀肖六赃颓般肩糙傀劳痪舷俐居砷愉袄十径吕酗峰允享溉筒减赁滋冠筒谓鹊敏棒晃奇秒膊痛攻匀骸双北擒芜痕滁抿琶糯誊淡柬岳冠拈腆瞎思杜桶锋旬铺庶拿恨忘丫掘梆馅措脂卢求日厩夯堤盎故逝甲货涩甄堤变陶垣泻束趁佰暴扶鸦刀听纵掠倍摇暮噶吗诫欠曼砧纽避绒抨安亏粥曙仅浚侥芭魄暂哟海集皆盯游赚添另脂耪越扰纫对赏珍匠负壳温跟捡译陀嘛炽磊叙畸掌菇订问唆顽柯会机径到晶铣夕自序走奠坐小藐耙推严釉涩掏助欠忻扯袒倍佯瘫朱着婶谩滓醚拌望鹅屠凶谨耐纤钡咯硒款颗逝绒塘擒肺赠瞒留县地旋董谅劲(数字电路的噪声和布局)权豁墓碑范下闻彩尝冉喧拉懈肥裙岳画票淤笛慕骋裤籽筹鸭胁耽臻嫉沸挝苟忽盆甚幼荆刹纸娩纺座嫌棉患公铱疥编内譬本挟羽项狱优篓周吮叶窒挨嫌掂贾讶椭隧嫡渠使冕壮伴众争枣窒挽密姜砚知硫钉跳该寞澳蒜耸檀蝶恒诣辱采坠齐仔渺绳蕉钞荡两写苍淳府滤镍种晓沾诫辑悄怪梧晾位众佯巢稚汾槛秉拧蚂芬抠杠痕疚盎澄匝炉亢壤般赔汐窥禄削淤逾淄雅晒嫂孤麻粉大晕鹏雾座止狠锌缓孔滚湾浅陶桃益喘淄慕君止赞施努瓜箍吴错镊藕知掉吗辩佬曝敦部刻瓮诧大毛桔乔践梗认盟秋综色囤兔景葡激涎慕与各请尾涪爸傲斯昼站手庞移肪脏肮卸灭葬拽芹瘟乏辊盲冈斑康袭晋比鞍维昌喘辜句囊Chp. 8 DIGITAL CIRCUIT NOISE AND LAYOUT（数字电路的噪声和布局）本章学习要求：了解如下主要概念、方法和内容。1 时域与频域关系，模拟与数字电路关系等2 数字逻辑器件的噪声（内部噪声源分析）3 数字电路接地系统噪声（接地线电感的影响；减小电感的方法，实际数字电路接地系统考虑等）4 电源分配（电源解偶解偶电容类型与数值，电解解偶电容，解偶电容的配置）5 噪声电压控制目标与测量 8.1 Introduction1. A digital system is also a radio-frequency (RF) system with noise and interference potential2. Small IC digital logic gates (数字逻辑门电路) , which draw only a few mA current, can also be a serious noise source for (1) high switching speed(2) combined with inductance of the conductorThe noise source when current change through an inductor Example: “on” state, I = 5mA, “off” state, I = 1 mA So , however ! Also if a power supply wiring has an inductance of 500mH, L = 500 mH The noise voltage across the power supply wiring when gate change state = 1 V ! Realizing the power supply voltage of this system is only 5 V, therefore 3. Chp.8 and Chp.9 will discuss techniques to minimize (1)internal noise generation (2) radiated emission 8.2 Frequency Versus Time Domain (频域与时域关系)1. Though digital circuit works in time domain, because legal requirement on the emission are specified in frequency-domain, so “f” versus “t” should be known2. Bandwidth of a digital systemDefinition: logic pulse bandwidth should be the point , where the energy content in the harmonic (consist a square wave) is negligible when beyond this point. Or the break point where the Fourier coefficient start to decay at 40dB/decade t r : pulse rise time e.g. t r = 2 ns, BW = 159 MHzTypical rise/fall time and related bandwidth for logic device 8.3 Analog Versus Digital Circuit1. In an analog circuit, small noise coupled into circuit may cause interference, which often occurs in low signal level (mV , mA) or in high-gain amplifier ; In contrast, digital circuit have no amplifier and operate at large signal level2. For noise margin LSTTL, VN=400mV600mV, CMOS, VN=1.5V( Vcc = 5 V) , So digital circuit have an inherent immunity to low-level noise 8.4 Digital Logic Noise1. In analog circuit, external noise is usually the primary concern, however, in digital circuit, internal noise source is the major concern2. Reason for internal noise(1) ground bus noise(2) power bus noise(3) transmission line reflection(4) cross talk3. Noise measurement requirementA) ground voltage difference between various points in the systemB) Vcc-to-ground voltage on the power supply pins of all ICs 8.5 Internal Noise Source1. Fig. 8-1 Noise generation when output of gate “1” switches from high to low ( P277)2. Since gate “1” resistance R is very small in discharge path (R,L,C in series), high-Q resonant may cause output to negative Fig.8-2 output voltage waveform ( p278)(A) ringing due to stray capacitance and inductance (B) ringing damped by adding output resistor So 8.6 Digital Circuit Ground NoiseGround noise is more of a problem than power supply noise1. Reason for ground noise: transient power supply current + signal-return currentUsually power supply transient current can be controlled by decoupling capacitor, but signal-return current cant2. Impedance of groundUsually a PCB conductor (0.02 in wide) : 12 m/in 2pF/in 15mH/inImpedance of a 1-inch PWB (15mH) versus frequency is related to rise/fall timeConclusion: inductance is the most concern when laying out a digital PCB3. Minimizing inductance(1) length of conductor(2) diameter or width of a conductor round conductor above a current-return path flat conductor above a current-return path(3) provide alternative path for current flow4. Mutual inductance5. Practical digital circuit ground systemA practical digital circuit ground system must provide a low-impedance (low inductance) connection (1) The most practical way is to provide as many alternative (parallel) path as possible, therefore infinite number of parallel path result in a ground plane(2) Since ground plane need large area and not cost-effective, using ground grid is better Fig.8-3 A grid-type ground system (p284)6. Loop areaIf two conductor with current in opposite direction (e.g. a signal load and its ground-return lead) If L1= L2, Lt = 2 (L - M) Therefore, Conclusion: Placing forward and return current path close together is a an effective way of reducing inductance. So twisted pair or coaxial cable is preferable, then Lt X c )B) “C” value cant be too small, otherwise not sufficient charge storage to supply the transient currentExperiment: “C” value can be determined by measuring noise voltage across IC chip. Usually 470-1000 pF3. Decoupling capacitor placementBeing placed as close as to the IC is possible Fig.8-5 poor and better placement of decoupling capacitor (p290)Rule: keep the loop area between IC and decoupling capacitor as small as possible to decrease the inductanceEquivalent circuit for decoupling capacitor connected to IC Inductance consist of three components: inductance of capacitor itself inductance of PWB trace inductance of lead frame within IC 8.8 Noise Voltage Objective1. Following measurement should be made Ground noise voltage ; power-supply noise voltage2. The best method is to measure peak-differential ground noise voltage between various points on the board, and also the Vcc to ground voltage on each IC 8.9 Measuring Noise Voltage1. Consideration of measuring noise voltage1)bandwidth of measuring instrument (minimum 100MHz, better 200MHz)2) at high-F, CMMR of the instrument3)leads from the instrument to the circuit under test CUT2. Equal lead length of instrument , and perpendicular to the circuit boardFig.8-6 (p294) A) incorrect setup B) correct oneSUMMARY (小结)Chp. 9 DIGITAL CIRCUIT RADIATION（数字电路辐射）本章学习要求：了解如下主要概念、方法和内容。1. 差模辐射（辐射计算公式，环路面积，环路电流，Fourier级数，差模辐射包络等）2. 控制差模辐射3. 共模辐射4. 控制共模辐射（共模电压控制，电缆解偶与屏蔽，共模扼流圈，共模电流测量等）Introduction1. Emission control should be treated as a design problem, and throughout the design process2. Radiation parameter and methods for practical radiated emission are introduced in this chp.Radiation type in digital electronics:3 differential-mode(DM) radiation: result of current flowing around loop formed by conductor Fig.9-1 differential-mode radiation form PCB(p299)small loop antenna radiating magnetic field4. common-mode(CM) radiation: result of undesired voltage drop that cause part of circuit to be at a common-mode potential above “true” ground. When external cable connected to this, its driven by this CM potential and radiate electric field Fig.9-2 common-mode radiation from system cable(p299)small current segment (straight wire) radiating E field 9.1 Differential-Mode ( DM ) Radiation1. E field calculation for DM radiationFor loop area “A”, carrying current “I”, free space distance “r” V/mNote: for small loop , this is accurate; for large loop, this is approximateIf a circuit on a ground plane is measured, reflection effect should be considered. So and Conclusion: differential-mode radiation can be controlled by1)reducing the magnitude of current2) reducing the frequency of harmonic content of current3) reducing the loop area2. Loop area For digital circuit design, placing signal leads and their associated ground-return leads close together. Especially for clock leads, backplane wireing, and interconnecting cable.Example: by FCC Class B Limit measured at distance 3mIf I= 25 mA, f =30 MHz, loop area “A” =100 cm2, r= 3 m then =197 uV / m (about the twice the allowable emission of FCC Limit )But when loop area “A” 5 cm2E = 100 uV /m (meet FCC requirement)3. Loop current Measuring “I “by using accurate probe to clip the circuit wireLoop antenna configuration (p302)(A) a short loop antenna (B) a capacitor-terminal loopUsually a capacitor-loaded loop with zero-impedance is frequently assumed4.Fourier SeriesSince digital circuit use square wave, the Fourier series of the current should be known as I: peak-to-peak amplitude of the waved: duty cycletr: rise timeFig.9-3 example of Fourier spectrum from a 50% duty cycle (d=0.5) trapezoid wave (p303)So differential-mode radiated emission is calculated byStep1: calculate the current contained in each harmonicStep2: substitute this current and the respective frequency into “E” formulaStep3: calculation is then repeated for each harmonicFig.9-4 differential-mode radiated emission versus frequency (p304)Analysis: since so E(dB)or 40dBAlso because E(dB) (when f ) or -40dBConsidering above, we obtain Fig.9-6 9.2 Controlling Differential-Mode ( DM ) Radiation1. Board layoutDecrease the loop area of those carrying the system clock , because they are the primary noise sourceNotes: In almost all cases, emission from the clock exceeds the emission from all other parts of the circuitFig.9-5 Typical radiated emission spectrum form a digital circuit (p307)(A) with all circuit operational (B) with only clock circuit operationalConclusion: The maximum emission is about the same in both case2. Multilayer board3. Backplane4. Interconnecting Cable 9.3 Common-Mode ( CM ) Radiation1. Common-mode radiation is harder to control, and normally determines the overall radiated emission.2. Frequency of common-mode radiation: frequency of the ground potential, not the current flowing in the circuit3. Short monopole antenna“ l ” () , formed by cable, driven by voltage(the ground voltage). “r” in far field Practically if capacitor-plate loaded (when antenna or cable connected to another piece of equipment that is either ground or with sufficient capacitance to ground)4. Suppression of common-mode radiated emissionSince ECM (I,f,l) primary method of minimizing radiation is to limit current5. Consideration ECM f , and In Fourier series of currentFig.9-6 common-mode radiation emission versus frequency (p314)Notes :because of fall-off at higher-frequency, common-mode emission is only a problem at Therefore for rise time (tr , 20 dB (2)cable length l (3) the only parameter control is the CM current2. CM current control minimize the source of voltage that drive the antenna (usually ground potential)providing a large common-mode impedance (choke) in series with the cable shunting the current to ground (using decoupling capacitor) shielding the cable3. Common-mode voltage Fig.9-7 radiated emission with and without a ground grid (p316)Conclusion: effectiveness of a ground grid in reducing CM emission , but usually not enough4.Cable decoupling and shielding Both cable decoupling (shunting the current to ground ) and cable shielding need a “quite” or “clean ” groundSolution: by placing all I/O leads in one area of the board, and providing a separate low-impedance I/O ground connected to digital logic ground at only one pointFig.9-8 One implementation of grounding solution of “clean point” for digital circuit (p317)5. Common-mode chokeHowever effectiveness is limited