VHDL语言介绍外文文献翻译、中英文翻译

1、本科生毕业论文（设计）英文原文原文出处：DOUGLASLP.VHDL：programming by exampleMNew York：McGrawHill Professional2002FOREWORDVHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHD

2、L from initial concept of design documentation, to design implementation and func tional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor compa nies. This book has served as the authoritative source of practical information o

3、n the use of VHDL for users of the language around the world.The use of VHDL has evolved and its importance increased as semi conductor devices dimensions have shrunk. Not more than 10 years ago it was common to mix designs described with schematics and VHDL. But as design complexity grew, the indus

4、try abandoned schematics in favor of the hardware description language only. The successive revisions of this book have always kept pace with the industrys evolving use of VHDL.The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDLs package structure

5、to allow design ers, electronic design automation companies and the semiconductor indus try to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoper

6、 ability was possible.All of this was facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera.And when the ASIC industry needed a standard way to convey gate-level design data and timing information in VHDL, one of A

7、ccelleras progenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries) was created and ratified as offers designers a single language flow from concept to gate-level signoff.In the late 90s, the Verilog HD

8、L and VHDL industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, set register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages.But from the beginning, the lead

9、ership of the VHDL community has assured open and internationally accredited standards for the electronic design engineering community. The legacy of this teams work continues to benefit the design community today as the benchmark by which one measures openness.The design community continues to see

10、benefits as the electronic design automation community continues to find new algorithms to work from VHDL design descriptions and related standards to again push designer productivity.And, as a new generation of designers of programmable logic devices move to the use of hardware description language

11、s as the basis of their design methodology, there will be substantial growth in the number of VHDL users.This new generation of electronic designers, along with the current designers of complex systems and ASICs, will find this book invaluable . Updated with current ue of the standard, all will bene

12、fit from the years of use that have made the VHDL language the underpinning of successful electronic design.Introduction to VHDLThe VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in

13、the 70s and early 80s by the U.S. Department of Defense. Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements.VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to c

14、reate sophisticated electronic products. This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language with numerous language constructs that are capable of describing very complex behavior. Learning all the features of VHDL is not a simple task.

15、 Complex features will be introduced in a simple form and then more complex usage will be described.In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987. The IEEE 1076-1987 standard VHDL is t

16、he VHDL used in this book.(Appendix D contains a brief description of VHDL 1076-1993.) All the examples have been described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation environment from Model Technology Inc. VHDL TermsBefore we go any further, lets define some of the terms

17、that we use throughout the book. These are the basic VHDL building blocks that are used in almost every description, along with some terms that are redefined in VHDL to mean something different to the average designer. Entity. All designs are expressed in terms of entities. An entity is the most bas

18、ic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lowerlevel descriptions contained in it. These lower-level descriptions will be lowerlevel mentities contained in the top-level entity des

19、cription.Architecture. All entities that can be simulated have an architecturedescription. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design.Config

20、uration. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design

21、.Package. A package is a collection of commonly used data types andsubprograms used in a design. Think of a package as a toolbox that containstools used to build designs.Driver. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will hav

22、e two drivers.Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware. In VHDL, a bus is a special kind of signal that may have its drivers turned off.Attribute. An attribute is data that are attached to VHDL objects or pre

23、defined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device.Generic. A generic is VHDLs term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall del

24、ay, values for the rise and fall delays could be passed into the entity with generics.Process. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.Describing Hardware in VHDLVHDL Descri

25、ptions consist of primary design units and secondary design units. The primary design units are the Entity and the Package. The secondary design units are the Architecture and the Package Body. Secondary design units are always related to a primary design unit. Libraries are collections of primary a

26、nd secondary design units. A typical design usually contains one or more libraries of design units.EntityA VHDL entity specifies the name of the entity, the ports of the entity, and entityrelated information. All designs are created using one or more entities. Lets take a look at a simple entity exa

27、mple:ENTITY mux ISPORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT; x, : OUT BIT);END mux;The keyword ENTITY signifies that this is the start of an entity statement. In the descriptions shown throughout the book, keywords of the language and types provided with the STANDARD package are shown in ALL CAPITA

28、L letters. For instance, in the preceding example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type provided is BIT. Names of user-created objects such as mux, in the example above, will be shown in lower case.The name of the entity is mux. The entity has seven ports in the

29、 PORT clause. Six ports are of mode INand one port is of mode OUT. The four data input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs, s0 and s1, are also of type BIT. The output port is of type BIT. The entity describes the interface to the outside world. It specifies the num

30、ber of ports, the direction of the ports, and the type of the ports. A lot more information can be put into the entity than is shown here, but this gives us a foundation upon which we can build more complex examples.ArchitecturesThe entity describes the interface to the VHDL model. The architecture

31、describes the underlying functionality of the entity and contains the statements that model the behavior of the entity. An architecture is always related to an entity and describes the behavior of that entity. An architecture for the counter device described earlier would look like this:ARCHITECTURE

32、 dataflow OF mux ISSIGNAL select : INTEGER;BEGINselect = 0 WHEN s0 = 0 AND s1 = 0 ELSE1 WHEN s0 = 1 AND s1= 0 ELSE2 WHEN s0 = 0 AND s1 = 1 ELSE3;x = a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHENselect = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;END dataflow;The keyword ARCHITE

33、CTURE signifies that this statement describes anarchitecture for an entity. The architecture name is dataflow. The entitythe architecture is describing is called mux.The reason for the connection between the architecture and the entity is that an entity can have multiple architectures describing the

34、 behavior of the entity. For instance, one architecture could be a behavioral description, and another could be a structural description.The textual area between the keyword ARCHITECTURE and the keyword BEGIN is where local signals and components are declared for later use.In this example signal sel

35、ect is declared to be a local signal.The statement area of the architecture starts with the keyword BEGIN.All statements between the BEGINand the ENDnetlist statement are calledconcurrent statements, because all the statements execute concurrently.Default ConfigurationsThe simplest form of explicit

36、configuration is the default configuration. This configuration can be used for models that do not contain any blocks or components to configure. The default configuration specifies the configuration name, the entity being configured, and the architecture to be used for the entity. Following is an ex

37、ample of two default configurations shown by configurations big_count and small_count:LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY counter ISPORT(load, clear, clk : IN std_logic;PORT(data_in : IN INTEGER;PORT(data_out : OUT INTEGER);END counter;ARCHITECTURE count_255 OF counter ISBEGINPROCESS(clk

38、)VARIABLE count : INTEGER := 0;BEGINIF clear = 1 THENcount := 0;ELSIF load = 1 THENcount := data_in;ELSEIF (clkEVENT) AND (clk = 1) AND(clkLAST_VALUE = 0) THENIF (count = 255) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;END PROCESS;END count_255;ARCHITECTURE count_64k

39、 OF counter ISBEGINPROCESS(clk)VARIABLE count : INTEGER := 0;BEGINIF clear = 1 THENcount := 0;ELSIF load = 1 THENcount := data_in;ELSEIF (clkEVENT) AND (clk = 1) AND(clkLAST_VALUE = 0) THENIF (count = 65535) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;END PROCESS;END

40、count_64k;CONFIGURATION small_count OF counter ISFOR count_255END FOR;END small_count;CONFIGURATION big_count OF counter ISFOR count_64kEND FOR;END big_count;This example shows how two different architectures for a counter entity can be configured using two default configurations. The entity for the

41、 counter does not specify any bit width for the data to be loaded into the counter or data from the counter. The data type for the input and output data is INTEGER.With a data type of integer, multiple types of counters can be supported up to the integer representation limit of the host computer for

42、 the VHDL simulator. The two architectures of entity counter specify two different-sized counters that can be used for the entity. The first architecture, count_255, specifies an 8-bit counter. The second architecture, count_64k, specifies a 16-bit counter. The architectures specify a synchronous co

43、unter with a synchronous load and clear. All operations for the device occur with respect to the clock.Each of the two configurations for the entity specifies a different architecture for the counter entity. Lets examine the first configuration in more detail. The configuration design unit begins wi

44、th the keyword CONFIGURATION and is followed by the name of the configuration. In this example, the name of the configuration is small_count. The keyword OF precedes the name of the entity BEGIN configured (counter). The next line of the configuration starts the block configuration section. The keyw

45、ord FOR is followed by a name of the architecture to use for the entity being configured or the name of the block of the architecture that will be configured. Any component or block configuration information then existsbetween the FOR ARCHITECTURE clause and the matching END FOR.In this architecture

46、, there are no blocks or components to configure; therefore, the block configuration area from the FOR clause to the END FOR clause is empty, and the default is used. The configuration is called the default configuration, because the default is used for all objects in the configuration.The first con

47、figuration is called small_count and binds architecture count_255 with entity counter to form a simulatable object. The second configuration binds architecture count_64k with entity counter and forms a simulatable object called big_count.第 15 页 共 15 页原文出处：DOUGLASLP.VHDL：programming by exampleMNew Yo

48、rk：McGrawHill Professional2002VHDL语言介绍前言自1987年IEEE被批准后，VHDL语言已经在电子设计生产中处于核心地位。近15年来，电子设计自动化行业已从最初的概念设计文件，设计实施和功能验证扩大了使用VHDL语言。可以说，现代的VHDL燃料合成技术刺激了ASIC半导体公司的成长发展。这本书已经成为世界各地VHDL语言用户实际使用情况的权威信息源。半导体器件尺寸随着VHDL语言的演变和它重要性的增加而缩小。10年前这是用原理图和VHDL共同混合设计描述的。但是，随着设计的复杂性增长，该行业被遗弃的电路图只能用硬件描述语言来替代。这本书的历次修订始终跟上行业使

49、用VHDLyuyan的 变化。事实上，VHDL语言的适应性对其结构是一种贡献。业内人士认为使用VHDL语言的一揽子结构设计，使地球资源卫星，电子设计自动化公司和半导体产业尝试尝试新的语言观念，以确保良好的设计工具和数据互操作性。当相关的数据类型中发现的IEEE 1164标准被批准，这意味着设计数据互能力是可能的。所有这一切都促进了财团的系统、电子设计自动化和半导体公司的支持被称为Accellera。当VHDL语言之一的ASIC的行业需要一个标准的方式转达门级的设计数据和时间信息时，Accellera的祖先（ VHDL语言国际）为了建设一个配套的标准而组建了IEEE VHDL团队。IEEE 10

50、76.4 VITAL（ VHDL的倡议建立的ASIC图书馆）已建立并为设计人员提供了单一的语言流从概念到门级签收而被批准。90年代后期，Verilog HDL语言和VHDL行业团队合作使用共同的时间数据，如IEEE 1497 SDF，为设置寄存器传输级（ RTL ）标准、更多的改进设计方法和外部连接提供硬件描述语言。但是，从一开始，VHDL的领导层已经自信的为电子设计工程社区开放了国际认可的标准。这个团队工作的遗产继续有利于今天大众化的设计作为衡量公开性的基准。设计界继续以电子设计自动化的社会效益而继续从VHDL设计说明和相关标准来寻求新的算法，以再次推动设计师的生产力。此外，作为新一代的设计

51、师的可编程逻辑器件转向使用硬件描述语言为基础的设计方法，将大幅增加VHDL语言使用者的数量。这新一代的电子设计，以及目前的设计的复杂系统和ASIC ，会发现这本书非常宝贵。更新目前的价值标准，都将受益于多年的使用，使VHDL语言成为电子设计成功的基础。VHDL语言VHSIC硬件描述语言是一个行业标准的语言从抽象到具体的水平来描述硬件，VHDL语言在七八十年代初期是为美国国防部工作的。它是以ADA语言为根源，就像将被看到的整体结构的VHDL和其他的VHDL报表。自成立以来所使用的字面数以万计的工程师在全球各地建立先进的电子产品使VHDL语言的使用迅速增加。本章将开始缓和读者到复杂的VHDL语言。

52、VHDL语言是一个功能强大的语言，许多语言结构，能够描述非常复杂的行为。学习VHDL的所有功能不是一项简单的任务。复杂的特点将用一个简单的表格来介绍，然后用更复杂的用法来加以说明。1986年，有人提议VHDL语言作为IEEE标准。它经历了一些修改意见和修改，直至1987年12月获得通过，成为IEEE 1076标准。1076至1987年的IEEE标准的VHDL硬件描述语言是用这本书。（附录D载有简要说明的VHDL 1076年至1993年。）所有的例子说明了在IEEE 1076 VHDL语言，并用模型技术公司的VHDL仿真环境来汇编和模拟。VHDL术语在进一步说之前，我们使用的这本书来定义一些术语

53、，这些都是基本的VHDL积木中使用的每一个描述，重新定义VHDL意味着与平常设计的不同。实体：所有设计都体现在实体。一个实体是设计中最基本的。最上层水平的设计是最高层的实体。如果设计分层次，那么最高层的描述将有低层描述的说明附在它里面。结构：所有实体可以有一个架构的说明来模拟。该架构描述的行为实体。一个单一的实体可以有多个架构。一个架构可能是行为而另一个可能是一个结构描述的设计。配置：配置声明是用来约束一个组件实例的一双实体架构。一个配置可以被视为像一个零件清单进行设计。它描述的使用的每一个实体的行为，就像零件列表说明哪一部分用于每一部分的设计。包：包是一个收集常用数据类型和子程序中使用的设计

54、。想想包含使用的工具建立的设计的一个工具箱作为一个包。驱动程序：这是一个信号上的一个源。如果一个信号有两个来源，那么当两个来源是由两个驱动程序来起作用的。总线：这个词，“巴士”通常使我想起一组信号或某个特定的通信方式，用于设计的硬件。在VHDL语言，总线是一种特殊的信号，表明可能由驱动程序来完成。属性：一个关于VHDL对象连接到VHDL的物体或预先确定的数据的属性数据。例如，电流驱动能力的一个缓冲区或最高工作温度的装置。通用：泛指是VHDL语言传递信息实体参数的任期。例如，如果一个实体是一个门级模型的上升和下降延迟，上升和下降延误的值才能通过成为实体与仿制。进程：一个进程是执行的VHDL中的一

55、个基本单位。一切行动，是在模拟VHDL描述分为单个或多个进程。描述硬件的VHDLVHDL语言描述组成主要设计单位和二次设计单位。主要设计单位是实体和包装。二次设计单位是建筑和包装机构。二次设计单位总是与主要设计单位相关。图书馆是收藏主要和次要的设计单位。一个典型的设计通常包含一个或多个图书馆的设计单位。实体一个VHDL实体指定的实体名称，实体的端口，以及实体相关的信息。所有设计创建使用一个或多个实体。让我们来看看一个简单的实体例子：ENTITY mux ISPORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT; x, : OUT BIT);END mux;关键字

56、“实体”是开始一个实体声明的标志，在整本书的说明中，标准封装中关键字的语言和类型全部用大写字母来显示。例如，在前面的示例中，关键字是ENTITY, IS, PORT, IN, INOUT,，等等。如果标准型是少量的。用户创建像复用一样的姓名，在上面的例子中，将以小写显示。实体的名称是多路复用，该实体有7个端口和端口条款。6个端口，一个是输入端口，另一个是输出端口。4个数据输入端口(a, b, c, d)是位宽类型。这两个多路选择输入是s0 和 s1，也都是位宽类型。输出端口也是位宽类型。实体描述外界的接口。它规定了一些端口，端口方向和端口的类型。比起这里显示的信息，实体可以存放更多的信息，但是

57、这为我们提供了建立更复杂例子的基础。架构实体是描述接口的VHDL模型。构架描述了实体的基本功能，并包含了模拟实体行为的陈述。架构始终是涉及实体和描述实体的行为。计数设备的构架更早的像这样描述：ARCHITECTURE dataflow OF mux ISSIGNAL select : INTEGER;BEGINselect = 0 WHEN s0 = 0 AND s1 = 0 ELSE1 WHEN s0 = 1 AND s1= 0 ELSE2 WHEN s0 = 0 AND s1 = 1 ELSE3;x = a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHENselect = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;END dataflow;关键字ARCHITECTURE本声明描述了一个实体的构架。该架构的名字是数据流。该实体的构架是一种被称为多路复用的描述。实体和结构连接之间的原因是一个实体可以有多个架构来描述实体的行