quanta da0z08mb6d0 acer gateway nv42

1、5432101Z08 SYSTEM BLOCK DIAGRAMDDRII-SODIMM1+1.8VSUSCPU_CLKCLOCK GENERATORICS9LPRS476AKLFT SLG8SP628VTR RTM880N-795AMD S1g1Caspian ProcessorHOST 200MHz+SMDDR_VREFPG 7,8DDR II 667 MHZDDHTREF_CLKPCIE 100MHzNBGFX_CLKDDRII-SODIMM2+1.8VSUSUSB 48MHzNBGPP_CLKPG 7,8+SMDDR_VREF+1.2V+2.5V+1.8VSUS VCC_CORE+SMD

2、DR_VTERM(638 S1g1 socket)REF 14MHzSBLINK_CLKPG 3+3VNB CORE(1.01.1V)CPU THERMAL SENSORPG 4,5,6+NB_CORE+3VPG 8HT_LINK(1.0)800 MHZSide portPG 9Giga LANBCM5784M+3V_S5NBRS780MNPCIE 0 +1.5VRJ45 PG 21LVDS Panel(LED)+3VPG 21VINPG 18LVDS(1ch)21mm X 21mm, 528pin BGAPCIE 3CC+3V+5VCRTMini Card (WLAN)+1.5V+1.1V_

3、NB+1.2V+1.8V+3V+NB_COREPG 18+1.8VSUS+3VPG 22+1.8V+1.8VSUS SMDDRGFX_TX0-3HDMIPG 9,10,11,12+SMDDR_VTERMPG 19+5VSBSRC_CLK+SMDDR_VREFA_LINK (X4)USBP4Card Reader controllerCard ReaderPG 23+3VPCURTS5159ESATA - HDDPG 24SATA0PG 23+3V+3V_S5SBSB710+3V+5V+3VSUS3V/5V+3VUSB2.0 I/O Ports X1USB2.0USBP8+5VPCUSATA -

4、 ODDPG 24SATA4+5VPCUPG 25+5V+5V21mm X 21mm, 528pin BGAUSBP10BT CONN.BB+3VSUSPG 22Azalia+1.2V+1.2V_S5+1.8V+3V_S5+3V+5V VCCRTCAzalia Audio CodecCX20561-15zUSBP5PG 20WEBCAM+3VPG 13,14,15,16,17PG 18+3VUSBP0;USBP1MODEM CONN. (MDC)LPCUSB2.0 BoardHP+SPDF JACKMIC JACKPG 20AMPG1441PG 20PG 24+3.3V_SUSECWPCE77

5、5+5VPG 20+3V+5V+3V+3VPCUPG 26SpeakerPG 20SPIAAPOWER/BFlash ROMTouch PadMMB/BFANKeyboardPG 25+3VPCUPG 26PROJECT : Z08Quanta Computer Inc.PG 8PG 25+3VPG 26+3VPCU+5VPG 25SiiizeDocument NumberBLOCK DIAGRAMRev1ADate:Tuesday, Apriiilll 28, 2009Sheet1 of3654321+1.2V+1.2V+1.2V_S5+1.5V+2.5V+2.5VVCC_CORECPU C

6、ORE5432102DDCCBBAAPROJECT : Z08Quanta Computer Inc.SiiizeDocumenttt NumberChange ListRev1ADattte:Tuesday, April 28,2009Sheet 2 of3654321ModelREVDATECHANGE LISTNOTEHWC1A2009/04/092009/04/162009/04/172009/04/212009/04/222009/04/232009/04/272009/04/281.Page 11: Exchange Pin define for LVDS ON & PWM. 2.

7、Page 21: U20 Footprint change to trf-10-1-24p-nb4. 3.Page 16: L39 Footprint from RC0603 chenge to RC0805. 4.Page 21: R389,R425 P/N change to CS12204JA44.5.Page 22: CN23 Footprint change to mipcie-as0b223-s40n-7f-52p-nb4. 6.Page 23: R460 change to 33 ohm;C586 change to 10P for EMI.7. Page 26: Add Q37

8、,Q38,R484,R485 for MMB leakage.And 3RD_MBCLK & 3RD_MBDATA pull high from +3V to +3VPCU.8. Page 26: Add CP8,CP9 for EMI.9. Page 24: Remove R284;mount C347 for EMI. 10.Page 20: Remove R312;mount C365 for EMI. 11.Page 3: Mount C248 and change to 15P for EMI.12.Page 23: Remove R295;Mount C358 and change

9、 to 15P for EMI. 13.Page 12: Add C597,C598 30P (+NB_CORE) for EMI.Add C599,C600 30P (+1.2V_VDDHTTX) for EMI. Add C601,C602 30P (+1.2V) for EMI.14.R120,R112,R388,R116,R387 change to short pad_0402.15. Page 19: Del Q20,Q21,R196,R204;add R486,R487 for AMD suggestion.16. Page 18: CN2 footprint from msc-

10、rb30-5-fg-30p-l to msc-rb30-5-fg-30p-l-nb4. 17.R8,R10,R214,R216,R437,R200,R28,R4,R419,R266,R265,R275,R287,R293,R314,R319,R325,R332,R334,R258,R283,R146,R148,R198 change to short pad_0402.18.R106,R79,R117,R118,R480,R267,R482,L1 change to short pad_0603.19.R105,R438,R223,R249,R29,R181,L21 change to sho

11、rt pad_0805.20.Page 19:Modify HDMI detect circuit_Del R174,R447,R441,Q35,Q36,R442;add R312,R488,D31. 21.Page 18:U2 pin7 modify voltage from +5V to +3V.22. Page 26:Swap NET CP8,CP9.23. Page 20:Mount U14,C435,C418;unmount L47 for Audio noise issue. 24.Page 26:Modify Y1 Footprint.Power2009/04/102009/04

12、/172009/04/222009/04/232009/04/271. Page27： Mount PR141(10K ohm) for Charger Issue.2. Page32： Change Z08A PU5 part number from AL009338014 to AL009334000. 3.Page32： Change PC77 from 10u/4V_8 to 10u/10V_8.4. PL5,PL8,PL10,PL11 Footprint change to choke-etqp4lr36wfc-nb4. 5.page27: 1.add PC1632. PR110,P

13、R139,PR149 change to short pad3. PR141 un-mount6. page28: 1.PR87,PR90,PR106,PR190,PR91 change to short pad. 2.JP2,JP3 remove3. PR92 un-mount 4.PR101 mount7. page29: 1.JP4,JP5 remove2.PR44,PR43,PR18,PR19,PR128,PR131,PR117,PR5 change to short pad.3. add PC164,PC1654. add PR197,PR1968. page30: 1.Remove

14、 JP8,JP9 9.page31: 1.Remove JP1,JP6,JP72.PR35,PR41,PR155,PR148 change to short pad. 3.+1.8VSUS_SRC net name change to +1.8VSUS 4.VIN_1.8 net name change to VIN.5.+1.8V_out net name change to +1.8VSUS 10.PL3,PL7 Footprint change to choke-spm10040t-r45m200-4p. 11.page28: Del NET RT8206_VIN.12. page29:

15、 Add PC166 27uF/25V to VIN.13. page28: Modify component from AO4496 to AO6402A.5432103CLK_GEN_SLG8SP628(CLK)+3V+3V_CLK_VDDL26+1.2V+1.2V_CLK_VDDIOBK1608HS600/500mA/60ohm_6L31C252C238C228C250C216C233C218C219+3VC215BK1608HS600/500mA/60ohm_610u/6.3V_60.1u/10V_40.1u/10V_40.1u/10V_40.1u/10V_40.1u/10V_40.1

16、u/10V_40.1u/10V_40.1u/10V_4C251C241C237C242C217C220C24910u/6.3V_60.1u/10V_40.1u/10V_40.1u/10V_40.1u/10V_40.1u/10V_40.1u/10V_4RP15DD*4.7KX2Q22*2N7002E31CGCLK_SMB PCLK_SMBR216shortt0402SLG8SP628 ICS9LPRS480RTM880N-796P/N : AL8SP628000P/N : ALPRS480000 P/N : AL000880000+3VQ23*2N7002E3CGDAT_SMB PDAT_SMB

17、Place within 0.5 of CLKGEN R173 U6change to short pad 4/22*261/F_4450CPUCLKP_R CPUCLKN_RR1750_4CPUCLKP CPUCLKNCPUCLKP +3V+3V_CLK_48+3V_CLK_VDDVDDDOT VDDSRC VDDATIG VDDSB_SRC VDDSATA VDDCPU VDDHTT VDDREF VDD48CPUK8_0T CPUK8_0CR1710_4CPUCLKN To CPU forCLKIN164926L33BK1608HS600/500mA/60ohm_63/10 Modify

18、 for AMD suggestion.35NBGFX_CLKP4030ATIG0T ATIG0C ATIG1T ATIG1CNBGFX_CLKP 4829NBGFX_CLKNNBGFX_CLKN To NB for GFX_REFC255 2.2U/6.3V_6C2470.1u/10V_45528EXT_GFX_CLKP_RT59 T63EXT_GFX_CLKN_R562763CC37SBLINK_CLKPSB_SRC0T SB_SRC0C SB_SRC1T SB_SRC1CSBLINK_CLKP +1.2V_CLK_VDDIO1136SBLINK_CLKNSBLINK_CLKN To NB

19、 for GPPSB_REFSBSRC_CLKN To SB for PCIE_RCLKVDDSRC_IO0 VDDSRC_IO1 VDDATIG_IO VDDSB_SRC_IO VDDCPU_IO1732SBSRC_CLKPSBSRC_CLKP SBSRC_CLKN2531 R206*0_634+3V_CLK_VDD4722T69 T68 T67SRC0T SRC0C SRC1T SRC1C SRC2T SRC2C SRC3T SRC3C SRC4T SRC4C21C240 33p/50V_4120GND48 GNDDOT GNDSRC0 GNDSRC1 GNDATIG GNDSB_SRC

20、GNDSATA GNDCPU GNDHTT GNDREFCG_XIN127191514T7210 CLK_PCIE_WLANCLK_PCIE_WLAN#CLK_PCIE_WLANTo Minicard (WLAN)18CLK_PCIE_WLAN# Y3 14.318MHZ24QFN6413T74331298T7633p/50V_42 CLK_PCIE_LANCLK_PCIE_LAN#43CLK_PCIE_LAN To LAN chipCG_XOUT46CLK_PCIE_LAN#5260+3V42T58 T56 T73 T75SRC6T/SATAT SRC6C/SATAC SRC7T/27M_S

21、S SRC7C/27M_NS41CG_XIN616X1 X2CG_XOUT625R166CGCLK_SMB25453 NBHT_REFCLKP NBHT_REFCLKNNBHT_REFCLKP SMBCLK SMBDATHTT0T/66M HTT0C/66MCGDAT_SMBNBHT_REFCLKN To NB for HT_REF310K_4NB CLOCK INPUT TABLER20822_4CLK_Card48 CLK_48M_USBR20922_4 31CLKREQ4# CLK_PD#5164CLK_48M_USB_RCLK_48M_USB To SB for USBCLK LAN_

22、CLKREQ#PD#48MHz_0Q18RHU002N06CLKREQ0#SEL_HTT662359T70 T57CLKREQ0# CLKREQ1# CLKREQ2# CLKREQ3# CLKREQ4#REF0/SEL_HTT66 REF1/SEL_SATA REF2/SEL_27BCLKREQ1#SEL_SATAB4558+3VR185158/F_4CLKREQ2#4457SEL_27EXT_NB_OSC To NB for REFCLKEXT_NB_OSCCLKREQ3#39R183T55CLKREQ4#38C232C24815p/50V_4R164*10p/50V_4SLG8SP628*

23、10K_4 4/21 Mount C248 and change to 15P for EMI.CLKREQ2# 31 CLKREQ_WLAN#Q17*RHU002N06+3V_CLK_VDD0226 Modify for AMD suggestion.R1808.2K_4CLK_PD#SEL_SATAR19333_4R192 1 2 *90.9/F_4EXT_SB_OSC To SB for OSCCLOCKS nameRX780RS780Clock pin function+3V_CLK_VDDNBGFX_CLKP NBGFX_CLKNRP1001 STUFFRP1001 STUFFto

24、NB for VGA reference clockR1948.2K_4MXM_REFCLKP MXM_REFCLKNRP66 STUFFRP66 NCto M82-S external reference clock -RX780 onlySEL_SATAAASEL_HTT66SEL_27NBGPP_CLKP NBGPP_CLKNto NB for RX780 for PCIEX2 interface reference clock only RS780 is internal share with AC-LINK clock,RS780 not needRP1005 STUFFRP1005

25、 NCR195*8.2K_4R2028.2K_4R184 8.2K_4SBLINK_CLKP SBLINK_CLKNto NB for AC-LINK reference clockRP1003 STUFFRP1003 STUFF* default543212 2 2 212314265666768697071727374TGND0 TGND1 TGND2 TGND3 TGND4 TGND5 TGND6 TGND7 TGND8 TGND9PROJECT : Z08Quanta Computer Inc.SiiizeDocumenttt NumberCLOCK GENERATOR_SLG8SP6

26、28Rev1ADattte:Tuesday, April 28, 2009Sheet 3of36SEL_HTT66166 MHz 3.3V single ended HTT clock0 *100 MHz differential HTT clockSEL_SATA1 *100 MHz non-spreading differential SRC clock0100 MHz spreading differential SRC clockSEL_27127MHz and 27M SS outputs0*100 MHz SRC clockNB CLOCKSRX780RS780HT_REFCLKP

27、100M DIFF100M DIFFHT_REFCLKN100M DIFF100M DIFFREFCLK_P14M SE (1.8V)14M SE (1.1V)REFCLK_NNCvrefGFX_REFCLK100M DIFF100M DIFF(IN/OUT)*GPP_REFCLK100M DIFFNC or 100M DIFF OUTPUTGPPSB_REFCLK100M DIFF100M DIFFC244 190.9/F_4R214shortt04021Clock chip has internal serial terminations for differencial pairs, e

28、xternal resistors are reserved for debug purpose.54321VLDT_RUNU17A20mil0420mil D4ATHLON Control and DebugC455AE5 VLDT_RUNVLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0AE4 VLDT_RUN AE3 VLDT_RUN+2.5VD3D2D1AE2 VLDT_RUN4.7u/6.3V_6L5530ohm_4A+1.8VSUS+1.8VSUSVDDA_RUNN5T4 HT_NB_CPU_CAD_H15

29、HT_NB_CPU_CAD_L15 HT_NB_CPU_CAD_H14 HT_NB_CPU_CAD_L14 HT_NB_CPU_CAD_H13 HT_NB_CPU_CAD_L13 HT_NB_CPU_CAD_H12 HT_NB_CPU_CAD_L12 HT_NB_CPU_CAD_H11 HT_NB_CPU_CAD_L11 HT_NB_CPU_CAD_H10 HT_NB_CPU_CAD_L10 HT_NB_CPU_CAD_H9 HT_NB_CPU_CAD_L9 HT_NB_CPU_CAD_H8 HT_NB_CPU_CAD_L8 HT_NB_CPU_CAD_H7 HT_NB_CPU_CAD_L7

30、HT_NB_CPU_CAD_H6L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_

31、CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6HT_CPU_NB_CAD_H15 HT_CPU_NB_CAD_L15 HT_CPU_NB_CAD_H14 HT_CPU_NB_CAD_L14 HT_CPU_NB_CAD_H

32、13 HT_CPU_NB_CAD_L13 HT_CPU_NB_CAD_H12 HT_CPU_NB_CAD_L12 HT_CPU_NB_CAD_H11 HT_CPU_NB_CAD_L11 HT_CPU_NB_CAD_H10 HT_CPU_NB_CAD_L10 HT_CPU_NB_CAD_H9 HT_CPU_NB_CAD_L9 HT_CPU_NB_CAD_H8 HT_CPU_NB_CAD_L8 HT_CPU_NB_CAD_H7 HT_CPU_NB_CAD_L7 HT_CPU_NB_CAD_H6C510*100u/6.3V_3528P5T3C519M3V5M4U5C135 0.22u/10VC140

33、L5V44.7u/6.3V_63300p/50V_4R39300_4R396300_4M5V3K3Y5K4W5AB5AA5AB4AB3AD5AC5AD4 AD3U17DH3F8 F9AF6 H_THERMTRIP#VDDA2 VDDA1THERMTRIP_L PROCHOT_LH4AC7 H_PROCHOT#DDG5H5CPU_HT_RESET#B7T216RESET_L PWROK LDTSTOP_LF3CPU_ALL_PWROKA7T214 T215CPU_LDTSTOP#F4F10E5A5VID5 VID4 VID3 VID2 VID1 VID0H_VID5 H_VID4 H_VID3

34、H_VID2 H_VID1 H_VID0 F5CPU_SIC_RAF4C6SIC SIDVLDT_RUNN3T1CPU_SID_RAF5A6N2R1U2A4L1R96 44.2F_4CPU_HTREF1P6C5HT_REF1 HT_REF0M1U3 CPU_HTREF0R6B5 HT_NB_CPU_CAD_L6HT_CPU_NB_CAD_L6L0_CADIN_L6L0_CADOUT_L6R9544.2F_4L3V1 HT_NB_CPU_CAD_H5 HT_NB_CPU_CAD_L5 HT_NB_CPU_CAD_H4 HT_NB_CPU_CAD_L4L0_CADIN_H5 L0_CADIN_L5

35、 L0_CADIN_H4 L0_CADIN_L4L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4HT_CPU_NB_CAD_H5 HT_CPU_NB_CAD_L5 HT_CPU_NB_CAD_H4 HT_CPU_NB_CAD_L4L2U1T1place them to CPU within 1AC63/10 Modify for AMD suggestion.CPU_PRESENT_LJ1W2W3F6 VCCSENSE VSSSENSEVDD_FB_H VDD_FB_LK1E6A3PWR_PSI# PSI_LG1AA2AA3AB1T2T19

36、7 HT_NB_CPU_CAD_H3 HT_NB_CPU_CAD_L3 HT_NB_CPU_CAD_H2L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2HT_CPU_NB_CAD_H3 HT_CPU_NB_CAD_L3 HT_CPU_NB_CAD_H2H1W9 VDDIO_FB_H VDDIO_FB_LVDDIO_FB_H VDDIO_FB_LG3Y9PSI_L is a Power Status Indicator signal. This signal is asserted when the

37、 processor is in a low powerstate. PSI_L should be connected to thepower supply controller, if the controller supports “skipmode, or diode emulation mode”. PSI_L is asserted by the processor during the C3 and S1 states.G2AA1AC2AC3AD1AC1T198 HT_NB_CPU_CAD_L2 HT_NB_CPU_CAD_H1 HT_NB_CPU_CAD_L1 HT_NB_CP

38、U_CAD_H0 HT_NB_CPU_CAD_L0L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0HT_CPU_NB_CAD_L2 HT_CPU_NB_CAD_H1 HT_CPU_NB_CAD_L1 HT_CPU_NB_CAD_H0 HT_CPU_NB_CAD_L0CPUCLKINE1A9CLKIN_H CLKIN_LCPUCLKIN#F1A8E3E2J5Y4 HT_NB_CPU_CLK_H1 HT

39、_NB_CPU_CLK_L1 HT_NB_CPU_CLK_H0 HT_NB_CPU_CLK_L0L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0HT_CPU_NB_CLK_H1 HT_CPU_NB_CLK_L1 HT_CPU_NB_CLK_H0K5Y3CPU_DBRDYG10DBRDYJ3Y1J2W1CPU_TMSAA9E10 CPU_DBREQ#HT_CPU_NB_CLK_L0 TMS TCK TRST_L TDIDBREQ_LCPU_TCKAC

40、9CPU_TRST#AD9P3T5CPU_TDIAF9AE9 CPU_TDO HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1L0_CTLIN_H1 L0_CTLIN_L1L0_CTLOUT_H1 L0_CTLOUT_L1HT_CPU_NB_CTL_H1TDOP4R5HT_CPU_NB_CTL_L1N1R2R3 HT_NB_CPU_CTL_H0 HT_NB_CPU_CTL_L0L0_CTLIN_H0 L0_CTLIN_L0L0_CTLOUT_H0 L0_CTLOUT_L0HT_CPU_NB_CTL_H0 HT_CPU_NB_CTL_L0P1C9CPU_TEST29_H_FBC

41、LKOUT_PR384 80.6F_4TEST29_H TEST29_LCPU_TEST25_H_BYPASSCLK_HC8 CPU_TEST29_L_FBCLKOUT_NE9TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12CPU_TEST25_L_BYPASSCLK_LE8Athlon 64 S1 Processor SocketCPU_TEST19_PLLTEST0G9PLACE IT CLOSE TO CPU WITHIN 1 ROUTE AS 80 Ohm DIFFERENTI

42、AL PAIRCPU_TEST18_PLLTEST1CH10CVLDT_RUNAA7C2AE7 CPU_TEST24_SCANCLK1TEST24 TEST23 TEST22 TEST21 TEST20CPU_TEST17_BP3AD7 CPU_TEST23_TSTUPDD7T38 T41T3R99 *51/F_4 HT_NB_CPU_CTL_H1 HT_NB_CPU_CTL_L1*51/F_4CPU_TEST16_BP2E7AE8 CPU_TEST22_SCANSHIFTEN AB8 CPU_TEST21_SCANEN AF7 CPU_TEST20_SCANCLK2CPU_TEST15_BP

43、1F7CPU_TEST14_BP0R97C7CPU_TEST12_SCANSHIFTENBAC8J7CPU_TEST28_H_PLLCHRZ_PTEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8T37 T48+1.2VVLDT_RUNCPU_TEST28_L_PLLCHRZ_NC3 AA6 W7H8TEST7 TEST6 TEST5 TEST4 TEST3 TEST2AF8 CPU_TEST27_SINGLECHAIN AE6 CPU_TEST26_BURNIN# K8C4H_THERMDC H_THERMDC H_THERMDAL20H_THERMDAW

44、8Y6 AB6FBJ3216HS800_1206C176C175C192C190C189C191180p/50V_44.7u/6.3V_64.7u/6.3V_60.22u/10V_40.22u/10V_4180p/50V_4CPU_RSVD_MA0_CLK3_PH16 CPU_MA_RESET# B18 CPU_MB_RESET#P20T24 T200 T27 T201RSVD0 RSVD1 RSVD2 RSVD3RSVD8 RSVD9T33 T212CPU_RSVD_MA0_CLK3_NP19CPU_RSVD_MA0_CLK0_PN20CPU_RSVD_MA0_CLK0_NB3 CPU_RS

45、VD_VIDSTRB1N19T205 T203RSVD10 RSVD11C1CPU_RSVD_VIDSTRB0H6 CPU_RSVD_VDDNB_FB_PT34 T35 T204RSVD12 RSVD13 RSVD14G6 CPU_RSVD_VDDNB_FB_NCPU_RSVD_CORE_TYPED5MIISCR24 W18 R23 AA8 H18 H19RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20CPU_RSVD_MB0_CLK3_PR26T15 T12 T19 T17RSVD4 RSVD5 RSVD6 RSVD7CPU_RSVD_MB0_CLK3_NR25CPU_RSVD_MB0_CLK0_PP22CPU_RSVD_MB0_CLK0_NR22+1.8VSUSBB+1.8VSUS +1.8VSUS+3VQ13 2 R37D4 CPU_COREPGFDV301N*10K_4*BAS316R43 10K_4R47 C523 3900P/50V_4CPUCLKIN CPUCLKPR42 300_4R36100K_64.7K_4R54 *0