4-datasheetuserguideg2231datasheet

1、MSP430G2x31 MSP430G2SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011MIXEDSIGNALMICROCONTROLLERFEATURESLow Supply-Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode: 220 A at 1 MHz, 2.2 V Standby Mode: 0.5 A Off Mode (RAM Retention): 0.1 A Five Power-Saving ModesUltra-Fast

2、 Wake-Up From Standby Mode in Less Than 1 s16-Bit RISC Architecture, 62.5-ns Instruction Cycle TimeBasic Clock Module Configurations16-Bit Timer_A With Two Capture/Compare RegistersUniversal Serial Interface (USI) Supporting SPI and I2C (See Table 1)Brownout Detector10-Bit 200-ksps A/D Converter Wit

3、h Internal Reference, Sample-and-Hold, and Autoscan (See Table 1)Serial Onboard Programming,No External Programming Voltage Needed, Programmable Code Protection by Security FuseOn-Chip Emulation Logic With Spy-Bi-Wire InterfaceFor Family Members Details, See Table 1Available in 14-Pin Plastic Small-

4、Outline Thin Package (TSSOP) (PW), 14-Pin Plastic Dual Inline Package (PDIP) (N), and 16-Pin QFN Package (RSA)For Complete Module Descriptions, See theMSP430x2xx Family Users Guide (SLAU144)Internal Frequencies up to 16 MHz With One Calibrated FrequencyInternal Very Low Power Low-Frequency (LF) Osci

5、llator32-kHz CrystalExternal Digital Clock SourceDESCRIPTIONThe Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimize

6、d to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode

7、in less than 1 s.The MSP430G2x21/G2x31 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication capability using synchronous protocols (SPI or I2C). For configuration

8、 details, see Table 1.Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.Please be aware that an important notice concerning availability, standard warranty, and

9、use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Productio

10、n processing does not necessarily include testing of all parameters.Copyright 20102011, Texas Instruments IncorporatedMSP430G2x31 MSP430G2x21SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Table 1. Available Options(1)(1)For the most current package and ordering information, see the Package Op

11、tion Addendum at the end of this document, or see the TI web site at .Package drawings, thermal data, and symbolization are available at /packaging.(2)2Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedDeviceBSLEEMFlash (KB)RAM (B)Timer_AUSIADC10Chann

12、elClockI/OPackage Type(2)MSP430G2231IRSA16 MSP430G2231IPW14 MSP430G2231IN14-121281x TA218LF, DCO, VLO1016-QFN14-TSSOP14-PDIPMSP430G2221IRSA16 MSP430G2221IPW14 MSP430G2221IN14-121281x TA21-LF, DCO, VLO1016-QFN14-TSSOP14-PDIPMSP430G2131IRSA16 MSP430G2131IPW14 MSP430G2131IN14-111281x TA218LF, DCO, VLO1

13、016-QFN14-TSSOP14-PDIPMSP430G2121IRSA16 MSP430G2121IPW14 MSP430G2121IN14-111281x TA21-LF, DCO, VLO1016-QFN14-TSSOP14-PDIPMSP430G2x31 MSP430G2SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Device Pinout, MSP430G2x21N OR PW PACKAGE (TOP VIEW)DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/

14、SBWTDIOP1.7/SDI/SDA/TDO/TDI P1.6/TA0.1/SDO/SCL/TDI/TCLKDVCC P1.0/TA0CLK/ACLKP1.1/TA0.0 P1.2/TA0.1P1.3 P1.4/SMCLK/TCK P1.5/TA0.0/SCLK/TMS1413121110981234567NOTE:See port schematics in Application Information for detailed I/O information.RSA PACKAGE (TOP VIEW)1615 14 13P1.0/TA0CLK/ACLKP1.1/TA0.0 P1.2/

15、TA0.1P1.312341211109XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCKRST/NMI/SBWTDIO56 7 8NOTE:See port schematics in Application Information for detailed I/O information.Submit Documentation Feedback3Copyright 20102011, Texas Instruments IncorporatedP1.4/SMCLK/TCK P1.5/TA0.0/SCLK/TMS P1.6/TA0.1/SDO/SCL/TDI/TCLK

16、P1.7/SDI/SDA/TDO/TDIDVCC DVCC DVSSDVSSMSP430G2x31 MSP430G2x21SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Device Pinout, MSP430G2x31N OR PW PACKAGE (TOP VIEW)DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIOP1.7/A7/SDI/SDA/TDO/TDI P1.6/TA0.1/A6/SDO/SCL/TDI/TCLKDVCC P1.0/TA0CLK/ACLK/

17、A0P1.1/TA0.0/A1 P1.2/TA0.1/A2 P1.3/ADC10CLK/A3/VREF-/VEREF- P1.4/SMCLK/A4/VREF+/VEREF+/TCKP1.5/TA0.0/A5/SCLK/TMS1413121110981234567NOTE:See port schematics in Application Information for detailed I/O information.RSA PACKAGE (TOP VIEW)16 15 14 13P1.0/TA0CLK/ACLK/A0P1.1/TA0.0/A1P1.2/TA0.1/A2 P1.3/ADC1

18、0CLK/A3/VREF-/VEREF-12341211109XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCKRST/NMI/SBWTDIO56 7 8NOTE:See port schematics in Application Information for detailed I/O information.4Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedP1.4/SMCLK/A4/VREF+/VEREF+/TCKP1.5/TA0.0/SCLK/A5/TM

19、SP1.6/TA0.1/SDO/SCL/TDI/TCLK P1.7/SDI/SDA/TDO/TDIDVCC DVCC DVSSDVSSMSP430G2x31 MSP430G2SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Functional Block Diagram, MSP430G2x21XIN XOUTDVCCDVSSP1.xP2.x82ACLKClock SystemSMCLKMCLK16MHz CPUMABincl. 16 RegistersMDBEmulation 2BPUSIWatchdogTimer0_A2Br

20、ownoutWDT+UniversalJTAGInterfaceProtection2 CCRegistersSerial Interface SPI, I2C15-BitRST/NMIFunctional Block Diagram, MSP430G2x31XIN XOUTDVCCDVSSP1.xP2.x82ACLKClock SystemSMCLKMCLK16MHz CPUMABincl. 16 RegistersMDBEmulation 2BPUSIWatchdogTimer0_A2BrownoutWDT+UniversalJTAGInterface2 CCRegistersProtec

21、tionSerial Interface SPI, I2C15-BitRST/NMISubmit Documentation Feedback5Copyright 20102011, Texas Instruments IncorporatedSpy-BiWirePort P22 I/OInterrupt capability pull-up/down resistorsPort P18 I/OInterrupt capability pull-up/down resistorsADC10-Bit 8 Ch.Autoscan 1 ch DMARAM 128BFlash2kB 1kBSpy-Bi

22、WirePort P22 I/OInterrupt capability pull-up/down resistorsPort P18 I/OInterrupt capability pull-up/down resistorsRAM 128BFlash 2KB1KBMSP430G2x31 MSP430G2x21SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Table 2. Terminal Functions(1) MSP430G2x31 only(2) TDO or TDI is selected via JTAG instru

23、ction.(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset.6Submit Documentation FeedbackCopyright 20102011, Texas Instruments IncorporatedTERMINALI/ODESCRIPTIONNAMENO.N, PWRSAP1.0/ TA0

24、CLK/ ACLK/ A021I/OGeneral-purpose digital I/O pin Timer0_A, clock signal TACLK input ACLK signal outputADC10 analog input A0(1)P1.1/ TA0.0/ A132I/OGeneral-purpose digital I/O pinTimer0_A, capture: CCI0A input, compare: Out0 output ADC10 analog input A1(1)P1.2/ TA0.1/ A243I/OGeneral-purpose digital I

25、/O pinTimer0_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A2(1)P1.3/ ADC10CLK/A3/VREF-/VEREF54I/OGeneral-purpose digital I/O pin ADC10, conversion clock output(1) ADC10 analog input A3(1)ADC10 negative reference voltage(1)P1.4/ SMCLK/A4/ VREF+/VEREF+/ TCK65I/OGeneral-purpose digi

26、tal I/O pin SMCLK signal outputADC10 analog input A4(1)ADC10 positive reference voltage(1)JTAG test clock, input terminal for device programming and testP1.5/ TA0.0/A5/ SCLK/ TMS76I/OGeneral-purpose digital I/O pin Timer0_A, compare: Out0 output ADC10 analog input A5(1)USI: clock input in I2C mode;

27、clock input/output in SPI modeJTAG test mode select, input terminal for device programming and testP1.6/ TA0.1/A6/ SDO/ SCL/TDI/TCLK87I/OGeneral-purpose digital I/O pinTimer0_A, capture: CCI1A input, compare: Out1 output ADC10 analog input A6(1)USI: Data output in SPI mode USI: I2C clock in I2C mode

28、JTAG test data input or test clock input during programming and testP1.7/A7/ SDI/ SDA/TDO/TDI(2)98I/OGeneral-purpose digital I/O pin ADC10 analog input A7(1)USI: Data input in SPI mode USI: I2C data in I2C modeJTAG test data output terminal or test data input during programming and testXIN/ P2.6/ TA

29、0.11312I/OInput terminal of crystal oscillator General-purpose digital I/O pin Timer0_A, compare: Out1 outputXOUT/ P2.71211I/OOutput terminal of crystal oscillator(3) General-purpose digital I/O pinRST/ NMI/SBWTDIO109IResetNonmaskable interrupt inputSpy-Bi-Wire test data input/output during programm

30、ing and testTEST/ SBWTCK1110ISelects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and testDVCC115, 16NASupply voltageDVSS1413, 14NAGround referenceQFN Pad-PadNAQFN package pad connection to VSS recommended.MSP430G

31、2x31 MSP430G2SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011SHORT-FORM DESCRIPTIONCPUThe MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with s

32、even addressing modes for source operand and four addressing modes for destination operand.The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- register operation execution time is one cycle of the CPU clock.Four of the registers, R0 to R3, are de

33、dicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.The instruction set consists o

34、f the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.PC/R0SP/R1SR/CG1/R2CG2/R3R4R5R6R7R8R9R10R11R12R13Instruction SetThe instruction set consists of 51 instructions wit

35、h three formats and seven address modes. Each instruction can operate on word andbytedata. Table 3 shows examples of the three types of instruction formats; Table4 shows the address modes.R14R15Table 3. Instruction Word FormatsTable 4. Address Mode Descriptions(1)(1) S = source, D = destinationSubmi

36、t Documentation Feedback7Copyright 20102011, Texas Instruments IncorporatedADDRESS MODESDSYNTAXEXAMPLEOPERATIONRegisterMOV Rs,RdMOV R10,R11R10 R11IndexedMOV X(Rn),Y(Rm)MOV 2(R5),6(R6)M(2+R5) M(6+R6)Symbolic (PC relative)MOV EDE,TONIM(EDE) M(TONI)AbsoluteMOV &MEM,&TCDATM(MEM) M(TCDAT)IndirectMOV Rn,Y

37、(Rm)MOV R10,Tab(R6)M(R10) M(Tab+R6)Indirect autoincrementMOV Rn+,RmMOV R10+,R11M(R10) R11R10 + 2 R10ImmediateMOV #X,TONIMOV #45,TONI#45 M(TONI)INSTRUCTION FORMATSYNTAXOPERATIONDual operands, source-destinationADD R4,R5R4 + R5 - R5Single operands, destination onlyCALL R8PC -(TOS), R8- PCRelative jump

38、, un/conditionalJNEJump-on-equal bit = 0General-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose RegisterGeneral-Purpose Regi

39、sterGeneral-Purpose RegisterConstant GeneratorStatus RegisterStack PointerProgram CounterMSP430G2x31 MSP430G2x21SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Operating ModesThe MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake u

40、p the device from any of the low-power modes, service the request, and restore back to the low- power mode on return from the interrupt program.The following six operating modes can be configured by software:Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled ACLK and SMCL

41、K remain active, MCLK is disabled Low-power mode 1 (LPM1)CPU is disabledACLK and SMCLK remain active, MCLK is disabledDCOs dc generator is disabled if DCO not used in active modeLow-power mode 2 (LPM2)CPU is disabledMCLK and SMCLK are disabled DCOs dc generator remains enabled ACLK remains activeLow

42、-power mode 3 (LPM3)CPU is disabledMCLK and SMCLK are disabled DCOs dc generator is disabled ACLK remains activeLow-power mode 4 (LPM4)CPU is disabled ACLK is disabledMCLK and SMCLK are disabled DCOs dc generator is disabled Crystal oscillator is stopped8Submit Documentation FeedbackCopyright 201020

43、11, Texas Instruments IncorporatedMSP430G2x31 MSP430G2SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Interrupt Vector AddressesThe interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriat

44、e interrupt handler instruction sequence.If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the CPU goes into LPM4 immediately after power-up.Table 5. Interrupt Sources, Flags, and Vectors(1) A reset is generated if the CPU tries to fetch instructi

45、ons from within the module register memory address range (0h to 01FFh) or from within unused address ranges.(2) Multiple source flags(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.(4) Interrupt flags are located in the

46、module.(5) MSP430G2x31 only(6) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary.Submit Documentation Feedback9Copyright 20102011, Texas Instruments IncorporatedINTERRUPT SOURCEINTERRUPT FLAGSYSTEM INTERRUPTWORD ADDR

47、ESSPRIORITYPower-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range(1)PORIFG RSTIFG WDTIFG KEYV(2)Reset0FFFEh31, highestNMIOscillator faultFlash memory access violationNMIIFG OFIFG ACCVIFG(2)(3)(non)-maskable (non)-maskable (non)-maskable0FFFCh300FFFAh290FFF8h280FFF6h27Watchdog Ti

48、mer+WDTIFGmaskable0FFF4h26Timer_A2TACCR0 CCIFG(4)maskable0FFF2h25Timer_A2TACCR1 CCIFG, TAIFG(2)(4)maskable0FFF0h240FFEEh230FFECh22ADC10(5)ADC10IFG(4)(5)maskable0FFEAh21USIUSIIFG, USISTTIFG(2)(4)maskable0FFE8h20I/O Port P2 (two flags)P2IFG.6 to P2IFG.7(2)(4)maskable0FFE6h19I/O Port P1 (eight flags)P1

49、IFG.0 to P1IFG.7(2)(4)maskable0FFE4h180FFE2h170FFE0h16See (6)0FFDEh to 0FFC0h15 to 0, lowestMSP430G2x31 MSP430G2x21SLAS694I FEBRUARY 2010 REVISED DECEMBER 2011Special Function Registers (SFRs)Most interrupt and module enable bits are collected into the lowest address space. Special functio

50、n register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.Legendrw:rw-0,1: rw-(0,1):Bit can be read and written.Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is re

51、set or set by POR.SFR bit is not present in device.Table 6. Interrupt Enable Register 1 and 2Address76543210rw-0rw-0rw-0rw-0WDTIEWatchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode.Oscillator fault interrupt enable (No

52、n)maskable interrupt enableFlash access violation interrupt enableOFIE NMIIEACCVIEAddress76543210Table 7. Interrupt Flag Register 1 and 2Address76543210rw-0rw-(0)rw-(1)rw-1rw-(0)WDTIFGSet on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.Flag set on oscillator fault.Power-On Reset interrupt flag