datasheetam29lv160db

1、Am29LV160D16 Megabit (2 M x 8-Bit/1 M x 16-Bit)CMOS 3.0 Volt-only Boot Sector Flash MemoryDISTINCTIVE CHARACTERISTICSSingle power supply operation Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications Regulated voltage range: 3.0 to 3.6 volt read and write op

2、erations and for compatibility with high performance 3.3 volt microprocessorsManufactured on 0.23 m process technology Fully compatible with 0.32 m Am29LV160B deviceHigh performance Access times as fast as 70 nsUltra low power consumption (typical values at 5 MHz) 200 nA Automatic Sleep mode current

3、 200 nA standby mode current 9 mA read current 20 mA program/erase currentFlexible sector architectureEmbedded Algorithms Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors Embedded Program algorithm automatically writes and verifie

4、s data at specified addressesMinimum 1,000,000 write cycle guarantee per sector20-year data retention at 125C Reliable operation for the life of the systemPackage option 48-ball FBGA 48-pin TSOP 44-pin SOCFI (Common Flash Interface) compliant Provides device-specific information to the system, allow

5、ing host software to easily reconfigure for different Flash devicesCompatibility with JEDEC standards Pinout and software compatible with single- power supply Flash Superior inadvertent write protectionData# Polling and toggle bits Provides a software method of detecting program or erase operation c

6、ompletionReady/Busy# pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion (not available on 44-pin SO)Erase Suspend/Erase Resume Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operationHar

7、dware reset pin (RESET#) Hardware method to reset the device to reading array dataOne 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode)One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode)Supports full chip erase Sector Protection features

8、:A hardware method of locking a sector to prevent any program or erase operations within that sectorSectors can be locked in-system or via programming equipmentTemporary Sector Unprotect feature allows code changes in previously locked sectorsUnlock Bypass Program Command Reduces overall programming

9、 time when issuing multiple program command sequencesTop or bottom boot block configurations availableThis Data Sheet states AMDs current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technica

10、l specifications.Publication# 22358Rev: B Amendment/+3 Issue Date: November 10, 2000GENERAL DESCRIPTIONThe Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide da

11、ta (x16) appears on DQ15DQ0; the byte-wide (x8) data appears on DQ7DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device canThe host system can detect whether a program

12、or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.The sector erase architecture allows memory sectors to b

13、e erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sectorprotection

14、 feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro- gramming equipment.The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, an

15、y sector that is not selected for erasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also res

16、et the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the

17、standby mode. Power consumption is greatly reduced in both these modes.AMDs Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously

18、via Fowler-Nordheim tun- neling. The data is programmed using hot electron injection.als obe program med in s tand ard EPROM programmers.The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device ha

19、s separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.The Am29LV160D is entirely comman

20、d set compatible with the JEDEC single-power-supply Flash stan- dard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internall

21、y latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm t

22、hat auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four.Device erasure occurs by executing the erase command sequence. This initiates the Embed

23、ded Erase algorithman internal algorithm that automati- cally preprograms the array (if it is not already pro- grammed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.2Am29LV160DTABLE OF CONTENTSProduct Select

24、or Guide4Block Diagram4Connection Diagrams5Pin Configuration7Logic Symbol7Ordering Information8Device Bus Operations9Table 1. Am29LV160D Device Bus Operations9Word/Byte Configuration9Requirements for Reading Array Data9Writing Commands/Command Sequences10Program and Erase Operation Status10Standby M

25、ode10Automatic Sleep Mode10RESET#: Hardware Reset Pin11Output Disable Mode11Table 2. Sector Address Tables (Am29LV160DT)12Table 3. Sector Address Tables (Am29LV160DB)13Autoselect Mode14Table 4. Am29LV160D Autoselect Codes (High Voltage Method)14Sector Protection/Unprotection14Temporary Sector Unprot

26、ect15Figure 1. Temporary Sector Unprotect Operation15Figure 2. In-System Sector Protect/Unprotect Algorithms16Common Flash Memory Interface (CFI)17Table 5. CFI Query Identification String17Table 6. System Interface String18Table 7. Device Geometry Definition18Hardware Data Protection19Table 8. Prima

27、ry Vendor-Specific Extended Query19Low VCC Write Inhibit19Write Pulse “Glitch” Protection19Logical Inhibit19Power-Up Write Inhibit19Command Definitions20Reading Array Data20Reset Command20Autoselect Command Sequence20Word/Byte Program Command Sequence20Unlock Bypass Command Sequence21Figure 3. Progr

28、am Operation21Chip Erase Command Sequence21Sector Erase Command Sequence22Erase Suspend/Erase Resume Commands22Figure 4. Erase Operation23Command Definitions24Table 9. Am29LV160D Command Definitions24Write Operation Status25DQ7: Data# Polling25Figure 5. Data# Polling Algorithm25RY/BY#: Ready/Busy#26

29、DQ6: Toggle Bit I26DQ2: Toggle Bit II26Reading Toggle Bits DQ6/DQ226Figure 6. Toggle Bit Algorithm27DQ3: Sector Erase Timer28Table 10. Write Operation Status28Absolute Maximum Ratings29Figure 7. Maximum Negative Overshoot Waveform29Figure 8. Maximum Positive Overshoot Waveform29Operating Ranges29DC

30、Characteristics30Figure 9. ICC1 Current vs. Time (Showing Active andAutomatic Sleep Currents)31Figure 10. Typical ICC1 vs. Frequency31Test Conditions32Figure 11. Test Setup32Table 11. Test Specifications32Figure 12. Input Waveforms and Measurement Levels32AC Characteristics33Read Operations33Figure

31、13. Read Operations Timings33Hardware Reset (RESET#)34Figure 14. RESET# Timings34Word/Byte Configuration (BYTE#)35Figure 15. BYTE# Timings for Read Operations35Figure 16. BYTE# Timings for Write Operations35Erase/Program Operations36Figure 17. Program Operation Timings37Figure 18. Chip/Sector Erase

32、Operation Timings38Figure 19. Data# Polling Timings (During Embedded Algorithms). 39 Figure 20. Toggle Bit Timings (During Embedded Algorithms)39Figure 21. DQ2 vs. DQ6 for Erase andErase Suspend Operations40Figure 22. Temporary Sector Unprotect/Timing Diagram40Figure 23. Sector Protect/Unprotect Tim

33、ing Diagram41Figure 24. Alternate CE# Controlled Write Operation Timings43Erase and Programming Performance44Latchup Characteristics44TSOP and SO Pin Capacitance44Data Retention44Physical Dimensions45TS 04848-Pin Standard TSOP45TSR04848-Pin Reverse TSOP46FBC04848-Ball Fine-Pitch Ball Grid Array (FBG

34、A)8 x 9 mm47SO 04444-Pin Small Outline Package48Revision Summary49Revision A (January 1999)49Revision A+1 (April 19, 1999)49Revision B (November 23, 1999)49Revision B+1 (February 22, 2000)49Revision B+2 (November 7, 2000)49Revision B+3 (November 10, 2000)49Am29LV160D3PRODUCT SELECTOR GUIDENote: See

35、“AC Characteristics” for full specifications.BLOCK DIAGRAMRY/BY#DQ0DQ15 (A-1)VCCVSSSector SwitchesErase Voltage GeneratorInput/Output BuffersRESET#State ControlCommand RegisterWE#BYTE#PGM Voltage GeneratorChip Enable Output Enable LogicSTBCE# OE#STBVCC DetectorA0A194Am29LV160DData LatchY-GatingCell

36、MatrixTimerAddress LatchY-DecoderX-DecoderFamily Part NumberAm29LV160DSpeed OptionVoltage Range: VCC = 2.73.6 V-70-90-120Max access time, ns (tACC)7090120Max CE# access time, ns (tCE)7090120Max OE# access time, ns (tOE)303550CONNECTION DIAGRAMSA15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE#RESET#NC NC RY/B

37、Y#A18 A17 A7 A6 A5 A4 A3 A2 A1123456789101112131415161718192021222324484746454443424140393837363534333231302928272625A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8DQ0 OE# VSS CE# A0Standard TSOPA16 BYTE#VSS DQ15/A-1DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 D

38、Q10 DQ2 DQ9 DQ1 DQ8 DQ0 OE#VSSCE# A0123456789101112131415161718192021222324484746454443424140393837363534333231302928272625A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE#RESET# NCNC RY/BY# A18 A17A7 A6 A5 A4 A3 A2 A1Reverse TSOPAm29LV160D5CONNECTION DIAGRAMSRESET#A18 A17 A7 A6 A5 A4 A3123456784443424140393

39、8373635343332313029282726252423WE# A19 A8 A9 A10 A11 A12 A13 A14 A15 A16BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4VCCA2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11910111213141516171819202122SOSpecial Handling InstructionsSpecial handling is required for Flash Memory products in FBGA p

40、ackages.Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.6Am29LV160DFBGATop View, Balls Facing DownA6B6C6D6E6F6G

41、6H6 A13A12A14A15A16BYTE# DQ15/A-1VSSA5B5C5D5E5F5G5H5 A9A8A10A11DQ7DQ14DQ13DQ6A4B4C4D4E4F4G4H4 WE#RESET#NCA19DQ5DQ12VCCDQ4A3B3C3D3E3F3G3H3 RY/BY#NCA18NCDQ2DQ10DQ11DQ3A2B2C2D2E2F2G2H2 A7A17A6A5DQ0DQ8DQ9DQ1A1B1C1D1E1F1G1H1 A3A4A2A1A0CE#OE#VSSPIN CONFIGURATIONLOGIC SYMBOLA0A19=20 addresses15 data inputs

42、/outputsDQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)Selects 8-bit or 16-bit mode Chip enableOutput enable Write enable Hardware reset pinReady/Busy output (N/A SO 044)3.0 volt-only single power supply(see Product Selector Guide for speed options and voltage supply toleranc

43、es)Device groundPin not connected internally20 DQ0DQ14 =16 or 8DQ15/A-1=BYTE# CE# OE# WE# RESET#RY/BY#= VCC=VSS NC=Am29LV160D7A0A19DQ0DQ15(A-1)CE# OE#WE# RESET#BYTE#RY/BY#(N/A SO 044)ORDERING INFORMATIONStandard ProductsAMD standard products are available in several packages and operating ranges. Th

44、e order number (Valid Combi- nation) is formed by a combination of the elements below.Am29LV160DT-70ECTEMPERATURE RANGEC IE=Commercial (0C to +70C)=Industrial (40C to +85C)=Extended (55C to +125C)PACKAGE TYPEE F SWC=48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) 48-Pin Thin Small

45、Outline Package (TSOP) Reverse Pinout (TSR048) 44-Pin Small Outline Package (SO 044)48-ball Fine-Pitch Ball Grid Array (FBGA)0.80 mm pitch, 8 x 9 mm package (FBC048)SPEED OPTIONSee Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET B=Top sector Bottom sectorDEVICE NUMBER/DES

46、CRIPTIONAm29LV160D16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory3.0 Volt-only Read, Program, and EraseValid CombinationsValid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid comb

47、inations and to check on newly released combinations.8Am29LV160DValid Combinations for FBGA PackagesOrder NumberPackage MarkingAm29LV160DT-70, Am29LV160DB-70WCC, WCI, WCEL160DT70V, L160DB70VC, I, EAm29LV160DT-90, Am29LV160DB-90L160DT90V, L160DB90VAm29LV160DT-120, Am29LV160DB-120L160DT12V, L160DB12VV

48、alid Combinations For TSOP and SO PackagesAm29LV160DT-70, Am29LV160DB-70EC, EI, EE,FC, FI, FE, SC, SI, SEAm29LV160DT-90, Am29LV160DB-90Am29LV160DT-120, Am29LV160DB-120DEVICE BUS OPERATIONSThis section describes the requirements and use of the device bus operations, which are initiated through the in

49、ternal command register. The command register it- self does not occupy any addressable memory loca- tion. The register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. The contents ofthe register serve as inputs to the inter

50、nal state ma- chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.Table 1. Am29LV160D Device B

51、us OperationsLegend:L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).2. The sector protect and sector unprotect functions may also b

52、e implemented via programming equipment. See the “Sector Protection/Unprotection” section.Word/Byte ConfigurationThe BYTE# pin controls whether the device data I/O pins DQ15DQ0 operate in the byte or word configura- tion. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15D

53、Q0 are active and con- trolled by CE# and OE#.If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0DQ7 are ac- tive and controlled by CE# and OE#. The data I/O pins DQ8DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.main at VIH. The BYTE# pin determines whether the de- vice outputs array data in words or bytes.The internal state machine is set for reading array data upon device p