ARM培训讲义提纲

ARM 位：西安电子科技大 写：何方 编写日期：2005年7月1 ARM3大热点是：第三、四代移动通信技术、数字电视嵌入式操作系统与常见的单片机、DSPDSP处理器：速度、IO设计指标、处理器的软件支持、处理器调试方式、处理器提供商的ARM芯片作为该系统的核心芯片。ARMAdvancedRISCMachines的缩写，ARM1990ARM以低成本、市场。ARMIP供应商，只做设计。ARM处理器系列有：ARM7系列、ARM9系列、ARM9E系列、ARM10系列、SecurCoreSC100、StrongARM、XScaleARM7系列、ARM9系列：1）ARM7系列：0.9MIPS/MHz3级流水、冯.ARM7TDMI和ARM720T；T16THUMB指令，D支持在片调试，M增强型乘法器，产生全64位结果，I:ICE2）ARM9系列：1.1MIPS/MHz5ARM920T、基于ARMLOGIC等。注意：ARM9ARM7ARM920TARM920TARM920TCP15协处理器内存管理单元ARM芯片的汇编语言。ARMARMV4V5V4，THUMBARM状态指令长度：32位、16操作模式：7种寄存器：316个状态寄存器ARMARMARMARMARM4－1所示

4－1：ARM1ARM执行ARM4－24－3ARM指令集：4－2：4－2：ARM

4－3：ARMARMCPSR条件码和指令条件域的状态被有条件地执行。该域（31:28）C、N、ZV标志的状态满足该域的16个可能条件，每种由复加在指令记忆符后的一个双字符后缀表示。例如，Branch（B为汇编语言）BEQ表示“BranchifEqual”Z标志被置位时执行ALCPSR4－4给出了条件码概况：4－4：ARMARM4－4。RnPC来执行一个分支。这个令时，Rn[0]ARMTHUMB指令对指令流进行解码。指令格4－1所示：4－1：BX★★BX- ；{cond}为双字母条件记忆符（即条件码），见表4－4，而Rn★使用R15R15作操作数，该情况未定义。 R0,Into_THUMB+1 R5, ; ;汇编作为ARM★★2分支与带链接分支（B、4－44－24－2：B、BL字节的分支。该指令偏置必须考虑预取操作，它会引起程序计数器PC超前当前指令2（8个字节）★存器以被Rn存作堆栈指针，使用LDMRn!,{..PC}。★★B{L}{cond}<expression> 常用请求带链接分支的指令形式。如果缺省，R14旧的PC值存入R14 如表4－4中所示的双字母助记符（条件码），如果缺省，默认为<expression>目标单元，汇编程序计算偏移量。 Bthere CMP ;R1＝0 ; ;ADDS R1＝R1＋1,设置CPSRBLCC ;C＝0,★★3数据处理指令仅在条件为真时被执行，参见表4－4。该指令编码如下图4－34－3（Rn（ImmOP2OP2OP2（OP1+OP2）★CPSR数据处理运算可分为逻辑运算和算术运算，逻辑运算（ND、EOR、TST、Q、ORR、OV、BIC、N）对操作数的所有相应位或产生结果的操作数执行逻辑运算。如果S位被置位（并且Rd不是R15，见下表），则CPSR中的V标志不受影响，C标志将被置位来执行barrelshifer（或当移位操作为LSL#0时保护），Z被置为结果bit31的逻辑值。4－5R15ALUbit31被置位，Z标志当且仅当结果全零时被置位，Nbit31（如果认为操作数为两个独立的有符号数时指示结果为负）★4-4ARM★50~31（LSL）Rm的内容并将每一位移动指定量到更有意义的位置。结果的最不重要位以零shifterCPSRS位。例如，LSL#54－5所示。

4－5置。LSR#54－6所示。4－6所以汇编程序将LSR#0（以及ASR#0和ROR#0）转换成LSL#0，并允许指定LSR#32。算术右移（ASR）Rmbit312个独立符号状态中的符号，例如，ASR#54－74－7Rmbit312Rmbit31Rmbit3110逻辑右移中常用零来填充高位。例如，ROR#54－8所示。4－8期望给ROR#0的移位域形式用于对barrelshifter这个循环右移是它使用附加的CPSR的C标志来提供一个要被移位的33位的数量到Rm内容4－9★如果该字节为零，Rm未改变的内容将被当作第二操作数，并且旧的CPSR的C标志值LSL32结果为零，进位输出等于Rm的0LSL大于32LSR32结果为零，进位输出等于Rm的31LSR大于32ROR32结果等于Rm，进位等于Rm的31RORn结果和进位与RORn-32相同，这里n大于32；因此不断从n中减去32，直到nbit71★★写入当Rd为R15且S标志置位时，操作结果被放入R15，对应于当前模式的SPSR被移入★用R15如果R15（PC）为前8个字节。如果用寄存器指定移位量，则PC为前12在ARM920T中TEQP的功能是：如果处理器工作在特许模式就将SPSR_<mode>移入CPSR指令周期：数据处理指令增加的周期数如下表4-4-6注：S、NI分别定义为顺序（S-周期、非顺序（N-周期）和内部（I-周期。 <opcode>{cond}{S} CMP,CMN,TEQ,TST无结果指令<opcode>{cond} <opcode>{cond}{S} Rm{,<shift>}或 双字母条件助记符，见表 如果S表示(指CMP,CMN,TEQ,TST)，置位条件码Rd,Rn和 寄存器号表达 如果使用，汇编程序将会产生一个移位的立即8 <Shiftname><register><shiftname>#expression,RRX带 ASL,LSL,LSR,ASR,ROR.(ASL与LSL一样 ;如果Z标志置位，使 R4,R5,R7,LSR;通过R2底部字节数逻辑右移R7，从R5;将答案放入;;从中断返回，并从SPSR方式保存□□4PSR转移（MRS、□

4－10：MRS、MSRARM920T□.PSR□.PSR状态时，程序不应当依赖保留位的特定值，因为将来的处理器可能会将它们10。 ;复制BICR0,R0,#0x1F ;回写修改后的PSR中的条件方式码时，可直接将值写入标志位而不必影响控N、Z、CV标志置位： ;PSR8□PSR1SS定义为顺序（S-周期。–MRS{cond}–MSR{cond}<psr>,Rm–MSR{cond}□.MSR–只将立即数转移到PSRMSR{cond}□ RdandRm CPSR,CPSR_all,SPSR或SPSR_all.(CPSR和CPSR_all与SPSR和意义相同 CPSR_flg或 ;CPSR[31:28]<-Rm[31:28] ;CPSR[31:28]<-Rm[31:28] CPSR_flg,#0xA0000000;CPSR[31:28]<-0xA(setN,C;clearZ,V) ;Rd[31:0]<-CPSR[31:0] ;CPSR[31:0]<- ;CPSR[31:28]<-MSRCPSR_flg,#0x50000000 ;CPSR[31:28]<-0x5(setZ,V;clearN,C)MSRSPSR_all,Rm ;SPSR_<mode>[31:0]<-Rm[31:0]MSR ;SPSR_<mode>[31:28]<-

MSR ;SPSR_<mode>[31:28]<-0xC(setN,Z;MRS ;Rd[31:0]<-□□5乘和带累加的乘（MUL、4－11：MUL、MLA323232位结果是一样的。这些32位，既可用于有符号乘法，也可用于无符号乘法。操作数 操作数 结0xFFFFFFF6 □RdRm一样。R15必须不能被当作操作数或目标寄Rd、RnRs可用作同一个寄存器。□CPSR标志：□MUL指令占用1S+mI周期，MLA指令占用1S+(m+1)I周期，这里S和I分别代表连续周期）和内部（I周期） 如果乘数操作数[32:8]位为全0或全如果乘数操作数[32:16]位为全0或全如果乘数操作数[32:24]位为全0或全□MUL{cond}{S}Rd,Rm,RsMLA{cond}{S}Rd,Rm,Rs,Rn 双字母条件助记符，见表 Rd,Rm,RsandRn ; ;ConditionallyR1:=R2*R3+R4,Settingcondition□□6长乘和带累加的长乘（MULL、该指令仅当条件为真时执行，参见表4－4。指令编码见下图4－124－12：MULL、MLAL（UMULL和SMULL）32RdHi,RdLo:=Rm*Rs的结果。6432RdLo32RdHi。带累加乘法形式（UMLALSMLAL）3264位数得RdHi,RdLo:=Rm*Rs+RdHi,RdLo的结果。6432RdLo读取，64位32RdHi读取，6432RdLo32RdHi。□□CPSR□对有符号指令SMULL、□..对无符号指令UMULL、□..SI分别代表连续（S周期）和内部（I周期）。表4－7.这里 双字母条件助记符，见表 RdLo,RdHi,Rm, 除R15 ;R4,R1:=R2*R3 ;R5,R1:=R2*R3+R5□□7该指令仅当条件为真时执行参见表4－4。指令编码见下图4－134-13□在指令中，基址寄存器的偏移量既可以是12bit的无符号立即数，也可以是一个第二寄关于寻址方式是增加还是减少模式，指令的W位（即D21）给出了可选项。当W=1=0时，基址寄存器值不变。在前索引位是多余的，并且总被设置为0。因此前索引数据传输总是回写到已经修改的基址寄存器。在后索引数据传输中W位使得在非特权模式下□□该指令级别可用于在ARM920T寄存器和存储器之间转移一个字节（B=1）（B=0）□Little-EndianLDRB7~0这样的802-2。0~70~2存取的半字将0~1516bit31bit31。4-14.Little-Endian□Big-Endian802-1。bit31bit31。□R15不能将R15用作寄存器偏置（Rm） 所以不能使用后寻址的LDR或STR指令，这里Rm是与Rn□□分别定义为顺序（S-周期、非顺序（N-周期）和内部（I-周期。STR2N执行周□<LDR|STR>{cond}{B}{T}Rd,这里 双字母助记符，见表 如果出现B RnandRm <Address>可以是表示产生一个地址:汇编程序将会产生一条指令，该指令以PC预索引寻址 [Rn,<#expression>]{!}<expression>[Rn,{+/-}Rm{,<shift>}]{!}变址寄存器+/-偏置，由<shift>后索引寻址 <expression>[Rn],{+/- 如果出现!写回基本寄存器(见W位 □□8半字和有符号数据转移4－44-15、4－164-15.4-16.□8bit（可能被移位）U=1时基址寄存器RnU0时基址寄存器Rn偏移量的修改可以在基址寄存器被用于传输地址之前（前索引P=1）或之后（后索引P=0）关于寻址方式是增加还是减少模式，指令的W位（即D21）给出了可选项。当W=1=0时，基址寄存器值不变。在前索引当选择后索引寻址时，回写位不应该被置为高（即W=1）□当设置S=0和H=1□时，L位不应该为0(表示存储)。LDRSB指令装载所选的字节到目的寄存器中的7～0位，同时在高24LDRSH指令装载所选的字节到目的寄存器中的15～0位，同时在高16位进行符号扩□端点形式和字节/8位，其余的位作符号扩展。（A[1]=1A[0]=1ARM920T将导入一个无法预测的值。这个被选半字被放入目标寄存器的16位；对于其余的位，LDRSH作符号扩展；LDRH0。半字存储（STRH）21631~0。外部存8位，其余的位作符号扩展。（A[1]=1A[0]=1ARM920T将导入一个无法预测的值。这个被选半字被放入目标寄存器的16位；对于其余的位，LDRSH作符号扩展；LDRH0。□使用当R15被用作基址寄存器(Rn)，则不应该指定回写位。当将R15用作基址寄存器时，必须记住它包含了在当前指令地址上的一个8bytes地址。R15不能被用作移位寄存器当R15被用作一个半字存储指令(STRH)的源寄存器(Rd)时，存储地址必须是指令地□□LDR（H、SH、SB）1S+1N+1I周期，LDR（H、SH、SB）PC2S+2N+1I周期，这里，S、NI分别定义为顺序（S-周期、非顺序（N-周期和内部周期。STRH2N□ 条件码，参见表 装载有符号字节(仅对于LDR有效 装载有符号半字(仅对于LDR有效 <Address>可以是 预索引寻址 [Rn,<#expression>]{!}<expression>[Rn,{+/-}Rm{,<shift>}]{!}变址寄存器+/-偏置，由<shift>后索引寻址 <expression>[Rn],{+/- RnRm用作寄存器操作数。如果Rn是R15，则汇编后将在当前ARM920T 如果出现!写回基本寄存器(见W位 ;将存在R2-R3地址中的半字装入R1，并回写R2 ;将R3中的半字存储到R14+14中，不回写 R8，[R2],#- ;将R2地址中的有符号数据字节存入R8中，并回写R2-到R2 ;有条件，将R0存储地址中的内容半字装入R11 ;产生PC相对于地址FRED的相对偏移量 R5,[PC,#(FRED-HERE-8)];存储R5中的半字到地址FRED中□□9块数据转移（LDM、4－44-17块传输指令用于装载(LDM)或存储(STM)当前的可以使用的存储器。它们支持所有可寄存器列表在指令里面占有16位，每一个位对应一个寄存器。如bit0＝1，表示对R0进4-17.□从最低存储器地址导入。假设考虑传输R1、R5、R7，基址寄存器Rn=0x1000，同时回写修改基址寄存器(W=1)。图4－22给出了传输的结果。□4-18.4-19.4-20.4-21.□使用S对于LDM和STMR15LDMSTMR15INCLUSIONOFTHEBASEINTHEREGISTERDATAAbortduringSTM在STMAbortsduringLDM在LDMn为转移的字节数。这里 括在{}(即{R0,R2- 如果出现请求，回写(W=1)，其余 4－8参考堆栈要求的形式，FD,ED,FA,EA定义了前/后索引和上/下偏移。F和E“满”或“空”A和DIA,IB,DA,DB用于堆栈以外的其他LDM/STMLDMFD ;将3STMIAR0,{R0- ;LDMFD R15□.(SP),CPSRLDMFDSP!,{R15}^ ;R15□.(SP),CPSR<-SPSR_mode，仅用于特权模式STMFDR13,{R0-R14}^ ;将用户模式寄存器放入堆栈中，仅用于特权模式STMEDSP!,{R0- ;将R0到R3存储到空间，同时R14 ;修改LDMEDSP!,{R0- ;SINGLEDATASWAP3-23.Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-23.Thedataswapinstructionisusedtoswapabyteorwordquantitybetweenaregisterandexternalmemory.Thisinstructionisimplementedasamemoryreadfollowedbyamemorywritewhichare“locked”together(theprocessorcannotbeinterrupteduntilbothoperationshavecompleted,andthememorymanageriswarnedtotreatthemasinseparable).Thisclassofinstructionisparticularlyusefulforimplementingsoftwaresemaphores.Theswapaddressisdeterminedbythecontentsofthebaseregister(Rn).Theprocessorfirstreadsthecontentsoftheswapaddress.Thenitwritesthecontentsofthesourceregister(Rm)totheswapaddress,andstorestheoldmemorycontentsinthedestinationregister(Rd).Thesameregistermaybespecifiedasboththesourceanddestination.TheLOCKoutputgoesHIGHforthedurationofthereadandwriteoperationstosignaltotheexternalmemorymanagerthattheyarelockedtogether,andshouldbeallowedtocompletewithoutinterruption.Thisisimportantinmulti-processorsystemswheretheswapinstructionistheonlyindivisibleinstructionwhichmaybeusedtoimplementsemaphores;controlofthememorymustnotberemovedfromaprocessorwhileitisperformingalockedoperation.3-23-23BYTESANDThisinstructionclassmaybeusedtoswapabyte(B=1)oraword(B=0)betweenanARM920Tregisterandmemory.TheSWPinstructionisimplementedasaLDRfollowedbyaSTRandtheactionoftheseisasdescribedinthesectiononsingledatatransfers.Inparticular,thedescriptionofBigandLittleEndianconfigurationappliestotheSWPinstruction.USEOF使用DonotuseR15asanoperand(Rd,RnorRs)inaSWPDATAIftheaddressusedfortheswapisunacceptabletoamemorymanagementsystem,thememorymanagercanflagtheproblembydrivingABORTHIGH.Thiscanhappenoneitherthereadorthewritecycle(orboth),andineithercase,theDataAborttrapwillbetaken.Itisuptothesystemsoftwaretoresolvethecauseoftheproblem,thentheinstructioncanberestartedandtheoriginalprogramcontinued.INSTRUCTIONCYCLESwapinstructionstake1S+2N+1Iincrementalcyclestoexecute,whereS,NandIaredefinedassequential(S-cycle),non-sequential,andinternal(I-cycle),respectively.周期）和内部（I-周期ASSEMBLER<SWP>{cond}{B} Two-characterconditionmnemonic.SeeTable3- IfBispresentthenbytetransfer,otherwisewordtransfer Expressionsevaluatingtovalidregisternumbers ;LoadR0withthewordaddressedbyR2,;storeR1at ;LoadR2withthebyteaddressedbyR4,;storebits0to7ofR3atSWPEQ ;Conditionallyswapthecontentsof;wordaddressedbyR1with<SWP>{cond}{B} 双字母条件助记符，见表3- 如果出现B

0~7SWPEQ ;有条件地与R0交换以R1SOFTWAREINTERRUPTTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-24,below.3-23-243-24.ThesoftwareinterruptinstructionisusedtoenterSupervisormodeinacontrolledmanner.Theinstructioncausesthesoftwareinterrupttraptobetaken,whicheffectsthemodechange.ThePCisthenforcedtoafixedvalue(0x08)andtheCPSRissavedinSPSR_svc.IftheSWIvectoraddressissuitablyprotected(byexternalmemorymanagementhardware)frommodificationbytheuser,afullyprotectedoperatingsystemmaybeconstructed.（由外部存储器管理硬件），RETURNFROMTHEThePCissavedinR14_svcuponenteringthesoftwareinterrupttrap,withthePCadjustedtopointtothewordaftertheSWIinstruction.MOVSPC,R14_svcwillreturntothecallingprogramandrestoretheCPSR.在进入软件中断陷阱时，PC被存入R14_svc，然后PC指向SWI指令后的字。MOVSNotethatthelinkmechanismisnotre-entrant,soifthesupervisorcodewishestousesoftwareinterruptswithinitselfitmustfirstsaveacopyofthereturnaddressandSPSR.COMMENTThebottom24bitsoftheinstructionareignoredbytheprocessor,andmaybeusedtocommunicateinformationtothesupervisorcode.Forinstance,thesupervisormaylookatthisfieldanduseittoindexintoanarrayofentrypointsforroutineswhichperformthevarioussupervisorfunctions.INSTRUCTIONCYCLESoftwareinterruptinstructionstake2S+1Nincrementalcyclestoexecute,whereSandNaredefinedassequential(S-cycle)andnon-sequential(N-cycle).周期ASSEMBLERSWI{cond} Twocharacterconditionmnemonic,Table3-<expression>Evaluatedandplacedinthecommentfield(whichisignoredby

;Getnextcharacterfromreadstream. ;Outputa"k"tothewritestream.SWINE0 ;Conditionallycallsupervisorwith0incommentfield.SWI{cond} 双字母条件助记符，见表3-<expression>估计和放入注释区(ARM920T不理睬 ; ;在写流程中输出SWINE ;有条件调用注释区0SupervisorThepreviousexamplesassumethatsuitablesupervisorcodeexists,for0x08B;SWIentry;AddressesofsupervisorDCDDCDDCD EQUEQUEQU ;SWIhasroutinerequiredinbits8-23anddata(ifany)in;bits0-7.AssumesR13_svcpointstoasuitableSTMFDR13,{R0-R2,R14};Saveworkregistersandreturnaddress. ;GetSWIinstruction.BICR0,R0,#0xFF000000 ;Cleartop8bits. ;Getroutineoffset. ;Getstartaddressofentrytable. ;Branchtoappropriateroutine. ;EnterwithcharacterinR0bits0-7.LDMFDR13,{R0- ;Restoreworkspaceand;restoringprocessormodeandCOPROCESSORDATAOPERATIONSTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-25.Thisclassofinstructionisusedtotellacoprocessortoperformsomeinternaloperation.NoresultiscommunicatedbacktoARM920T,anditwillnotwaitfortheoperationtocomplete.Thecoprocessorcouldcontainaqueueofsuchinstructionsawaitingexecution,andtheirexecutioncanoverlapotheractivity,allowingthecoprocessorandARM920Ttoperformindependenttasksin3-23-25COPROCESSORTheS3C2410X,unlikesomeotherARM-basedprocessors,doesnothaveanexternalcoprocessorinterface.Itdoesnothaveaon-chipcoprocessoralso.SothenallcoprocessorinstructionswillcausetheundefinedinstructiontraptobetakenontheS3C2410X.Thesecoprocessorinstructionscanbeemulatedbytheundefinedtraphandler.EventhoughexternalcoprocessorcannotbeconnectedtotheS3C2410X,thecoprocessorinstructionsarestilldescribedhereinfullforcompleteness.(Rememberthatanyexternalcoprocessordescribedinthissectionisasoftwareemulation.)3-25.Onlybit4andbits24to31ThecoprocessorfieldsaresignificanttoARM920T.Theremainingbitsareusedbycoprocessors.Theabovefieldnamesareusedbyconvention,andparticularcoprocessorsmayredefinetheuseofallfieldsexceptCP#asappropriate.TheCP#fieldisusedtocontainanidentifyingnumber(intherange0to15)foreachcoprocessor,andacoprocessorwillignoreanyinstructionwhichdoesnotcontainitsnumberintheCP#field.TheconventionalinterpretationoftheinstructionisthatthecoprocessorshouldperformanoperationspecifiedintheCPOpcfield(andpossiblyintheCPfield)onthecontentsofCRnandCRm,andplacetheresultinCRd.INSTRUCTIONCYCLECoprocessordataoperationstake1S+bIincrementalcyclestoexecute,wherebisthenumberofcyclesspentinthecoprocessorbusy-waitloop.SandIaredefinedassequential(S-cycle)andinternal(I-协处理器操作占用1S+bI周期，这里，bASSEMBLERCDP{cond} Twocharacterconditionmnemonic.SeeTable3-2. Theuniquenumberoftherequiredcoprocessor EvaluatedtoaconstantandplacedintheCPOpccd,cnandcmEvaluatetothevalidcoprocessorregisternumbersCRd,CRnandCRm WherepresentisevaluatedtoaconstantandplacedintheCPCDP{cond} 双字母条件助记符，见表3- cd,cnandcm分别表示有效协处理器寄存器号CRd、CRn和 ;Requestcoproc1todooperation;onCR2andCR3,andputtheresultinCDPEQp2,5,c1,c2,c3,2 ;IfZflagissetrequestcoproc2todooperation5(type2);onCR2andCR3,andputtheresultinCOPROCESSORDATATRANSFERS(LDC,协处理器数据转移（LDC、Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionencodingisshowninFigure3-26.Thisclassofinstructionisusedtoload(LDC)orstore(STC)asubsetofacoprocessors'sregistersdirectlytomemory.ARM920Tisresponsibleforsupplyingthememoryaddress,andthecoprocessorsuppliesoracceptsthedataandcontrolsthenumberofwordstransferred.3-23-263-26.THECOPROCESSORTheCP#fieldisusedtoidentifythecoprocessorwhichisrequiredtosupplyoracceptthedata,andacoprocessorwillonlyrespondifitsnumbermatchesthecontentsofthisfield.TheCRdfieldandtheNbitcontaininformationforthecoprocessorwhichmaybeinterpretedindifferentwaysbydifferentcoprocessors,butbyconventionCRdistheregistertobetransferred(orthefirstregisterwheremorethanoneistobetransferred),andtheNbitisusedtochooseoneoftwotransferlengthoptions.ForinstanceN=0couldselectthetransferofasingleregister,andN=1couldselectthetransferofalltheregistersforcontextswitching.ADDRESSINGARM920Tisresponsibleforprovidingtheaddressusedbythememorysystemforthetransfer,andtheaddressingmodesavailableareasubsetofthoseusedinsingledatatransferinstructions.Note,however,thattheimmediateoffsetsare8bitswideandspecifywordoffsetsforcoprocessordatatransfers,whereastheyare12bitswideandspecifybyteoffsetsforsingledatatransfers.The8bitunsignedimmediateoffsetisshiftedleft2bitsandeitheraddedto(U=1)orsubtractedfrom(U=0)thebaseregister(Rn);thiscalculationmaybeperformedeitherbefore(P=1)orafter(P=0)thebaseisusedasthetransferaddress.Themodifiedbasevaluemaybeoverwrittenbackintothebaseregister(ifW=1),ortheoldvalueofthebasemaybepreserved(W=0).Notethatpost-indexedaddressingmodesrequireexplicitsettingoftheWbit,unlikeLDRandSTRwhichalwayswrite-backwhenpost-indexed.Thevalueofthebaseregister,modifiedbytheoffsetinapre-indexedinstruction,isusedastheaddressforthetransferofthefirstword.Thesecondword(ifmorethanoneistransferred)willgotoorcomefromanaddressoneword(4bytes)higherthanthefirsttransfer,andtheaddresswillbeincrementedbyonewordforeachsubsequenttransfer.ADDRESSThebaseaddressshouldnormallybeawordalignedquantity.Thebottom2bitsoftheaddresswillappearonA[1:0]andmightbeinterpretedbythememorysystem.Useof使用IfRnisR15,thevalueusedwillbetheaddressoftheinstructionplus8bytes.Basewrite-backtoR15mustnotbespecified.DATAIftheaddressislegalbutthememorymanagergeneratesanabort,thedatatrapwillbetaken.Thewrite-backofthemodifiedbasewilltakeplace,butallotherprocessorstatewillbepreserved.Thecoprocessorispartlyresponsibleforensuringthatthedatatransfercanberestartedafterthecauseoftheaborthasbeenresolved,andmustensurethatanysubsequentactionsitundertakescanberepeatedwhentheinstructionisretried.INSTRUCTIONCYCLECoprocessordatatransferinstructionstake(n-1)S+2N+bIincrementalcyclestoexecute,where:nThenumberofwordstransferred.bThenumberofcyclesspentinthecoprocessorbusy-waitS,NandIaredefinedassequential(S-cycle),non-sequential(N-cycle),andinternal(I-cycle),协处理器数据转移指令占用(n-1)S+2N+bI周期，这里 ASSEMBLER<LDC|STC>{cond}{L} Loadfrommemoryto Storefromcoprocessorto Whenpresentperformlongtransfer(N=1),otherwiseperformshorttransfer Twocharacterconditionmnemonic.SeeTable3-2.. Theuniquenumberoftherequiredcoprocessor AnexpressionevaluatingtoavalidcoprocessorregisternumberthatisplacedintheCRdfield<Address>canAnexpressionwhichgeneratesanTheassemblerwillattempttogenerateaninstructionusingthePCasabaseandacorrectedimmediateoffsettoaddressthelocationgivenbyevaluatingtheexpression.ThiswillbeaPCrelative,pre-indexedaddress.Iftheaddressisoutofrange,anerrorwillbegeneratedApre-indexedaddressing offsetof[Rn,<#expression>]{!}offsetof<expression>Apost-indexedaddressing offsetof<expression> writebackthebaseregister(settheWbit)if!is isanexpressionevaluatingtoavalidARM920Tregisternumber.IfRnisR15,theassemblerwillsubtract8fromtheoffsetvaluetoallowforARM920T ;Loadc2ofcoproc1from;table,usingaPCrelativeaddress. ;Conditionallystorec3ofcoproc;intoanaddress24bytesupfrom;writethisaddressbacktoR5,and;longtransferoption(probablytostoremultipleAlthoughtheaddressoffsetisexpressedinbytes,theinstructionoffsetfieldisinwords.Theassemblerwilladjusttheoffsetappropriately.COPROCESSORREGISTERTRANSFERS(MRC,协处理器寄存器转移（MRC、Theinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedTable3-2..TheinstructionencodingisshowninFigure3-ThisclassofinstructionisusedtocommunicateinformationdirectlybetweenARM920Tandacoprocessor.AnexampleofacoprocessortoARM920Tregistertransfer(MRC)instructionwouldbeaFIXofafloatingpointvalueheldinacoprocessor,wherethefloatingpointnumberisconvertedintoa32bitintegerwithinthecoprocessor,andtheresultisthentransferredtoARM920Tregister.AFLOATofa32bitvalueinARM920TregisterintoafloatingpointvaluewithinthecoprocessorillustratestheuseofARM920Tregistertocoprocessortransfer(MCR).AnimportantuseofthisinstructionistocommunicatecontrolinformationdirectlyfromthecoprocessorintotheARM920TCPSRflags.Asanexample,theresultofacomparisonoftwofloatingpointvalueswithinacoprocessorcanbemovedtotheCPSRtocontrolthesubsequentflowofexecution.3-23-273-27.THECOPROCESSORTheCP#fieldisused,asforallcoprocessorinstructions,tospecifywhichcoprocessorisbeingcalledupon.TheCPOpc,CRn,CPandCRmfieldsareusedonlybythecoprocessor,andthepresentedhereisderivedfromconventiononly.Otherinterpretationsareallowedwherethecoprocessorfunctionalityisincompatiblewiththisone.TheconventionalinterpretationisthattheCPOpcandCPfieldsspecifytheoperationthecoprocessorisrequiredtoperform,CRnisthecoprocessorregisterwhichisthesourceordestinationofthetransferredinformation,andCRmisasecondcoprocessorregisterwhichmaybeinvolvedinsomewaywhichdependsontheparticularoperationspecified.对所有协处理器指令，CP#CPOpc、CRn、CPCRm区仅用于协处理器，并且这里的解释仅仅来源于惯例。TRANSFERSTOR15转移到WhenacoprocessorregistertransfertoARM920ThasR15asthedestination,bits31,30,29and28ofthetransferredwordarecopiedintotheN,Z,CandVflagsrespectively.Theotherbitsofthetransferredwordareignored,andthePCandotherCPSRbitsareunaffectedbythetransfer.TRANSFERSFROM从R15AcoprocessorregistertransferfromARM920TwithR15asthesourceregisterwillstorethe一个从ARM920T的带有R15作为源寄存器的协处理器寄存器转移将存储PC+12INSTRUCTIONCYCLEMRCinstructionstake1S+(b+1)I+1Cincrementalcyclestoexecute,whereS,IandCaredefinedassequential(S-cycle),internal(I-cycle),andcoprocessorregistertransfer(C-cycle),respectively.MCRinstructionstake1S+bI+1Cincrementalcyclestoexecute,wherebisthenumberofcyclesspentinthecoprocessorbusy-waitloop.MRC指令占用1S+(b+1)I+1C周期，LDRPC占用2S+2N+1I周期，这里，S、I和C分别定ASSEMBLER<MCR|MRC>{cond}p#,<expression1>,Rd,cn,cm{,<expression2>} MovefromcoprocessortoARM920Tregister(L=1) MovefromARM920Tregistertocoprocessor Twocharacterconditionmnemonic.SeeTable3-2 Theuniquenumberoftherequiredcoprocessor EvaluatedtoaconstantandplacedintheCPOpc AnexpressionevaluatingtoavalidARM920Tregistercnandcm ExpressionsevaluatingtothevalidcoprocessorregisternumbersCRnandCRmrespectively WherepresentisevaluatedtoaconstantandplacedintheCP ;Requestcoproc2toperformoperation;onc5andc6,andtransferthe;32-bitword)resultbackto ;Requestcoproc6toperformoperation;onR4andplacetheresultinc6.MRCEQ ;Conditionallyrequestcoproc3;performoperation9(type2)onc5;c6,andtransfertheresultbacktoUNDEFINEDTheinstructionisonlyexecutediftheconditionistrue.ThevariousconditionsaredefinedinTable3-2.TheinstructionformatisshowninFigure3-28.3-23-283-28.Iftheconditionistrue,theundefinedinstructiontrapwillbeNotethattheundefinedinstructionmechanisminvolvesofferingthisinstructiontoanycoprocessorswhichmaybepresent,andallcoprocessorsmustrefusetoacceptitbydrivingCPAandCPBHIGH.INSTRUCTIONCYCLEThisinstructiontakes2S+1I+1Ncycles,whereS,NandIaredefinedassequential(S-cycle),non-sequential(N-cycle),andinternal(I-cycle).ASSEMBLERTheassemblerhasnomnemonicsforgeneratingthisinstruction.Ifitisadoptedinthefutureforsomespecifieduse,suitablemnemonicswillbeaddedtotheassembler.Untilsuchtime,thisinstructionmustnotbeused.INSTRUCTIONSETThefollowingexamplesshowwaysinwhichthebasicARM920Tinstructionscancombinetogiveefficientcode.Noneofthesemethodssavesagreatdealofexecutiontime(althoughtheymaysavesome),mostlytheyjustsavecode.USINGTHECONDITIONALUsingConditionalsforLogical ;IfRn=pORRm=qTHENGOTOLabel. Thiscanbereplaced CMPNERm,#q ;Ifconditionnotsatisfiedtryothertest. Absolute;Test;and2'scomplementifMultiplicationby4,5or6(Run Rc,Ra,LSL#2;Multiplyby4, ;Testvalue,ADDCSRc,Rc,Ra ;Completemultiplyby5,ADDHIRc,Rc,Ra ;Completemultiplyby6.CombiningDiscreteandRange ;Discretetest,CMPNERc,#""-1 ;RangetestMOVLSRc,# ;IFRc<=""OR;THENRc:=DivisionandAnumberofdivideroutinesforspecificapplicationsareprovidedinsourceformaspartoftheANSIClibraryprovidedwiththeARMCrossDevelopmentToolkit,availablefromyoursupplier.Ashortgeneralpurposedivideroutinefollows.;EnterwithnumbersinRaand ;Bittocontrolthe ;MoveRbuntilgreaterthanCMPCCRb,RaMOVCCRb,Rb,ASL#1MOVCCRcnt,Rcnt,ASL#1 ;TestforpossibleSUBCS ;SubtractifADDCSRc,Rc,Rcnt ;Putrelevantbitintoresult ;ShiftcontrolbitMOVNE ;Halveunless ;DivideresultinRc,remainderinOverflowDetectionintheARM920TOverflowinunsignedmultiplywitha32-bitUMULL ;3to6 ;+1cycleandaregister Overflowinsignedmultiplywitha32-bitSMULL ;3to6 Rt,RdASR#31 ;+1cycleandaregister Overflowinunsigned