《EDA技术教程(第五版)》课后习题答案(第1-10章)

《EDA技术实用教程(第五版)》课后习 EDAASICFPGA开发有什么关系？FPGAASICASIC与软件描述语言相比，VHDL有什么特点?CPUCPUCPUVHDLVHDLVHDL(硬件描述语言)表达的l-3什么是综合?有哪些类型?么 什么是综合?用行为和功能层次表达的电子系统转换为低层次的便于具体实现的模块组合装配的过程。有哪些类型答：(1)VHDL(RegisterTransportLevel，RTL)，即从行为域到结构域的综合，即行为综合。(3RTL逻辑综合。(4)从逻辑门表示转换到版图表示(ASICFPGA综合在电子设计自动化中的地位是什么?答：是核心地位（见图1-3VHDLVHDLEDA技术中，自顶向下的设计方法的重要意义是什么IP在EDA技术的应用和发展中的意义是什么 答：IPEDAFPGA/CPLDEDA工具及其在整个流程中的作用。(P12~14)1.设计输入(原理图/HDLEDA设计输入器将电路系统以一定的表达方式输入计算机)；2.综合(EDA综合器就是将电路的高级语言(如行为描述)转换成低级的，可与FPGA／CPLD的基本结构相映射的网表文件或程序。)；3.适配(EDA适配器的功能是将JEDEC、JAM)；4.时序仿真(EDA对VHDL、原理图描述或其他描述形式的逻辑功能进行测试模拟，以器件的硬件特性。)；5.编程下载(EDA编程下载把适配后生成的下行硬件调试和验证(HardwareDebugging)。)；6.硬件测试(最后是将FPGACPLDEDAFPGAPC OLMC（输出逻辑宏单元）有何功能?GAL是怎样实现可编程组合电路与时序电路的。P34~36OLMC有何功能?答：OLMCGAL是怎样实现可编程组合电路与时序电路的?什么是基于乘积项的可编程逻辑结构?P33~34，40什么是基于查找表的可编程逻辑结构?P40~42什么是基于乘积项的可编程逻辑结构?答：GAL、CPLD之类都是FPGA系列器件中的LAB有何作用 答：FPGA（Cyclone/CycloneII）系列器件主要由逻辑阵列块LAB、嵌入式存储器块（EAB、I/OPLL元）构成的；FPGALAB。与传统的测试技术相比，边界扫描技术有何优点?答：使用BST（边界扫描测试）规范测试，不必使用物理探针，解释编程与配置这两个概念。一股使用此技术进行编程。CPLD被编程后改变了电可擦除存储单元配置：SRAM查找表的编程单元。编程信息是保存在PLDCPLD；将基于查PLD器件MAXIIPLD器件?为什么?P47~51PLDSRAM中。MAXIICPLD类型的PLDEEPROM中。 INOUTBUFFER有何异同点。P60INOUT:具有三态控制的双向传送端口BUFFER:ENTITYbuf3sIS --实体1:三态缓冲器PORT(input:INenable:IN

output:OUTSTD_LOGIC); ENDbuf3s;ENTITYmux21 2选1多路选择 INoutput:OUTIF_THENCASE语句的表达方式写出此电路的VHDL,s1和s0STD_LOGIC_VECTOR;s1=’0’,s0=’0’；s1=’0’,s0=’1’；s1=’1’,s0=’0’--1IF_THEN41LIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41IS (a,b,c,d:IN

INSTD_LOGIC;INSTD_LOGIC;OUTSTD_LOGIC);ENDENTITY OF SIGNALs0s1STD_LOGIC_VECTOR(1DOWNTO0);-- --s1s0,s1s0s0s1=s0s1=s0s1=ENDENDEND --2CASE41LIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41IS (a,b,c,d:IN

INSTD_LOGIC;INSTD_LOGIC;OUTSTD_LOGIC);ENDENTITY OF SIGNALs0s1STD_LOGIC_VECTOR(1DOWNTO0);-- --s1s0,s1s0CASEs0s1 --caseWHEN"00" y WHEN"01" y WHEN"10" y WHEN"11" y WHENOTHERS ENDENDEND 1VHDL8位全减器。要求suber(s_out=1,x<y),sub_in图3- 全减器结构--解(1.1)：实现1位半减器h_suber(diff=x-y；s_out=1,x<y)LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_suber INdiff,s_out:OUTSTD_LOGIC);ENDENTITY OFh_suberIS <=xXOR(NOTs_out<=(NOTx)ANDy;ENDARCHITECTUREhs1;--解(1.2)4-201 --1USEENTITYf_suber INSTD_LOGIC;sub_out,diff_out:OUTENDENTITY OFf_suberISCOMPONENTh_suberPORT(x,y:

--INdiff,s_out:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALa,b,c --1

sub_out<=cOREND (2)1位全减器为基本硬件,8位减法器,要求用例化语句来完成此项设计(x-y-sun_in=difft)。

8位减法器(上图所示)。LIBRARYUSEENTITYsuber_8 INSTD_LOGIC; INSTD_LOGIC; OUTSTD_LOGIC;diff4,diff5,diff6,diff7,sout:OUTSTD_LOGIC);ENDENTITYsuber_8;ARCHITECTUREs8OFsuber_8ISCOMPONENTf_suber

--INsub_out,diff_out:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALa0,a1,a2,a3,a4,a5,a6 --1 ENDARCHITECTUREs8;VHDL3-8(条件)语句、ifelse4种方式中，哪一种解（1）：--3-538译码器设计(条件赋值语句实现)LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYdecoder3to8 DIN:IN STD_LOGIC_VECTOR(2DOWNTO0);DOUT:OUTBIT_VECTOR(7DOWNTO0));ENDARCHITECTUREbehaveOFdecoder3to8ISWITHCONV_INTEGER(DIN)SELECTDOUT<="00000001"WHEN0,"00000010"WHEN"00000100"WHEN"00001000"WHEN"00010000"WHEN"00100000"WHEN"01000000"WHEN"10000000"WHEN7,UNAFFECTEDWHENOTHERS;END解（2）：case--3-538译码器设计(case语句实现)LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYdecoder3to8 DIN: STD_LOGIC_VECTOR(2DOWNTODOUT:OUTBIT_VECTOR(7DOWNTOENDARCHITECTUREbehaveOFdecoder3to8ISPROCESS(DIN)CASECONV_INTEGER(DIN)ISWHEN0=>DOUT<="00000001";WHEN1=>DOUT<="00000010";WHEN2=>DOUT<="00000100";WHEN3=>DOUT<="00001000";WHEN4=>DOUT<="00010000";WHEN5=>DOUT<="00100000";WHEN6=>DOUT<="01000000";WHEN7=>DOUT<="10000000";WHENOTHERS=>NULL;ENDENDEND解（3）：if_else--3-538译码器设计(if_else语句实现)LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYdecoder3to8 DIN:IN STD_LOGIC_VECTOR(2DOWNTO0);DOUT:OUTBIT_VECTOR(7DOWNTO0));ENDARCHITECTUREbehaveOFdecoder3to8ISPROCESS(DIN)IFCONV_INTEGER(DIN)=0THENDOUT<="00000001";ELSIFCONV_INTEGER(DIN)=1THENDOUT<="00000010";ELSIFCONV_INTEGER(DIN)=2THENDOUT<="00000100";ELSIFCONV_INTEGER(DIN)=3THENDOUT<="00001000";ELSIFCONV_INTEGER(DIN)=4THENDOUT<="00010000";ELSIFCONV_INTEGER(DIN)=5THENDOUT<="00100000";ELSIFCONV_INTEGER(DIN)=6THENDOUT<="01000000";ELSIFCONV_INTEGER(DIN)=7THENDOUT<="10000000";ENDIF;ENDEND解（4）：--3-538译码器设计(移位操作实现)LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYdecoder3to8 DIN:IN STD_LOGIC_VECTOR(2DOWNTO0);DOUT:OUTBIT_VECTOR(7DOWNTO0));ENDARCHITECTUREbehaveOFdecoder3to8ISDOUT<="00000001"SLLCONV_INTEGER(DIN);--被移位部END8421BCD51，否0。--解：3-68421BCD51，否则输出0。 USEUSEENTITYg_5_cmp d_in INSTD_LOGIC_VECTOR(3DOWNTO--cmp_out:OUTSTD_LOGIC); ENDARCHITECTUREBHVOFg_5_cmpISIF(d_in>"0101")cmp_out<='1'51。cmp_out<='0'50。ENDIF;ENDENDif--3-7if --1USEUSEENTITYf_adderPORT(ain,bin,cin: INSTD_LOGIC;cout,sum:OUTSTD_LOGIC);ENDENTITYf_adder;ARCHITECTUREfd1OFf_adderISPROCESS(ain,bin,cin)IFain='1'XORbin='1'XORcin='1'THENsum<='1';ELSEsum<='0';ENDIF;IF(ain='1'ANDbin='1')OR(ain='1'ANDcin='1')OR(bin='1'cin='1')OR(ain='1'ANDbin='1'ANDcin='1')THENcout<='1';ELSEENDENDENDARCHITECTURE8位二进制--解：3-88 USEUSEENTITYorg_patch org_data INSTD_LOGIC_VECTOR(70);--patch_data:OUTSTD_LOGIC_VECTOR(7DOWNTOENDARCHITECTUREBHVOForg_patchISIF(org_data(7)='0')patch_data<=org_dataorg_data>=0，补码=原码。 ENDENDEND--3-9LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYgrayTObinaryport(DIN:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTBIT_VECTOR(3DOWNTO0));ENDARCHITECTUREbehaveOFgrayTObinaryISPROCESS(DIN)CASEDINWHEN"0000"=>DOUT<="0000";WHEN"0001"=>DOUT<="0001";WHEN"0011"=>DOUT<="0010";WHEN"0010"=>DOUT<="0011";WHEN"0110"=>DOUT<="0100";WHEN"0111"=>DOUT<="0101";WHEN"0101"=>DOUT<="0110";WHEN"0100"=>DOUT<="0111";WHEN"1100"=>WHEN"1101"=>DOUT<="1001";WHEN"1111"=>DOUT<="1010";WHEN"1110"=>DOUT<="1011";WHEN"1010"=>DOUT<="1100";WHEN"1011"=>DOUT<="1101";WHEN"1001"=>DOUT<="1110";WHEN"1000"=>DOUT<="1111";WHENOTHERS=>NULL;ENDCASE;ENDENDif3A[2..0]、B[2..0]的比较器电路。对于比较(A<B)、(A>B)、(A=B)的结果分别给出输出信号--3-10if3A[2..0]、B[2..0]的比较对于比较(A<B)、(A>B)、(A=B)的结果分别给出输出信号LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOMPISPORT(A,B STD_LOGIC_VECTOR(2DOWNTO0)3LTOUTSTD_LOGIC;--小于输出GTOUTSTD_LOGIC;--大于输出EQ:OUTSTD_LOGIC);--等于输出ENDENTITYCOMP;ARCHITECTUREONEOFCOMPISIF(A<B)THENLT<='1';ELSELT<='0';ENDIF;IF(A>B)THENGT<='1';ELSEGT<='0';ENDIF;IF(A=B)THENEQ<='1';ELSEEQ<='0';ENDEND LT(A<B) GT(A>B) EQ<=(A=B);--等于ENDARCHITECTUREONE;8832位加法器。--3-11GENERIC88LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYADDER8BISGENERIC(S: --SPORT(A,B:IN STD_LOGIC_VECTOR(S-1DOWNTO0);CIN:IN SUM:OUTSTD_LOGIC_VECTOR(S-1COUT:OUTENDENTITYADDER8B;ARCHITECTUREONEOFADDER8BISVARIABLES1:STD_LOGIC_VECTOR(S-1DOWNTO0);VARIABLEC1:STD_LOGIC;--_VECTOR(S FORiIN1TOSIFA(i-1)='1'XORB(i-1)='1'XORC1='1'THENS1(i-1):='1';ELSES1(i-1):='0';ENDIF; C1='1')OR(B(i-1)='1'ANDC1='1')OR(A(i-1)='1'ANDB(i-1)='1'ANDTHENELSEENDENDLOOP;ENDENDARCHITECTURE2BCDBCD码加法器BCD码的补码获取方式与普通二进制数稍有不1。--3-122BCD码减法器(法)(a-b=a+[-b]补码LIBRARYIEEE;--待例化元件USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_arith.ALL;USEIEEE.STD_LOGIC_unsigned.ALL;ENTITYSUB2BCDISPORT(a,b:IN STD_LOGIC_VECTOR(7DOWNTO0);diff:outSTD_LOGIC_VECTOR(7DOWNTO0);sout:OUTSTD_LOGIC);ENDARCHITECTUREbehaveOFSUB2BCDISVARIABLEcc:STD_LOGIC_VECTOR(7DOWNTO0);IFa<bTHENsout<='1';ELSEsout<='0';ENDIF; cc:=cc+"00000110";ENDIF; cc:=cc+"01100000";ENDIF; cc:=cc+"00000110";ENDIF; cc:=cc+"01100000";ENDIF;IFa<bTHEN cc:=cc+"00000110";ENDIF; cc:=cc+"01100000";ENDIF;ENDENDEND4位乘法器，为此首先设计一个加法器，用例化语GENERIC16位乘法器。--3-134位移位相加型乘法器设计(例化调用加法器LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYMULT4BISGENERIC(S: --SPORT(R:OUTSTD_LOGIC_VECTOR(2*S-1DOWNTO0);A,B:INSTD_LOGIC_VECTOR(S-1DOWNTO0));ENDENTITYMULT4B;ARCHITECTUREONEOFMULT4BISCOMPONENTaddernPORT(a,b: result:outSTD_LOGIC_VECTOR);ENDCOMPONENT;SIGNALA0:STD_LOGIC_VECTOR(2*S-1DOWNTO0); STD_LOGIC_VECTOR(2*S-1DOWNTO0);A0<=CONV_STD_LOGIC_VECTOR(0,S)&A;

ENDu0:addernPORTMAP(a=>RR0,b=>RR1,result=>ZZ0);u1:addernPORTMAP(a=>ZZ0,b=>RR2,result=>ZZ1);u2:addernPORTMAP(a=>ZZ1,b=>RR3,result=>R);ENDARCHITECTURE--3-13a16位乘法器(3-13_MULTSBLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYMULT16BISPORT(D1,D2:IN STD_LOGIC_VECTOR(15DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(31DOWNTO0));ARCHITECTUREBHVOFMULT16BCOMPONENT --MULTS8GENERIC(S:integer); --MULTSB实体中关于参数“端PORT(R:OUTstd_logic_vector(2*S-1DOWNTO0);A,B:IN std_logic_vector(S-1DOWNTO0));ENDCOMPONENT; 7--解：3-14744输出 USEUSEENTITYvote_7PORT( INSTD_LOGIC_VECTOR(6DOWNTO0);--7位表决输入(1:同意，0:不同意G_4:OUT --CNTHOUTSTD_LOGIC_VECTOR(2DOWNTO0));--ENDARCHITECTUREBHVOFvote_7ISVARIABLEQ:STD_LOGIC_VECTOR(2DOWNTO0);FORnIN0TO6 nLOOPIF(DIN(n)='1')THENQ:=Q+1;ENDIF;ENDLOOP;IFQ>=4THENG_4<='1';ELSEG_4<='0';ENDIF;ENDPROCESS;END44--3-1544LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYMAXDATAISPORT(A:IN STD_LOGIC_VECTOR(3DOWNTO0);MAXOUT:OUTSTD_LOGIC);ENDENTITYMAXDATA;ARCHITECTUREONEOFMAXDATAIS MAXOUT<='0';ENDIF;ENDENDARCHITECTUREVHDL8位二进制数相加，然后将和左4AABB中。--3-16VHDL84ABLIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYADDER8BISGENERIC(S: --SPORT(A,B:IN STD_LOGIC_VECTOR(S-1DOWNTO0);CIN:IN SUM:OUTSTD_LOGIC_VECTOR(S-1COUT:OUTAA,BB:OUTSTD_LOGIC_VECTOR(S-1+4ENDENTITYADDER8B;ARCHITECTUREONEOFADDER8BISVARIABLES1:STD_LOGIC_VECTOR(S-1DOWNTO0);VARIABLEC1:STD_LOGIC;VARIABLEAB:STD_LOGIC_VECTOR(S-1+4FORiIN1TOSIFA(i-1)='1'XORB(i-1)='1'XORC1='1'THENS1(i-1):='1';ELSES1(i-1):='0';ENDIF; C1='1')OR(B(i-1)='1'ANDC1='1')OR(A(i-1)='1'ANDB(i-1)='1'ANDTHENELSEENDENDENDENDARCHITECTURE

举例说明GENERIC说明语句（在实体定义语句中定义类属C<=A+BAB和CCP89；第二种使用USEIEEE.SDT_LOGIC_UNSIGNED.ALL语句打开重载运算符程序包。VHDL中有哪三种数据对象?详细说明它们的功能特点以及使用方法举例说明数据对象与数据类型的关系信号变量常量P713-20能把任意一种进制的值向一整数类型的数据对象赋值吗?如果能，怎样做? 能（若A,B,C,D是信号整数类型，BITBOOLEAN对于逻辑操作应使用哪种类型关系操作的结果为哪种类型?IF语句测试的表达式是哪种类型?88A=[A7..A0]B=[B7..80]D、E、FA=BD=1；A>BE=1A<BF=1。第一种设计方案是常规的比较器设--3-22比较器的输入是两个待比较的8A=[A7..A0]和B=[B7..80]，输出是EQ、GT、FA=BEQ=1A>B时GT=1A<BLT=1。LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOMPISPORT(A,B STD_LOGIC_VECTOR(7DOWNTO0)3LTOUTSTD_LOGIC;--小于输出GTOUTSTD_LOGIC;--大于输出EQ:OUTSTD_LOGIC);--等于输出ENDENTITYCOMP;ARCHITECTUREONEOFCOMPISIF(A<B)THENLT<='1';ELSELT<='0';ENDIF;IF(A>B)THENGT<='1';ELSEGT<='0';ENDIF;IF(A=B)THENEQ<='1';ELSEEQ<='0';ENDENDENDARCHITECTURE--3-22比较器的输入是两个待比较的8A=[A7..A0]和B=[B7..80]，输出是EQ、GT、FA=BEQ=1A>B时GT=1A<BLT=1。LIBRARYUSEUSEENTITYCOMPPORT(A,B STD_LOGIC_VECTOR(7DOWNTO0)3LTOUTSTD_LOGIC;--小于输出GTOUTSTD_LOGIC;--大于输出EQ:OUTSTD_LOGIC);--等于输出ENDENTITYCOMP;ARCHITECTUREONEOFCOMPSIGNALC:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALD,E,F,G:INTEGERRANGE255DOWNTOIF(C(7)='1')THENLT<='1';ELSELT<='0';ENDIF;IF(C=0)THENEQ<='1';ELSEIF(C(7)='0')THENGT<='1';ELSEGT<='0';ENDENDENDENDARCHITECTURE3-1941多路选择器。2l1:层次例2:3进程。--1mux21a.vhdLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21aIS INy:OUTSTD_LOGIC);ENDENTITYmux21a;ARCHITECTUREoneOFmux21aISIFs='0'ENDENDENDARCHITECTURE--1mux41b.vhdLIBRARYUSEENTITYmux41b OUTY:OUT ENDARCHITECTUREbdf_typeOFmux41bIScomponentmux21a INy:OUTendsignalN0,N1:STD_LOGIC;u1:mux21aPORTMAP(a=>X0,b=>X1,s=>S0,y=>N0);u2:mux21aPORTu3:mux21aPORTMAP(a=>N0,b=>N1,s=>S1,y=>OUTY);--2mux41a.vhdLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41aIS INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYARCHITECTUREoneOFmux41asignalN0,N1:STD_LOGIC;com1:PROCESS(x1,x2,s0)IFs0='0'THENENDENDcom2:PROCESS(x3,x4,s0)IFs0='0'THENENDENDcom3:PROCESS(N0,N1,s1)IFs1='0'THENENDENDENDARCHITECTURE QuartusIIVHDL文本输入设计的流程：从文答：1建立工作库文件夹和编辑设计文件；2创建工程；3编译前设置；4全程编译；5时序仿真；6引脚锁定；7配置文件下载；8SignalTapII；9SignalTapII的待测信号；10SignalTapII；11SignalTapII件存盘；12SignalTapII测试信息的编译下载；13启动QuartusIIHelpAssignmentsTimingRequirements&Qptions的功能、使用方CompilationProcessAnalysis&SynthesisSetting的功能和使用方法，以及其SynthesisNetlistOptimization的功能和使用方法。TimingRequirements&Qptions的功能、他用方法和检测途经。SpecifyingTimingRequirementsandOptions(ClassicTimingAnalyzer)achievethedesiredspeedperformanceandothertimingcharacteristicsfortheentireproject,forspecificdesignentities,orforindividualclocks,nodes,andpins.Whenyouspecifyeitherproject-wideorindividualtimingrequirements,theFitteroptimizestheplacementoflogicinthedeviceinordertomeetyourtiminggoals.YoucanusetheTimingwizardortheTimingAnalysisSettingscommandtoeasilyspecifyallproject-widetimingrequirements,oryoucanusetheAssignmentEditortoassignindividualclockorI/Otimingrequirementstospecificentities,nodes,andpins,ortoallvalidnodesincludedinawildcardorassignmentgroupassignment.Tospecifyproject-widetimingOntheAssignmentsmenu,clickIntheCategorylist,selectTimingAnalysis Tospecifyproject-widetSU,tH,tCO,and/ortPDtimingrequirements,specifyvaluesunderDelayrequirements. Tospecifyproject-wideminimumdelayrequirements,specifyoptionsunderMinimumdelayrequirements.UnderClockSettings,selectDefaultrequired IntheDefaultrequiredfmaxbox,typethevalueoftherequiredfMAXandselectatimeunitfromthelist. Ifyouwanttospecifyoptionsforcuttingorreportingcertaintypesoftimingpathsglobally,enablingrecovery/removalanalysis,enablingclocklatency,andreportingunconstrainedtimingpaths,followtheseClickTospecifyclockOntheAssignmentsmenu,clickIntheCategorylist,selectTimingAnalysisUnderClockSettings,clickIndividualClickIntheNewClockSettingsdialogbox,typeanameforthenewclocksettingsintheClocksettingsnamebox.Toassigntheclocksettingstoaclocksignalinthedesign,typeaclocknodenameintheAppliestonodebox,orclickBrowse...toselectanodenameusingtheNodeFinder.Ifyouwanttospecifytimingrequirementsforanabsoluteclock,followthesesteps:Ifyouhavealreadyspecifiedtimingrequirementsforanabsoluteclock,andyouwanttospecifytimingrequirementsforaderivedclock,followthesesteps:IntheNewClockSettingsdialogbox,clickIntheIndividualClocksdialogbox,clickIntheSettingsdialogbox,clickOK.Tospecifyindividualtimingrequirements:OntheAssignmentsmenu,clickAssignmentIntheCategorybar,selectTimingtoindicatethecategoryofassignmentyouwishtomake.Typeanodenameand/orwildcardthatidentifiesthedestinationnode(s)youwanttoassign.Double-clicktheTocellandclickNodeFindertousetheNodeFindertoenteranodename.Double-clicktheTocell,clickthearrowthatappearsontherightsideofthecell,andclickSelectAssignmentGrouptoenteranexistingassignmentgroupname.Tospecifyanassignmentsource,repeatstep3tospecifythesourcenameintheFromcell.Inthespreadsheet,double-clicktheAssignmentNamecellandselectthetimingassignmentyouwishtomake.TospecifytiminganalysisreportingForassignmentsthatrequireavalue,TospecifytiminganalysisreportingOntheAssignmentsmenu,clickIntheCategorylist,double-clickTimingAnalysisClickTimingAnalyzerTospecifytherangeoftiminganalysisinformationreported,specifyoneormoreoptionsintheTimingAnalyzerReportingpage.ClickCompilationProcess的功能和使用方法。CompilationProcessSettingsPage(SettingsDialogBox)AllowsyoutodirecttheCompilertousesmartcompilation,savesynthesisresultsforthecurrentdesign'stop-levelentity,disabletheOpenCorePlushardwareevaluationfeature,orexportversion-compatibledatabasefiles.Youcanalsocontroltheamountofdiskspaceusedforcompilation.UseSmartcompilation:Preservefewernodenamestosavediskspace:RunAssemblerduringcompilation:Saveanode-levelnetlistoftheentiredesignintoapersistentsourcefile:Exportversion-compatibledatabase:Displayentitynamefornodename:DisableOpenCorePlushardwareevaluationfeature:Analysis&SynthesisSettingSynthesisNetlistOptimization的功能和使用方法。Analysis&SynthesisSettingsPage(SettingsDialogBox)Allowsyoutospecifyoptionsforlogicsynthesis.CreatedebuggingnodesforIPcores:MoreSettings:Otheroptions:MessageLevel:Advanced:SynthesisNetlistOptimizationsPage(SettingsDialogSpecifiesthefollowingoptionsforoptimizingnetlistsduringsynthesis:PerformWYSIWYGprimitiveresynthesis:Performgate-levelregisterAllowregisterretimingtotradeoffTsu/TcowithAssignmentsAssignmentEditorAbouttheAssignmentUserInterfaceandCustomizingtheUserPinLogicLockAssignmentValidationandIntegrationwiththePin有哪三种引脚锁定的方法?注意事项，并说明它们各自的特点。提示，第三种方法是选择AssignmentsPins对话框，进行引脚设置。JTAGFPGAFlashEPCS器件的间接33-133-14--3-134位移位相加型乘法器设计(例化调用加法器)LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYMULT4BISGENERIC(S:INTEGER:=4); --S4PORT(R:OUTSTD_LOGIC_VECTOR(2*S-1DOWNTO0);A,B:INSTD_LOGIC_VECTOR(S-1DOWNTO0));ENDENTITYMULT4B;ARCHITECTUREONEOFMULT4BCOMPONENTaddernPORT(a,b: result:outSTD_LOGIC_VECTOR);ENDCOMPONENT;SIGNALA0:STD_LOGIC_VECTOR(2*S-1DOWNTOSIGNALRR3,RR2,RR1,RR0,ZZ1,ZZ0:STD_LOGIC_VECTOR(2*S-1DOWNTO0);A0<=CONV_STD_LOGIC_VECTOR(0,S)&A; RR0<=(OTHERS=>'0');ENDIF;IF(B(1)='1')THENRR1<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0)SLL1);ELSERR1<=(OTHERS=>'0');ENDIF;IF(B(2)='1')THENRR2<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0)SLL2);ELSERR2<=(OTHERS=>'0');ENDIF;IF(B(3)='1')THENRR3<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0)SLL3);ELSERR3<=(OTHERS=>'0');ENDIF;ENDu0:addernPORTMAP(a=>RR0,b=>RR1,result=>ZZ0);u1:addernPORTMAP(a=>ZZ0,b=>RR2,result=>ZZ1);u2:addernPORTMAP(a=>ZZ1,b=>RR3,result=>R);ENDARCHITECTURE--解：3-14744 USEUSEENTITYvote_7PORT( INSTD_LOGIC_VECTOR(6DOWNTO0);--7位表决输入(1:同意，0:不同意G_4:OUTSTD_LOGIC; CNTHOUTSTD_LOGIC_VECTOR(2DOWNTO0));--表决结果统计数ENDARCHITECTUREBHVOFvote_7ISVARIABLEQ:STD_LOGIC_VECTOR(2DOWNTO0);FORnIN0TO6 nLOOPIF(DIN(n)='1')THENQ:=Q+1;ENDIF;ENDLOOP;IFQ>=4THENG_4<='1';ELSEG_4<='0';ENDIF;ENDPROCESS;ENDcoutsumDlK22QuartusII给出编译报错：“Can'tplacemultiplepinsassignedtopinLocationPinD1(K22)”，试问，问题出在哪里?如何解决?P994-5nCEO原来的“Useasprogrammingpin”改为“UseasregularI/O”I/O74148（8-3线八进位优先编码器）8421BCD74148（8-3线八进位优先编码器8421BCD374139（2线-4线译码器）5-2474283（4位二进制全加器）号，CO1AS解：用74283（4位二进制全加器）8421BCD解：用74283（4位二进制全加器）8421BCD码加法器电路（化简7人表决电路（4位二进制全7keepkeep属性应用的好处。在本章示例中，或自主选择一个示例，使用SignalProbeEP3C55上进行硬件测试，并说明这一功能的特点及优势。P113~1144-143-233-24--1：4-143-23】0～2558位二进LIBRARY --USEUSEWORK.n_pack.ALL;ENTITYaxampISPORT(datIN --ouOUT --ARCHITECTUREbhvOFaxampIS3-23】打开使用)LIBRARYIEEE;USEPACKAGEn_packSUBTYPEnatISIntegerrange0to255;--IntegerTYPEBit8ISarray(7downto0)OFstd_logic;--FUNCTIONnat_to_Bit8(s:nat)RETURNBit8;ENDn_pack;PACKAGEBODYn_packFUNCTIONnat_to_Bit8(s:nat)RETURNBit8ISVARIABLEDin:Integerrange255downto0;VARIABLERut:Bit8;VARIABLERig:Integer:=2**7;FORIin7downto0IFDin/Rig>0THENRut(i):='1';Din:=Din-Rig;ELSERut(i):='0'; ENDIF;ENDRETURNENDEND

VHDL0(复位)有两种不同方法，它--1：5-15-4DLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1IS Q:OUTARCHITECTUREbhvOFDFF1SIGNALQ1:STD_LOGIC; PROCESS(CLK,Q1,RST,EN)IFRST='1'THENELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THENENDENDENDEND

2：5-1【5-5DLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1ISPORT(CLK,RST,D: Q:OUTARCHITECTUREbhvOFDFF1SIGNALQ1:STD_LOGIC; IFCLK'EVENTANDCLK='1'IFRST='1'THENQ1<='0';ELSEQ1<=D;ENDIF;ENDIF;ENDEND

--举例（5-1）说明，为什么使用条件叙述不完整的条件句而导致时序电路综合结果。--解：5-25-1】DLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1ISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTSTD_LOGIC);ARCHITECTUREbhvOFDFF1SIGNALQ1:STD_LOGIC; IFCLK'EVENTANDCLK='1THENQ1<=D;ENDIF;ENDEND

--10D--5-310DLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF1IS Q:OUTARCHITECTUREbhvOFDFF1SIGNALQ1:STD_LOGIC; PROCESS(CLK,Q1,RST,SET)IFRST='1'THENELSIFCLK'EVENTANDCLK='1'THENIFSET='1'THENQ1<='1';ELSEENDENDENDEND

--5-15(异步复位和同步加载十进制加法计数器)改写成一异08位二进制加法计数器。--5-408LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,RST,EN,LOAD:INDATA STD_LOGIC_VECTOR(3DOWNTO0)4DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0);--计数值COUTOUT --ENDARCHITECTUREbehavOFCNT10ISVARIABLEQ:STD_LOGIC_VECTOR(3DOWNTO0);IFRST='0THENQ:=(OTHERS ELSIFLOAD='0THEN --ELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THEN

加载（同步使能IFQ<9THENQ:=Q+1;--允许计数,9ELSEQ:=(OTHERS=>'0')9时，计数值清零ENDIF;ENDENDIFQ=9THENCOUT<='1'9ELSEEND --ENDEND5-4COUT与异步加LOAD16(4)位二进制数计数器，即一个l6(4)位可控的分频器，并说明工作原理。设输入频率fi=4MHzf0=(516.5±1)Hz(允许误差±0.1Hz)16位加--5-55-4COUTLOAD连在--16(4)l6(4)--fi=4MHzf0=(516.5±1)Hz(允许误差±0.1Hz)16位加载数LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,RST,EN:INDATA STD_LOGIC_VECTOR(3DOWNTO0)4DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0);--计数值COUTBUFFER --ENDARCHITECTUREbehavOFCNT10IS IFRST='0THENQ:=(OTHERS ELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THEN

加载（同步使能IFCOUT='1THEN --IFQ<9THENQ:=Q+1;--允许计数,9ELSEQ:=(OTHERS=>'0')9时，计数值清零ENDIF;ENDENDENDIFQ=9THENCOUT<='1'9，输出进位信号ELSECOUT<='0';END ENDPROCESS;ENDRTL图(5-195-19)VHDL描述，注意其中D触发器和锁存器的表述。5-18RTL--15-18RTLVHDLmux21a.vhd 用WHEN_ELSE实现2选1多路选择器程序(mux21a.vhd) USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21aISPORT(a,b: INSTD_LOGIC;s: INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21a;ARCHITECTUREoneOFmux21aIS WHENs='0'ELSEb;ENDARCHITECTUREone;--25-18RTLVHDLDFF6.vhd D型触发器程序(DFF6.vhd)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF6ISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTSTD_LOGIC);ARCHITECTUREbhvOFDFF6ISIFCLK='1'THENQ<=D;ENDENDEND5-65-18RTLVHDL--35-18RTLVHDLT5_18.vhd USEIEEE.STD_LOGIC_1164.ALL;ENTITYT5_18ISPORT(D1,D2,CLK INQ:OUTSTD_LOGIC);ENDENTITY ARCHITECTUREoneOFT5_18ISCOMPONENT --21PORT(a,b: INSTD_LOGIC;s: INSTD_LOGIC;y:OUTSTD_LOGIC);ENDCOMPONENT --DPORT(CLK:IND:INSTD_LOGIC;Q:OUTSTD_LOGIC);ENDSIGNALDD: --1 mux21aPORTMAP(CLK,D2,D1,DD); PORTMAP(CLK,DD,Q);ENDARCHITECTURE5-19RTL--15-19RTLVHDLmux21a.vhd 用WHEN_ELSE实现2选1多路选择器程序(mux21a.vhd) USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21aISPORT(a,b: INSTD_LOGIC;s: INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21a;ARCHITECTUREoneOFmux21aIS WHENs='0'ELSEb;ENDARCHITECTUREone;--25-19RTLVHDLDFF_PRE_CLR.vhd顶层 DLIBRARYUSEIEEE.STD_LOGIC_1164.ALL;ENTITYDFF_PRE_CLR_ENAISPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTENA:INSTD_LOGIC;PRE:INSTD_LOGIC;CLR:INARCHITECTUREbhvOFDFF_PRE_CLR_ENASIGNALQ1:STD_LOGIC; IFCLR='1'THENQ1<='0';ELSIFPRE='1'THENQ1<='1';ELSIFCLK'EVENTANDCLK='1'ANDENA='1'END--IFEN='1THEN --END --ENDEND5-65-19RTLVHDL--35-19RTLVHDLT5_19.vhd USEIEEE.STD_LOGIC_1164.ALL;ENTITYT5_19ISPORT(RST,D,CLK: INSTD_LOGIC;Q,DOUT:OUTSTD_LOGIC);END ARCHITECTUREoneOFT5_19COMPONENT --DPORT(CLK:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTENA:INSTD_LOGIC;PRE:INSTD_LOGIC;CLR:INENDCOMPONENT --DPORT(a,b: INSTD_LOGIC;s: INSTD_LOGIC;y:OUTSTD_LOGIC);ENDSIGNALDD,DDD:STD_LOGIC; --1个信号作为内部的 mux21aPORTMAP(D,'0',RST,DD);DDD<=DXORDD; DFF_PRE_CLR_ENAPORTMAP(CLK,DDD,DOUT,'1','0','0'); DFF_PRE_CLR_ENAPORTMAP(CLK,DD,Q,'1','0','0');ENDARCHITECTUREVHDL74LS160(异步复位和同步使能加--5- VHDL74LS160(载、计数的十进制加法计数器)LIBRARYUSEUSEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT10ISPORT(CLK,RST,EN,LOAD:INDATA STD_LOGIC_VECTOR(3DOWNTO0)4DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0);--计数值COUTOUT --ENDARCHITECTUREbehavOFCNT10ISVARIABLEQ:STD_LOGIC_VECTOR(3DOWNTO0);IFRST='0THENQ:=(OTHERS ELSIFCLK'EVENTANDCLK='1'THENIFEN='1'THEN

加载（同步使能IFLOAD='0'THENQ:=DATA;

--IFQ<9THENQ:=Q+1允许计数,ELSEQ:=(OTHERS=>'0')9ENDENDENDENDIFQ=9THENCOUT<='1'9ELSEEND --ENDEND016位二进制加减可控计数器VHDL描述。--解：5-816位二进制加减可控计数器(带预置数)VHDL VHDL16LIBRARYUSEUSEENTITYADD_SUB_LOAD_16 IN

COUT:OUTSTD_LOGIC);ENDENTITYARCHITECTUREA_S_16OFADD_SUB_LOAD_16ISVARIABLECQI:STD_LOGIC_VECTOR(15DOWNTO--VARIABLELS_LOAD:IFRST='1'THENCQI:=(OTHERS=>'0');--计数器异步复位ELSIFLOAD='1'THEN --ELSIFCLK'EVENTANDCLK='1 --IF --检测是否允许计数(同步他能IFCQI<16#FFFF# --允许计数ELSECQI:=(OTHERS=> --65535,计数值ENDIFCQI=16#FFFF#THEN --ELSECOUT<='0';ENDIF;ENDIF --检测是否允许计数(同步他能IFCQI>0 --允许计数,ELSECQI:=(OTHERS=> --65535,计数值ENDIFCQI=0THEN ELSECOUT<='0';ENDIF;ENDENDENDPROCESS;

--ENDARCHITECTURE基于原理图输入方式，用 触发器构成按循环(000->001->011->111->101->100->000)4位全加器(74283)74374(8D触发器)474299（8位通用移位寄存器、74373（8D锁存器、D触发器和非门来完成上述功能，应该(1)(2)74163（4位二进制计数器74138（3线-8线译码器12路脉冲112路输出的位置。若改用一片74195（4位通用移位寄存器）代替以上的74163（4位二进制计数器位的时刻输出1。(同步复位) --1(同步复位)：5-125位 511。LIBRARYIEEE;USEUSEENTITY PORT

P_out:OUT 0);--P_out:o_e_outOUT ENDENTITYodd_even_p_RXD_5;ARCHITECTUREoneOFodd_even_p_RXD_5IS shift_QSTD_LOGIC_VECTOR(4DOWNTO0);--shift_Q:VARIABLEshift_cntSTD_LOGIC_VECTOR(2DOWNTO0);--shift_cnt:IFCLK'EVENTANDCLK='1 --IFRST='1'THENshift_cnt:="100"; IFshift_cnt=4THEN --检测到接收5位串行输入数据 o_e_out<=shift_Q(4)XORshift_Q(3)XORshift_Q(2)XORshift_Q(1)shift_Q(0);--shift_Q:=S_in&shift_Q(4DOWNTO1);--采样移位串行输入shift_cnt:=shift_cnt+1;--shift_Q:=S_in&shift_Q(4DOWNTO1);--采样移位串行输入ENDIF;ENDENDENDENDARCHITECTURE--2(异步复位)：5-125位 511LIBRARYUSEUSEENTITY

PORT P_outOUT

o_e_out:OUT ENDENTITYodd_even_p_RXD_5;ARCHITECTUREoneOFodd_even_p_RXD_5IS shift_QSTD_LOGIC_VECTOR(4DOWNTO0);--shift_Q:VARIABLEshift_cntSTD_LOGIC_VECTOR(2DOWNTO0);--shift_cnt:IFRST='1'THENshift_cnt:="011"; IFCLK'EVENTANDCLK='1 --IFshift_cnt=4THEN --检测到接收5位串行输入数据 o_e_out<=shift_Q(4)XORshift_Q(3)XORshift_Q(2)XORshift_Q(1)shift_Q(0);--shift_Q:=S_in&shift_Q(4DOWNTO1);--采样移位串行输入shift_cnt:=shift_cnt+1;--shift_Q:=S_in&shift_Q(4DOWNTO1);--采样移位串行输入ENDIF;ENDENDENDENDARCHITECTURE7490（十进制计数器）842174194、74273、D触发器等器件组位一组数据全部转换结束后，输出才变化一次。(QII下波形仿真) QuartusIIVHDLSignalTapIIP146~P152SignalTapII整的程序和对它的实测结果。P151~P152ARCHITECTUREONEOFxxxattributechip_pinofCLK0：signalis”G21”;6.6.2QuartusIISynplify通过实测证实在编译中QuartusII调用了Synplify综合器。 7-1.MegaWizardPlug-InManagerLPMlpm_counter块的程序，其中参数自定。（7-1）P171--7-1如果不使用MegawizardPlug_InManagerLPM lpm_counter--答：1.在程序开始部分增加打开"lpm"库和使用"lpm"--答：2.在结构说明描述部分增加调用"lpm"传递参数和端口的申--答：3.在结构行为描述部分增加调用"lpm"传递参数和端口的例--答：4.lpm_counter（LPM）VHDLLIBRARYieee;USEieee.std_logic_1164.all;LIBRARYlpm;USEENTITYSINGT_counterPORT(clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTOENDARCHITECTURESYNOFsingt_counterSIGNAL :STD_LOGIC_VECTOR(7DOWNTOCOMPONENTGENERIC(lpm_direction:STRING;

lpm_type: :PORT(clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTOENDq<=sub_wire0(7DOWNTO0);lpm_counter_component:lpm_counterGENERICMAP(lpm_direction=>"UP",lpm_port_updown lpm_type=>"LPM_COUNTER",lpm_width=>8)PORTMAP(clock=>clock,q=>sub_wire0);END0QuartusII1：7-7RAM(810LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_ARITH.ALL;--此程序包括含转换函数USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYRAM10x8PORT(CLK:INSTD_LOGIC;WREN:INSTD_LOGIC;A:INSTD_LOGIC_VECTOR(9DOWNTO0);RAM10DIN:INSTD_LOGIC_VECTOR(7DOWNTO0);RAMQ:OUTSTD_LOGIC_VECTOR(7DOWNTO0));8ARCHITECTUREbhvOFRAM10x8TYPEG_ARRAYISARRAY(0TO1024)OFSTD_LOGIC_VECTOR(7DOWNTO0);SIGNALMEM:G_ARRAY;MEMG_ARRAYattributeram_init_file:string;--定义字符串属性的标识ram_init_file。attributeram_init_fileofMEM:ram_init_fileMEMSIGNALIS"../SIND10X8.mif";--并将字符串"data7x8.mif"初始ram_init_file。IFRISING_EDGE(CLK)IFWREN='1'THEN MEM(CONV_INTEGER(A))<=DIN;--RAMENDENDIF(FALLING_EDGE(CLK))THENENDENDEND2：7-18将参数传入底层模块例7-6。顶层文件的参数设数据宽度=16，存储msize=1024。LIBRARYIEEE;USEUSEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--此程序包包含算符重载函数ENTITY