嵌入式系统原理与应用 第3版 S3C2410寄存器地址C定义

/*

*vivi/include/s3c2400.h

*

*DefinitionofconstantsrelatedtotheS3C2410microprocessor(basedonARM290T).

*ThisfileisbasedontheS3C2400UserManual2002,01,23.

*

*Copyright(C)2002MIZIResearch,Inc.

*

*Author:JanghoonLyu<nandy@>

*Date:$Date:2002/10/1102:27:29$

*

*$Revision:1.8$

*/

/*

*History

*

*2002-05-14:JanghoonLyu<nandy@>

*-Initialcode

*/

#include"hardware.h"

#include"bitfield.h"

#defineUSR26_MODE 0x00

#defineFIQ26_MODE 0x01

#defineIRQ26_MODE 0x02

#defineSVC26_MODE 0x03

#defineUSR_MODE 0x10

#defineFIQ_MODE 0x11

#defineIRQ_MODE 0x12

#defineSVC_MODE 0x13

#defineABT_MODE 0x17

#defineUND_MODE 0x1b

#defineSYSTEM_MODE 0x1f

#defineMODE_MASK 0x1f

#defineF_BIT 0x40

#defineI_BIT 0x80

#defineCC_V_BIT (1<<28)

#defineCC_C_BIT (1<<29)

#defineCC_Z_BIT (1<<30)

#defineCC_N_BIT (1<<31)

/*MemoryController*/

#defineMEM_CTL_BASE 0x48000000

#definebMEMCTL(Nb) __REGl(MEM_CTL_BASE+(Nb))

/*Offset*/

#defineoBWSCON 0x00 /*R/W,Buswidthandwaitstatusctrlreg.*/

#defineoBANKCON0 0x04 /*R/W,Bank0controlreg.*/

#defineoBANKCON1 0x08 /*R/W,Bank1controlreg.*/

#defineoBANKCON2 0x0C /*R/W,Bank2controlreg.*/

#defineoBANKCON3 0x10 /*R/W,Bank3controlreg.*/

#defineoBANKCON4 0x14 /*R/W,Bank4controlreg.*/

#defineoBANKCON5 0x18 /*R/W,Bank5controlreg.*/

#defineoBANKCON6 0x1C /*R/W,Bank6controlreg.*/

#defineoBANKCON7 0x20 /*R/W,Bank7controlreg.*/

#defineoREFRESH 0x24 /*R/W,SDRAMrefreshcontrolregister*/

#defineoBANKSIZE 0x28 /*R/W,Flexiblebanksizeregister*/

#defineoMRSRB6 0x2C /*R/W,Moderegistersetregisterbank6*/

#defineoMRSRB7 0x2C /*R/W,Moderegistersetregisterbank7*/

/*Registers*/

#defineBWSCON bMEMCTL(oBWSCON)

#defineBANKCON0 bMEMCTL(oBANKCON0)

#defineBANKCON1 bMEMCTL(oBANKCON1)

#defineBANKCON2 bMEMCTL(oBANKCON2)

#defineBANKCON3 bMEMCTL(oBANKCON3)

#defineBANKCON4 bMEMCTL(oBANKCON4)

#defineBANKCON5 bMEMCTL(oBANKCON5)

#defineBANKCON6 bMEMCTL(oBANKCON6)

#defineBANKCON7 bMEMCTL(oBANKCON7)

#defineREFRESH bMEMCTL(oREFRESH)

#defineBANKSIZE bMEMCTL(oBANKSIZE)

#defineMRSRB6 bMEMCTL(oMRSRB6)

#defineMRSRB7 bMEMCTL(oMRSRB7)

/*Bits*/

#defineSELF_REFRESH (1<<22)

/*ClockandPowerManagement*/

#defineCLK_CTL_BASE 0x4C000000

#definebCLKCTL(Nb) __REGl(CLK_CTL_BASE+(Nb))

/*Offset*/

#defineoLOCKTIME 0x00 /*R/W,PLLlocktimecountregister*/

#defineoMPLLCON 0x04 /*R/W,MPLLconfigurationregister*/

#defineoUPLLCON 0x08 /*R/W,UPLLconfigurationregister*/

#defineoCLKCON 0x0C /*R/W,Clockgeneratorcontrolreg.*/

#defineoCLKSLOW 0x10 /*R/W,Slowclockcontrolregister*/

#defineoCLKDIVN 0x14 /*R/W,Clockdividercontrol*/

/*Registers*/

#defineLOCKTIME bCLKCTL(oLOCKTIME)

#defineMPLLCON bCLKCTL(oMPLLCON)

#defineUPLLCON bCLKCTL(oUPLLCON)

#defineCLKCON bCLKCTL(oCLKCON)

#defineCLKSLOW bCLKCTL(oCLKSLOW)

#defineCLKDIVN bCLKCTL(oCLKDIVN)

/*Fields*/

#definefMPLL_MDIV Fld(8,12)

#definefMPLL_PDIV Fld(6,4)

#definefMPLL_SDIV Fld(2,0)

/*macros*/

#defineGET_MDIV(x) FExtr(x,fMPLL_MDIV)

#defineGET_PDIV(x) FExtr(x,fMPLL_PDIV)

#defineGET_SDIV(x) FExtr(x,fMPLL_SDIV)

/*GPIO*/

#defineGPIO_CTL_BASE 0x56000000

#definebGPIO(p,o) __REGl(GPIO_CTL_BASE+(p)+(o))

/*Offset*/

#defineoGPIO_CON 0x0 /*R/W,Configuresthepinsoftheport*/

#defineoGPIO_DAT 0x4 /*R/W, Dataregisterforport*/

#defineoGPIO_UP 0x8 /*R/W,Pull-updisableregister*/

#defineoGPIO_RESERVED 0xC /*R/W,Reserved*/

#defineoGPIO_A 0x00

#defineoGPIO_B 0x10

#defineoGPIO_C 0x20

#defineoGPIO_D 0x30

#defineoGPIO_E 0x40

#defineoGPIO_F 0x50

#defineoGPIO_G 0x60

#defineoGPIO_H 0x70

#defineoMISCCR 0x80 /*R/W,Miscellaneouscontrolregister*/

#defineoDCLKCON 0x84 /*R/W,DCLK0/1controlregister*/

#defineoEXTINT0 0x88 /*R/W,Externalinterruptcontrolreg.0*/

#defineoEXTINT1 0x8C /*R/W,Externalinterruptcontrolreg.1*/

#defineoEXTINT2 0x90 /*R/W,Externalinterruptcontrolreg.2*/

#defineoEINTFLT0 0x94 /*R/W,Reserved*/

#defineoEINTFLT1 0x98 /*R/W,Reserved*/

#defineoEINTFLT2 0x9C /*R/W,Externalinterruptcontrolreg.2*/

#defineoEINTFLT3 0xA0 /*R/W,Externalinterruptcontrolreg.3*/

#defineoEINTMASK 0xA4 /*R/W,Externalinterruptmaskregister*/

#defineoEINTPEND 0xA8 /*R/W,Externalinterruptpendingreg.*/

/*Registers*/

#defineGPACON bGPIO(oGPIO_A,oGPIO_CON)

#defineGPADAT bGPIO(oGPIO_A,oGPIO_DAT)

#defineGPBCON bGPIO(oGPIO_B,oGPIO_CON)

#defineGPBDAT bGPIO(oGPIO_B,oGPIO_DAT)

#defineGPBUP bGPIO(oGPIO_B,oGPIO_UP)

#defineGPCCON bGPIO(oGPIO_C,oGPIO_CON)

#defineGPCDAT bGPIO(oGPIO_C,oGPIO_DAT)

#defineGPCUP bGPIO(oGPIO_C,oGPIO_UP)

#defineGPDCON bGPIO(oGPIO_D,oGPIO_CON)

#defineGPDDAT bGPIO(oGPIO_D,oGPIO_DAT)

#defineGPDUP bGPIO(oGPIO_D,oGPIO_UP)

#defineGPECON bGPIO(oGPIO_E,oGPIO_CON)

#defineGPEDAT bGPIO(oGPIO_E,oGPIO_DAT)

#defineGPEUP bGPIO(oGPIO_E,oGPIO_UP)

#defineGPFCON bGPIO(oGPIO_F,oGPIO_CON)

#defineGPFDAT bGPIO(oGPIO_F,oGPIO_DAT)

#defineGPFUP bGPIO(oGPIO_F,oGPIO_UP)

#defineGPGCON bGPIO(oGPIO_G,oGPIO_CON)

#defineGPGDAT bGPIO(oGPIO_G,oGPIO_DAT)

#defineGPGUP bGPIO(oGPIO_G,oGPIO_UP)

#defineGPHCON bGPIO(oGPIO_H,oGPIO_CON)

#defineGPHDAT bGPIO(oGPIO_H,oGPIO_DAT)

#defineGPHUP bGPIO(oGPIO_H,oGPIO_UP)

#defineMISCCR bGPIO(oMISCCR,0)

#defineDCLKCON bGPIO(oDCLKCON,0)

#defineEXTINT0 bGPIO(oEXTINT0,0)

#defineEXTINT1 bGPIO(oEXTINT1,0)

#defineEXTINT2 bGPIO(oEXTINT2,0)

#defineEINTFLT0 bGPIO(oEINTFLT0,0)

#defineEINTFLT1 bGPIO(oEINTFLT1,0)

#defineEINTFLT2 bGPIO(oEINTFLT2,0)

#defineEINTFLT3 bGPIO(oEINTFLT3,0)

#defineEINTMASK bGPIO(oEINTMASK,0)

#defineEINTPEND bGPIO(oEINTPEND,0)

/*UART*/

#defineUART_CTL_BASE 0x50000000

#defineUART0_CTL_BASE UART_CTL_BASE

#defineUART1_CTL_BASE UART_CTL_BASE+0x4000

#defineUART2_CTL_BASE UART_CTL_BASE+0x8000

#definebUART(x,Nb) __REGl(UART_CTL_BASE+(x)*0x4000+(Nb))

#definebUARTb(x,Nb) __REGb(UART_CTL_BASE+(x)*0x4000+(Nb))

/*Offset*/

#defineoULCON 0x00 /*R/W,UARTlinecontrolregister*/

#defineoUCON 0x04 /*R/W,UARTcontrolregister*/

#defineoUFCON 0x08 /*R/W,UARTFIFOcontrolregister*/

#defineoUMCON 0x0C /*R/W,UARTmodemcontrolregister*/

#defineoUTRSTAT 0x10 /*R,UARTTx/Rxstatusregister*/

#defineoUERSTAT 0x14 /*R,UARTRxerrorstatusregister*/

#defineoUFSTAT 0x18 /*R,UARTFIFOstatusregister*/

#defineoUMSTAT 0x1C /*R,UARTModemstatusregister*/

#defineoUTXHL 0x20 /*W,UARTtransmit(little-end)buffer*/

#defineoUTXHB 0x23 /*W,UARTtransmit(big-end)buffer*/

#defineoURXHL 0x24 /*R,UARTreceive(little-end)buffer*/

#defineoURXHB 0x27 /*R,UARTreceive(big-end)buffer*/

#defineoUBRDIV 0x28 /*R/W,Baudratedivisorregister*/

/*Registers*/

#defineULCON0 bUART(0,oULCON)

#defineUCON0 bUART(0,oUCON)

#defineUFCON0 bUART(0,oUFCON)

#defineUMCON0 bUART(0,oUMCON)

#defineUTRSTAT0 bUART(0,oUTRSTAT)

#defineUERSTAT0 bUART(0,oUERSTAT)

#defineUFSTAT0 bUART(0,oUFSTAT)

#defineUMSTAT0 bUART(0,oUMSTAT)

#defineUTXH0 bUARTb(0,oUTXHL)

#defineURXH0 bUARTb(0,oURXHL)

#defineUBRDIV0 bUART(0,oUBRDIV)

#defineULCON1 bUART(1,oULCON)

#defineUCON1 bUART(1,oUCON)

#defineUFCON1 bUART(1,oUFCON)

#defineUMCON1 bUART(1,oUMCON)

#defineUTRSTAT1 bUART(1,oUTRSTAT)

#defineUERSTAT1 bUART(1,oUERSTAT)

#defineUFSTAT1 bUART(1,oUFSTAT)

#defineUMSTAT1 bUART(1,oUMSTAT)

#defineUTXH1 bUARTb(1,oUTXHL)

#defineURXH1 bUARTb(1,oURXHL)

#defineUBRDIV1 bUART(1,oUBRDIV)

#defineULCON2 bUART(2,oULCON)

#defineUCON2 bUART(2,oUCON)

#defineUFCON2 bUART(2,oUFCON)

#defineUMCON2 bUART(2,oUMCON)

#defineUTRSTAT2 bUART(2,oUTRSTAT)

#defineUERSTAT2 bUART(2,oUERSTAT)

#defineUFSTAT2 bUART(2,oUFSTAT)

#defineUMSTAT2 bUART(2,oUMSTAT)

#defineUTXH2 bUARTb(2,oUTXHL)

#defineURXH2 bUARTb(2,oURXHL)

#defineUBRDIV2 bUART(2,oUBRDIV)

/*...*/

#defineUTRSTAT_TX_EMPTY (1<<2)

#defineUTRSTAT_RX_READY (1<<0)

#defineUART_ERR_MASK 0xF

/*Interrupts*/

#defineINT_CTL_BASE 0x4A000000

#definebINT_CTL(Nb) __REG(INT_CTL_BASE+(Nb))

/*Offset*/

#defineoSRCPND 0x00

#defineoINTMOD 0x04

#defineoINTMSK 0x08

#defineoPRIORITY 0x0a

#defineoINTPND 0x10

#defineoINTOFFSET 0x14

#defineoSUBSRCPND 0x18

#defineoINTSUBMSK 0x1C

/*Registers*/

#defineSRCPND bINT_CTL(oSRCPND)

#defineINTMOD bINT_CTL(oINTMOD)

#defineINTMSK bINT_CTL(oINTMSK)

#definePRIORITY bINT_CTL(oPRIORITY)

#defineINTPND bINT_CTL(oINTPND)

#defineINTOFFSET bINT_CTL(oINTOFFSET)

#defineSUBSRCPND bINT_CTL(oSUBSRCPND)

#defineINTSUBMSK bINT_CTL(oINTSUBMSK)

#defineINT_ADCTC (1<<31) /*ADCEOCinterrupt*/

#defineINT_RTC (1<<30) /*RTCalarminterrupt*/

#defineINT_SPI1 (1<<29) /*UART1transmitinterrupt*/

#defineINT_UART0 (1<<28) /*UART0transmitinterrupt*/

#defineINT_IIC (1<<27) /*IICinterrupt*/

#defineINT_USBH (1<<26) /*USBhostinterrupt*/

#defineINT_USBD (1<<25) /*USBdeviceinterrupt*/

#defineINT_RESERVED24 (1<<24)

#defineINT_UART1 (1<<23) /*UART1receiveinterrupt*/

#defineINT_SPI0 (1<<22) /*SPIinterrupt*/

#defineINT_MMC (1<<21) /*MMCinterrupt*/

#defineINT_DMA3 (1<<20) /*DMAchannel3interrupt*/

#defineINT_DMA2 (1<<19) /*DMAchannel2interrupt*/

#defineINT_DMA1 (1<<18) /*DMAchannel1interrupt*/

#defineINT_DMA0 (1<<17) /*DMAchannel0interrupt*/

#defineINT_LCD (1<<16) /*reservedforfutureuse*/

#defineINT_UART2 (1<<15) /*UART2interrupt*/

#defineINT_TIMER4 (1<<14) /*Timer4interrupt*/

#defineINT_TIMER3 (1<<13) /*Timer3interrupt*/

#defineINT_TIMER2 (1<<12) /*Timer2interrupt*/

#defineINT_TIMER1 (1<<11) /*Timer1interrupt*/

#defineINT_TIMER0 (1<<10) /*Timer0interrupt*/

#defineINT_WDT (1<<9) /*Watch-Dogtimerinterrupt*/

#defineINT_TICK (1<<8) /*RTCtimetickinterrupt*/

#defineINT_BAT_FLT (1<<7)

#defineINT_RESERVED6 (1<<6) /*Reservedforfutureuse*/

#defineINT_EINT8_23 (1<<5) /*Externalinterrupt8~23*/

#defineINT_EINT4_7 (1<<4) /*Externalinterrupt4~7*/

#defineINT_EINT3 (1<<3) /*Externalinterrupt3*/

#defineINT_EINT2 (1<<2) /*Externalinterrupt2*/

#defineINT_EINT1 (1<<1) /*Externalinterrupt1*/

#defineINT_EINT0 (1<<0) /*Externalinterrupt0*/

#defineINT_ADC (1<<10)

#defineINT_TC (1<<9)

#defineINT_ERR2 (1<<8)

#defineINT_TXD2 (1<<7)

#defineINT_RXD2 (1<<6)

#defineINT_ERR1 (1<<5)

#defineINT_TXD1 (1<<4)

#defineINT_RXD1 (1<<3)

#defineINT_ERR0 (1<<2)

#defineINT_TXD0 (1<<1)

#defineINT_RXD0 (1<<0)

/*NANDFlashController*/

#defineNAND_CTL_BASE 0x4E000000

#definebINT_CTL(Nb) __REG(INT_CTL_BASE+(Nb))

/*Offset*/

#defineoNFCONF 0x00

#defineoNFCMD 0x04

#defineoNFADDR 0x08

#defineoNFDATA 0x0c

#defineoNFSTAT 0x10

#defineoNFECC 0x14

/*PWMTimer*/

#definebPWM_TIMER(Nb)__REG(0x51000000+(Nb))

#definebPWM_BUFn(Nb,x)bPWM_TIMER(0x0c+(Nb)*0x0c+(x))

/*Registers*/

#defineTCFG0bPWM_TIMER(0x00)

#defineTCFG1bPWM_TIMER(0x04)

#defineTCONbPWM_TIMER(0x08)

#defineTCNTB0bPWM_BUFn(0,0x0)

#defineTCMPB0bPWM_BUFn(0,0x4)

#defineTCNTO0bPWM_BUFn(0,0x8)

#defineTCNTB1bPWM_BUFn(1,0x0)

#defineTCMPB1bPWM_BUFn(1,0x4)

#defineTCNTO1bPWM_BUFn(1,0x8)

#defineTCNTB2bPWM_BUFn(2,0x0)

#defineTCMPB2bPWM_BUFn(2,0x4)

#defineTCNTO2bPWM_BUFn(2,0x8)

#defineTCNTB3bPWM_BUFn(3,0x0)

#defineTCMPB3bPWM_BUFn(3,0x4)

#defineTCNTO3bPWM_BUFn(3,0x8)

#defineTCNTB4bPWM_BUFn(4,0x0)

#defineTCNTO4bPWM_BUFn(4,0x4)

/*Fields*/

#definefTCFG0_DZONEFld(8,16)/*thedeadzonelength(=timer0)*/

#definefTCFG0_PRE1Fld(8,8)/*prescalervaluefortime2,3,4*/

#definefTCFG0_PRE0Fld(8,0)/*prescalervaluefortime0,1*/

#definefTCFG1_MUX4 Fld(4,16)

/*bits*/

#defineTCFG0_DZONE(x)FInsrt((x),fTCFG0_DZONE)

#defineTCFG0_PRE1(x)FInsrt((x),fTCFG0_PRE1)

#defineTCFG0_PRE0(x)FInsrt((x),fTCFG0_PRE0)

#defineTCON_4_AUTO(1<<22)/*autoreloadon/offforTimer4*/

#defineTCON_4_UPDATE(1<<21)/*manualUpdateTCNTB4*/

#defineTCON_4_ONOFF(1<<20)/*0:Stop,1:startTimer4*/

#defineCOUNT_4_ON(TCON_4_ONOFF*1)

#defineCOUNT_4_OFF(TCON_4_ONOFF*0)

#defineTCON_3_AUTO(1<<19)/*autoreloadon/offforTimer3*/

#defineTIMER3_ATLOAD_ON(TCON_3_AUTO*1)

#defineTIMER3_ATLAOD_OFFFClrBit(TCON,TCON_3_AUTO)

#defineTCON_3_INVERT(1<<18)/*1:InverteronforTOUT3*/

#defineTIMER3_IVT_ON(TCON_3_INVERT*1)

#defineTIMER3_IVT_OFF(FClrBit(TCON,TCON_3_INVERT))

#defineTCON_3_MAN(1<<17)/*manualUpdateTCNTB3,TCMPB3*/

#defineTIMER3_MANUP(TCON_3_MAN*1)

#defineTIMER3_NOP(FClrBit(TCON,TCON_3_MAN))

#defineTCON_3_ONOFF(1<<16)/*0:Stop,1:startTimer3*/

#defineTIMER3_ON(TCON_3_ONOFF*1)

#defineTIMER3_OFF(FClrBit(TCON,TCON_3_ONOFF))

/*macros*/

#defineGET_PRESCALE_TIMER4(x) FExtr((x),fTCFG0_PRE1)

#defineGET_DIVIDER_TIMER4(x) FExtr((x),fTCFG1_MUX4)

/*

*NANDFlashController(1~6-8)

*

*Register

NFCONFNANDFlashConfiguration[word,R/W,0x00000000]

NFCMDNANDFlashCommandSet[word,R/W,0x00000000]

NFADDRNANDFlashAddressSet[word,R/W,0x00000000]

NFDATANANDFlashData[word,R/W,0x00000000]

NFSTATNANDFlashStatus[word,R,0x00000000]

NFECCNANDFlashECC[3bytes,R,0x00000000]

*

*/

#definebNAND_CTL(Nb)__REG(0x4e000000+(Nb))

#defineNFCONFbNAND_CTL(0x00)

#defineNFCMDbNAND_CTL(0x04)

#defineNFADDRbNAND_CTL(0x08)

#defineNFDATAbNAND_CTL(0x0c)

#defineNFSTATbNAND_CTL(0x10)

#defineNFECCbNAND_CTL(0x14)

#definefNFCONF_TWRPH1Fld(3,0)

#defineNFCONF_TWRPH1FMsk(fNFCONF_TWRPH1)

#defineNFCONF_TWRPH1_0FInsrt(0x0,fNFCONF_TWRPH1)/*0*/

#definefNFCONF_TWRPH0Fld(3,4)

#defineNFCONF_TWRPH0FMsk(fNFCONF_TWRPH0)

#defineNFCONF_TWRPH0_3FInsrt(0x3,fNFCONF_TWRPH0)/*3*/

#definefNFCONF_TACLSFld(3,8)

#defineNFCONF_TACLSFMsk(fNFCONF_TACLS)

#defineNFCONF_TACLS_0FInsrt(0x0,fNFCONF_TACLS)/*0*/

#definefNFCONF_nFCEFld(1,11)

#defineNFCONF_nFCEFMsk(fNFCONF_nFCE)

#defineNFCONF_nFCE_LOWFInsrt(0x0,fNFCONF_nFCE)/*active*/

#defineNFCONF_nFCE_HIGHFInsrt(0x1,fNFCONF_nFCE)/*inactive*/

#definefNFCONF_ECCFld(1,12)

#defineNFCONF_ECCFMsk(fNFCONF_ECC)

#defineNFCONF_ECC_NINITFInsrt(0x0,fNFCONF_ECC)/*notinitialize*/

#defineNFCONF_ECC_INITFInsrt(0x1,fNFCONF_ECC)/*initialize*/

#definefNFCONF_ADDRSTEPFld(1,13)/*AddressingStep*/

#defineNFCONF_ADDRSTEPFMsk(fNFCONF_ADDRSTEP)

#definefNFCONF_PAGESIZEFld(1,14)

#defineNFCONF_PAGESIZEFMsk(fNFCONF_PAGES