VHDL数字电路课程实验报告

VHDL数字电路课程实验报告实验一8分频器一、实验要求：分别用信号量和变量实现八分频器二、实验过程：1、代码：8分频器vhdlibraryieee;useieee.std_logic_1164.all;entityfreq_dividerisport(clk:instd_logic;out1,out2:bufferbit);endfreq_divider;architectureexampleoffreq_dividerissignalcount1:integerrange0to7;beginprocess(clk)variablecount2:integerrange0to7;beginif(clk'eventandclk='1')thencount1<=count1+1;count2:=count2+1;if(count1=3)thenout1<=notout1;count1<=0;endif;if(count2=4)thenout2<=notout2;count2:=0;endif;endif;endprocess;endexample;八分频器tbLIBRARYieee;USEieee.std_logic_1164.all;ENTITYfd_tbisENDfd_tb;architecturebehavioroffd_tbiscomponentfreq_dividerport(clk:INSTD_LOGIC;out1,out2:bufferbit);endcomponent;signalclk:std_logic;signalout1,out2:bit;beginu1:freq_dividerportmap(clk,out1,out2);processbeginclk<='0';waitfor50ns;loopclk<=notclk;waitfor25ns;endloop;endprocess;endbehavior;2、结果图：实验二实现例8.6实验要求：电路只有一个输入时钟信号，输出信号在适中的两个边沿都会发生变化实验内容：代码信号发生器vhdENTITYsignal_genISPORT(clk:INBIT;outp:OUTBIT);ENDsignal_gen;ARCHITECTUREfsmOFsignal_genISTYPEstateIS(one,two,three);SIGNALpr_state1,nx_state1:state;SIGNALpr_state2,nx_state2:state;SIGNALout1,out2:BIT;BEGINPROCESS(clk)BEGINIF(clk'EVENTANDclk='1')THENpr_state1<=nx_state1;ENDIF;ENDPROCESS;PROCESS(clk)BEGINIF(clk'EVENTANDclk='0')THENpr_state2<=nx_state2;ENDIF;ENDPROCESS;PROCESS(pr_state1)BEGINCASEpr_state1ISWHENone=>out1<='0';nx_state1<=two;WHENtwo=>out1<='1';nx_state1<=three;WHENthree=>out1<='1';nx_state1<=one;ENDCASE;ENDPROCESS;PROCESS(pr_state2)BEGINCASEpr_state2ISWHENone=>out2<='1';nx_state2<=two;WHENtwo=>out2<='0';nx_state2<=three;WHENthree=>out2<='1';nx_state2<=one;ENDCASE;ENDPROCESS;outp<=out1ANDout2;ENDfsm;信号发生器tbentitytb_fsmisendtb_fsm;architecturebehavioroftb_fsmiscomponentsignal_genisport(clk:inbit;outp:outbit);endcomponent;signalclk,outp:bit;beginu1:signal_genportmap(clk,outp);processbeginclk<='0';waitfor20ns;loopclk<=notclk;waitfor10ns;endloop;endprocess;endbehavior;结果图实验三常数比较器实验要求常数比较器，用于比较的变量位宽应大于等于常数实验内容代码常数比较器vhdLIBRARYieee;USEieee.std_logic_1164.all;entitycompareisport(b:inintegerrange0to15;x1,x2,x3:outstd_logic);endcompare;architecturecompareofcompareisconstanta:integer:=10;beginx1<='1'whena>belse'0';x2<='1'whena=belse'0';x3<='1'whena<belse'0';endcompare;常数比较器tbLIBRARYieee;USEieee.std_logic_1164.all;entitytb_compareisendtb_compare;architecturebehavioroftb_compareiscomponentcompareport(b:inintegerrange0to15;x1,x2,x3:outstd_logic);endcomponent;signalb:integer;signalx1,x2,x3:std_logic;beginu1:compareportmap(b,x1,x2,x3);processbeginb<=5;waitfor10ns;b<=8;waitfor10ns;b<=10;waitfor10ns;b<=13;waitfor10ns;b<=10;waitfor10ns;b<=3;waitfor10ns;endprocess;endbehavior;结果图实验四序列检测器实验要求序列检测’1001’弱检测到，输出‘1‘，否则输出’0‘实验内容状态图ZZeroq=0fourq=1twoq=0oneq=0threeq=0d=0d=1d=1d=1d=1d=1d=0d=0d=0rstd=0代码序列检测器vhdlibraryieee;useieee.std_logic_1164.all;entitystring_detectorisport(datain,clk:inbit;q:outbit);endstring_detector;architecturesdofstring_detectoristypestateis(zero,one,two,three,four);signalpr_state,nx_state:state;beginprocess(clk)beginif(clk'eventandclk='1')thenpr_state<=nx_state;endif;endprocess;process(datain,pr_state)begincasepr_stateiswhenzero=>q<='0';if(datain='1')thennx_state<=one;elsenx_state<=zero;endif;whenone=>q<='0';if(datain='0')thennx_state<=two;elsenx_state<=zero;endif;whentwo=>q<='0';if(datain='0')thennx_state<=three;elsenx_state<=zero;endif;whenthree=>q<='0';if(datain='1')thennx_state<=four;elsenx_state<=zero;endif;whenfour=>q<='1';nx_state<=zero;endcase;endprocess;endsd;序列检测器tb------------------------------------------------------------------libraryieee;useieee.std_logic_1164.all;------------------------------------------------------------------entitytestBenchisendtestBench;------------------------------------------------------------------architecturetestoftestBenchiscomponentstring_detectorisport(datain,clk:inbit;q:outbit);endcomponent;signaldatain,clk:bit;signalq:bit;beginSD:string_detectorportmap(datain,clk,q);processbeginforiin0to100loopclk<='0';waitfor10ns;clk<='1';waitfor10ns;endloop;endprocess;processbegindin<='1';waitfor20ns;din<='0';waitfor20ns;din<='0';waitfor20ns;din<='0';waitfor20ns;din<='1';waitfor20ns;