DSP原理与应用-第2章 CPU结构与指令集

第二章CPU结构与指令集第二章CPU结构与指令集2.1CPU结构2.2C67x指令集

2.3流水线

2.4中断

DSP的一般结构2.1CPU结构外设CPU内部存储器内部总线外部存储器数据寄存器处理单元片内存储器片外存储器存储器的层次2.1.1CPU结构框图程序取指指令分配指令译码程序执行机构程序总线数据总线存储器映射(统一编址)描述起始地址终止地址单字节或四字节寻址内部ROM页0(256KBytes)0x000000000x0003FFFF单字节或四字节内部ROM页1(128KBytes)0x000400000x0005FFFF单字节或四字节内部RAM页0(256KBytes)0x100000000x1003FFFF单字节或四字节存储器和缓存控制寄存器0x200000000x2000001F单字节器件配置寄存器0x400000000x40000083单字节PLL控制寄存器0x410000000x4100015F单字节定时器(RTI)控制寄存器0x420000000x420000A3单字节通用主机接口(UHPI)寄存器0x430000000x43000043单字节McASP0控制寄存器0x440000000x440002BF单字节SPI0控制寄存器0x470000000x4700007F单字节I2C0控制寄存器0x490000000x4900007F单字节I2C1控制寄存器0x4A0000000x4A00007F单字节McASP0DMA端口(此范围内的任何地址)0x540000000x54FFFFFF单字节dMAX控制寄存器0x600000000x6000008F单字节dMAX0(HiMAX)事件入口表0x610080000x6100807F单字节或四字节dMAX0(HiMAX)传输入口表0x610080A00x610081FF单字节或四字节通过EMIF访问的外部SDRAM空间0x800000000x8FFFFFFF单字节或四字节通过EMIF访问的外部异步器件/Flash空间0x900000000x9FFFFFFF单字节或四字节EMIF控制寄存器0xF00000000xF00000BF单字节2.1.2CPU数据通道2个通用存放器组(A和B)，包括32个存放器8个功能单元(.L1、.L2、.S1、.S2、.M1、.M2、.D1、.D2)2个数据读取通路(LD1和LD2)，每侧有2个32位读取总线2个数据存储通路(ST1和ST2)，每侧有1个32位存储总线2个存放器组交叉通路(1x和2x)2个数据寻址通路(DA1和DA2)1.通用存放器组功能(1)存放数据，作为指令的源操作数和目的操作数。注意传送方向和数据字长(2)作为间接寻址的地址指针，存放器A4～A7和B4～B7还能够以循环寻址方式工作(3)A1、A2、B0、B1和B2可用做条件存放器A1:A0A3:A2…A29:A28A31:A30oddeven:32840-bitRegB1:B0B3:B2…B29:B28B31:B30oddeven:32840-bitReg40位/64位存放器对

Allcombinationsof40-bitregistersareshownbelow:Theregistersmustbefromthesameside.Thefirstregistermustbeevenandthesecondodd.Theregistersmustbeconsecutive.2.功能单元功能单元定点操作浮点操作.L单元32／40位算术和比较操作32-位最左边1或0的位数计数32位和40位归一化操作32位逻辑操作算术操作数据类型转换操作DP→SPINT→DP，INT→SP.S单元32位算术操作32／40位移位和32位位域操作32位逻辑操作转移常数产生寄存器与控制器数据传递(仅.S2)比较倒数和倒数平方根操作绝对值操作SP→DP数据类型转换.M单元16×16位乘法操作32×32乘法操作浮点乘法操作.D单元32-位加，减，线性及循环寻址计算带5位常数偏移量的字读取与存储带15位常数偏移量的字读取与存储(仅.D2)带5位常数偏移量的双字读取3.存放器组交叉通路.L1、.S1、.D1和.M1可以直接读写存放器组A

.L2、.S2、.D2和.M2可以直接读写存放器组B

1x交叉通路允许数据通道A的功能单元从存放器组B读它的源操作数

2x交叉通路允许数据通道B的功能单元从存放器组A读它的源操作数4.数据存储器及读取存储通路(Load指令)存放器组A的读入通路为LD1(2个32位)

存放器组B的读入通路为LD2(2个32位)

LDDW指令一次可读取64位数据到A或B存放器

(Store指令)存放器组A的写数据通路为ST1存放器组B的写数据通路为ST25.数据地址通路数据地址通路DA1和DA2来自.D功能单元

数据通道以T1、T2表示

LDW.D1T2*A0[3]，B1D1产生地址，用LD2数据通道读入数据到B1存放器6.控制存放器组缩写寄存器名描述AMR寻址模式寄存器指定是否使用线性或循环寻址。如果是循环寻址，还包括循环寻址的尺寸CSR控制状态寄存器包括全局中断使能位，高速缓冲存储器控制位和其他各种控制和状态位FADCR浮点加法配置寄存器指定.L单元的溢出方式，舍入方式，记录NaN及其他异常FAUCR浮点辅助配置寄存器记录.S单元NaN及其他异常FMCR浮点乘法配置寄存器指定.M单元的溢出方式，舍入方式，记录NaN及其他异常ICR中断清除寄存器允许软件清除挂起的中断IER中断使能寄存器允许使能／禁止个别中断IFR中断标志寄存器显示中断状态IRP中断返回指针保存从可屏蔽中断返回时的地址ISR中断设置寄存器允许软件控制设置中断ISTP中断服务表指针指向中断服务表的起始地址NRP不可能屏蔽中断返回指针保存从不可屏蔽中断返回时的地址PCE1程序计数器保存处于流水线E1节拍的取指包地址6.控制存放器组模式描述00线性寻址(复位后默认值)01循环寻址使用BK0字段10循环寻址使用BK1字段11保留寻址模式存放器(AMR)控制状态存放器(CSR)位字段名功能15−10PWRD控制低功耗模式，该值读时总为零9SAT饱和位。任一功能单元执行一个饱和操作时被置1，饱和位只能有MVC指令清零，被功能单元饱和操作置位。当清除和置位在同一周期内发生时，功能单元对它的置位优先。饱和位在饱和发生后一个周期被置位8EN端结方式：1=小端终结，0=大端终结7−5PCCPCC程序高速缓冲存储器控制模式4−2DCC数据高速缓冲存储器控制模式1PGIE当一个中断发生时，保存以前的全局中断使能位GIE0GIE全局中断使能位，它控制除复位和不可屏蔽中断之外的所有可屏蔽中断使能：GIE=1时，可屏蔽中断使能：GIE=0时，可屏蔽中断禁止6.控制存放器组指令集概述2.延迟间隙延迟间隙在数量上等于从指令的源操作数被读取直到执行的结果可以被访问所需要的指令周期数。指令类型延迟间隙功能单元等待时间读周期写周期单周期01ii2周期DP11ii,i+1DP比较12i,i+11+14周期31ii+3INT到DP转换41ii+3,i+4Load41ii,i+4MPYSP2DP42ii+3,i+4ADDDP/SUBDP62i,i+1i+5,i+6MPYSPDP63i,i+1i+5,i+6MPYI84i,i+1,1+2,i+3i+8MPYID94i,i+1,1+2,i+3i+8,i+9MPYDP94i,i+1,1+2,i+3i+8,i+93.指令操作码映射图代码段说明creg指定条件寄存器的代码z指定条件src,dst分别指定源及目的操作数代码x指定源操作数2是否使用交叉通道op指令操作代码s选择寄存器组A或B作为目的操作数p指定是否并行执行CPU运行时，总是一次取

8条指令，组成一个取指包

所有并行执行的指令组成一个执行包

周期/执行包指令1A2B3CDE4FGH4.并行操作3位操作码字段creg指定条件存放器1位字段z指定是零测试还是非零测试z=1，进行零测试，即条件存放器的内容为0是真z=0，进行非零测试，即条件存放器的内容非0是真creg=0，z=0，那么指令将无条件地执行条件存放器：A1、A2、B0、B1和B2[B0]ADD.L1A1，A2，A3||[!B0]ADD.L2B1，B2，B3以上2条指令是相互排斥5.条件操作6.寻址方式全部采用间接寻址

所有存放器都可以做线性寻址的地址指针

循环寻址的地址指针：A4-A7，B4-B7

由AMR控制地址修改方式：线件方式或循环方式

循环寻址循环块的尺寸与BK0／BK1内5位数值N的关系为块尺寸＝2(N+1)字节例如N的二进制数为10000，等于十进制16，那么块尺寸＝2(16+1)＝131072字节寻址方式不修改地址寄存器先修改地址寄存器后修改地址寄存器寄存器间接寻址*R*＋＋R*－－R*R＋＋*R－－寄存器相对寻址*＋R[ucst5]*－R[ucst5]*＋＋R[ucst5]*－－R[ucst5]*R＋＋[ucst5]*R－－[ucst5]基地址+变址*＋R[offseR]*－R[offseR]*＋＋R[offseR]*－－R[offseR]*R＋＋[offseR]*R－－[offseR]带15位常数偏移量的寄存器相对寻址*+B14／B15[ucst15]6.寻址方式读取／存储类指令访问数据存储器地址的汇编语法格式

ucst5-----无符号二进制5位常数偏移量ucst15---无符号二进制15位常数偏移量Little-endianordering,inwhichbytesareorderedfromrighttoleft,themostsignificantbytehavingthehighestaddressBig-endianordering,inwhich

bytes

areorderedfromlefttoright,themostsignificantbytehavingthelowestaddress大小端位由DSP的LENDIAN管脚设置终结方式(大小端位)BA987654h11,10,01,00BA987654h00,01,10,11终结方式(大小端位)C6000DSP汇编指令分类2.2.2读取/存储类指令读取指令：LDB／LDBU／LDH／LDHU／LDW／LDDW

存储指令：STB／STH／STW

单字节(Byte)、双字节(半字HalfWord)和四字节(字Word)位数不同有符号/无符号(U)，符号位的扩展不同地址偏移修正因子：LDB(U)／LDH(U)／LDW指令分别读入字节／半字／字，要乘以相应的比例因子1、2、4

2.2.2读取/存储类指令例2-1线性寻址下的变址计算

LDW.D1*++A4[1],A6

此例为先修改地址，地址偏移量按1×4计算，计算结果如下所示：例如02012.2.2读取/存储类指令例2-2循环寻址方式下的地址计算

LDW.D1*++A4[9],A1

此处假设寻址模式存放器AMR=0x00030001，A4已被设定为循环寻址方式，块字节尺寸为24=16=10h(N=3)。因为是以字为单位读取，变址偏移量为9×4=36=24h。线件寻址时地址应为00000124h；循外寻址时，24h对低4位(第0-3位)地址10h取模，余数为4，故实际寻址地址为00000104h。

例如02021.加减运算指令

(1)ADD/ADDU/SUB/SUBU

操作数为整型(32位)或长整型(40位)的指令(2)ADD2/SUB2

操作数为半字(16位)的指令，ADD2／SUB2指令的特点是同时进行2个16位补码数的加减运算，高半字与低半字之间没有进／借位，各自独立进行(3)SADD/SSUB

带饱和的有符号数加减运算指令，操作数为32位或40位有符号数(4)ADDK

与16位常数进行加法操作的指令(5)ADDAB／ADDAH／ADDAW／ADDAD，SUBAB／SUBAH／SUBAW

按寻址方式的加减运算类指令溢出问题如果运算结果超出目的操作数字长所能表示的范围，造成运算结果的高位丧失，使保存的运算结果不正确，称为溢出。通常有3种方法解决溢出问题(1)用较长的字长来存放运算结果：1632可行，3240耗时(2)用带饱和的加减运算指令做补码数加减运算：保证符号不变，并且给出提示位(3)对整个系统乘一个小于1的比例因子：实际中最常用例2-3减法运算举例SSUB.L2B1,B2,B3SUB.L2B1,B2,B3SUB.L2B1,B2,B5:B4例如0203溢出了!符号位在这里无溢出!例2-4计算累加和的程序，用长型数存放和数，有8位保护位，例如0204Loop:LDW.D1*A4++,A0NOP4ADD.L1A3:A2,A0,A3:A2SUB.L2B1,1,B1[B1]B.S1LoopNOP5例2-5按寻址方式的加法运算指令ADDAH.D1A4,A2,A4B×2=16h对8取余得6例如0205例2-6按寻址方式的减法运算指令SUBAB.D1A5,A0,A5-4×1=-4h对10h取余得C例如02052.乘法运算指令

(1)适宜于整数乘法的指令

以MPY为首字母的22条指令

(2)适宜于Q格式数相乘的3条指令

SMPY／SMPYLH／SMPYHL

以16×16位的硬件乘法器为根底，整数乘法的2个源操作数都是16位字长，目的操作数为32的存放器，不存在溢出问题。所谓定点格式，即约定机器中所有数据的小数点位置是固定不变的。在计算机中通常采用两种简单的约定：将小数点的位置固定在数据的最高位之前，或者是固定在最低位之后。一般常称前者为定点小数，后者为定点整数。Q格式：小数点位于第n位之右侧，称为Qn格式定点小数是纯小数，约定的小数点位置在符号位之后、有效数值局部最高位之前。假设数据x的形式为x=x0.x1x2…xn(其中x0为符号位，x1～xn是数值的有效局部，也称为尾数，x1为最高有效位)，那么在计算机中的表示形式为：Q格式定点数2-n

≤|x|≤1-2-nQ0格式数定点整数是纯整数，约定的小数点位置在有效数值局部最低位之后。假设数据x的形式为x=x0x1x2…xn(其中x0为符号位，x1～xn是尾数，xn为最低有效位)，那么在计算机中的表示形式为：Q格式定点数1≤|x|≤2n-1

Q15格式数例2-7整数乘法运算

(1)MPYH.M1A1,A2,A3

(2)MPYHU.M1A1,A2,A3

例如0207符号位扩展无符号数2.2.4逻辑及位域操作指令MV:

通用存放器之间传送数据MVC:

用于在通用存放器与控制存放器之间传送数据，此条指令只能使用.S2功能单元MVK:

用于把16位常数送入通用存放器MVKH/MVKLHMVKL结合生成32位常量2.2.5搬移类指令用标号label表示目标地址的转移指令B(.S)label用存放器表示目标地址的转移指令B.S2src2从可屏蔽中断存放器取目标地址的转移指令B.S2IRP从不可屏蔽中断存放器取目标地址的转移指令B.S2NRP转移指令有5个指令周期的延迟间隙。转移指令后的5个指令执行包全部进入CPU流水线，并相继执行。

程序转移类指令2.2.7浮点运算指令(1)浮点加减法指令

ADDSP/ADDDP/SUBSP/SUBDP

(2)数据类型转换指令10条

INTSP(U)/INTDP(U)/SPINT/DPINT/SPDP/SPTRUNC/DPSP/DPTRUNC

(3)浮点乘法及32位整数乘法指令6条

MPYSP／MPYSPDP／MPYSP2DP／MPYDP／MPYI／MPYID

(4)特殊的浮点运算指令6条

ABSSP／ABSDP／RCPSP／RCPDP(倒数)／RSQRSP／RSQRDP(平方根倒数)

(5)单／双精度浮点数的比较判决指令6条

CMPLTSP／CMPLTDP／CMPGTSP／CMPGTDP／CMPEQSP／CMPEQDP

(6)双精度数据的读取／存储指令

LDDW／STDW1.IEEE标准的浮点数表示法s代表数的符号，0为正，1为负

e是指数阶码，视做无符号数(0<e<255)

f是尾数的分数局部floatdouble32位单精度浮点数格式数的格式符号位(s)指数阶码(e)尾数的分数(f)代表的数值规格化数x0<e<255x(-1)s×2(e-127)×1.f非规格化数x0非零(-1)s×2(-126)×0.f无穷大数02550+无穷大12550−无穷大无效数x255非零NaN(Not-a-Number)x2551xx..xQnaN(QuietNaN)x2550xx..x和非零SnaN(SignalNaN)符号十六进制值十进制值备注NaN_out0x7FFFFFFFQnaN(QuietNaN)00x000000000.0-00x80000000-0.010x3F8000001.020x400000002.0LFPN0x7F7FFFFF3.40282347e+38单精度规格化浮点数最大值SFPN0x008000001.17549435e-38单精度规格化浮点数正最小值LDFPN0x0007FFFF1.17549421e-38单精度非规格化浮点数最大值SDFPN0x000000011.40129846e-45单精度非规格化浮点数正最小值一些特殊数的单精度浮点数的符号1+2-1+2-2+…+2-23=1+=1+1-2-23=1.99999988079071044921875×2127=3.40282346638528860e+3864位双精度浮点数格式数的格式符号位(s)指数阶码(e)尾数的分数(f)代表的数值规格化数x0<e<2047x(-1)s×2(e-1023)×1.f非规格化数x0非零(-1)s×2(-1022)×0.f无穷大数020470+无穷大120470−无穷大无效数x2047非零NaN(Not-a-Number)x20471xx..xQnaN(QuietNaN)x20470xx..x和非零SnaN(SignalNaN)一些特殊数的单精度浮点数的符号符号十六进制值十进制值备注NaN_out0x7FFFFFFFFFFFFFFFQnaN(QuietNaN)00x00000000000000000.0-00x8000000000000000-0.010x3F800000000000001.020x40000000000000002.0LFPN0x7F7FFFFFFFFFFFFF1.7976931348623157e+308单精度规格化浮点数最大值SFPN0x00800000000000002.2250738585072014e−308单精度规格化浮点数正最小值LDFPN0x0007FFFFFFFFFFFF2.2250738585072009e−308单精度非规格化浮点数最大值SDFPN0x00000000000000014.9406564584124654e−324单精度非规格化浮点数正最小值2.C672x的浮点运算控制存放器作用:

(1)为.L、.S和.M单元的运算设置浮点舍入方式；

(2)包括一些字段用来记录指令执行中遇到的问题，以便检查，包括：

源操作数src1和src2是否是无效数NaN或非规格化数；

结果是否上溢、下溢、不准确、无穷大或者无效；

是否执行了除以零的操作；

是否用了NaN源操作数作比较等。FADCR2.C672x的浮点运算控制存放器ImplementationofSumofProducts(SOP)ImplementationofSumofProducts(SOP)SOPisthekeyelementformostDSPalgorithms.Solet’swritethecodeforthisalgorithmandatthesametimelearntheC6000architecture.Twobasicoperationsarerequiredforthisalgorithm.(1)Multiplication(2)AdditionThereforetwobasicinstructionsarerequiredY=N

an

xnn=1*=a1

*x1+a2*x2

+...+aN*

xNMultiply(MPY)Themultiplicationofa1byx1isdoneinassemblybythefollowinginstruction:MPY a1,x1,YThisinstructionisperformedbyamultiplierunitthatiscalled“.M〞Y=N

an

xnn=1*=a1

*x1+a2*x2

+...+aN*

xNTheimplementationinthismodulewillbedoneinassembly.Multiply(.Munit).MY=40

an

xnn=1*The.MunitperformsmultiplicationsinhardwareMPY .M a1,x1,Y

Note:16-bitby16-bitmultiplierprovidesa32-bitresult. 32-bitby32-bitmultiplierprovidesa64-bitresult.Addition(.?).M.?Y=40

an

xnn=1*

MPY .M a1,x1,prod

ADD .? Y,prod,Y

Add(.Lunit).M.LY=40

an

xnn=1*

MPY .M a1,x1,prod

ADD .L Y,prod,Y

RISCprocessorssuchastheC6000useregisterstoholdtheoperands,soletschangethiscode.RegisterFile-AY=40

an

xnn=1*

MPY .M a1,x1,prod ADD .L Y,prod,Y

.M.LA0A1A2A3A4A15RegisterFileA.

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.a1x1prod32-bitsYLetuscorrectthisbyreplacinga,x,prodandYbytheregistersasshownabove.SpecifyingRegisterNamesY=40

an

xnn=1*

MPY .M A0,A1,A3 ADD .L A4,A3,A4

TheregistersA0,A1,A3andA4containthevaluestobeusedbytheinstructions..M.LA0A1A2A3A4A15RegisterFileA.

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.a1x1prod32-bitsYY=40

an

xnn=1*

MPY .M A0,A1,A3 ADD .L A4,A3,A4

RegisterFileAcontains16registers(A0-A15)whichare32-bitswide..M.LA0A1A2A3A4A15RegisterFileA.

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.a1x1prod32-bitsYSpecifyingRegisterNamesA:Theoperandsareloadedintotheregistersbyloadingthemfromthememoryusingthe.Dunit..M.LA0A1A2A3A15RegisterFileA.

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.a1x1prod32-bitsY.DDataMemoryQ:Howdoweloadtheoperandsintotheregisters?DataloadingA:Theloadinstructions..M.LA0A1A2A3A15RegisterFileA.

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.a1x1prod32-bitsY.DDataMemoryQ:Whichinstruction(s)canbeusedforloadingoperandsfromthememorytotheregisters?LoadInstructions(LDB,LDH,LDW,LDDW)0000000000000004000000080000000C00000010Data32-bitsBeforeusingtheloadunityouhavetobeawarethatthisprocessorisbyteaddressable,whichmeansthateachbyteisrepresentedbyauniqueaddress.Alsotheaddressesare32-bitwide.addressFFFFFFFFLoadInstructions(LDB,LDH,LDW,LDDW)Thesyntaxfortheloadinstructionis:Where:Rnisaregisterthatcontainstheaddressoftheoperandtobeloadedand

Rmisthedestinationregister.0000000000000004000000080000000C00000010Dataa1x1prod32-bitsYaddressFFFFFFFFLDx*Rn,RmLoadInstructions(LDB,LDH,LDW,LDDW)Thesyntaxfortheloadinstructionis:Thequestionnowishowmanybytesaregoingtobeloadedintothedestinationregister?0000000000000004000000080000000C00000010Dataa1x1prod32-bitsYaddressFFFFFFFFLoadInstructions(LDB,LDH,LDW,LDDW)LDx*Rn,RmThesyntaxfortheloadinstructionis:0000000000000004000000080000000C00000010Dataa1x1prod32-bitsYaddressFFFFFFFFTheanswer,isthatitdependsontheinstructionyouchoose: LDB:loadsonebyte(8-bit) LDH:loadshalfword(16-bit) LDW:loadsaword(32-bit) LDDW:loadsadoubleword(64-bit)Note:LDonitsowndoesnotexist.LoadInstructions(LDB,LDH,LDW,LDDW)LDx*Rn,Rm0000000000000004000000080000000C00000010Data32-bitsaddressFFFFFFFFDCBAExample:IfweassumethatA5=0x4then:(1) LDB*A5,A7;givesA7=0x00000001(2) LDH*A5,A7;givesA7=0x00000201(3) LDW*A5,A7;givesA7=0x04030201(4) LDDW*A5,A7:A6;

givesA7:A6=0x0807060504030201Thesyntaxfortheloadinstructionis:01LoadInstructions(LDB,LDH,LDW,LDDW)LDx*Rn,Rm43218765FE90Question:Ifdatacanonlybeaccessedbytheloadinstructionandthe.Dunit,howcanweloadtheregisterpointerRninthefirstplace?Thesyntaxfortheloadinstructionis:LoadInstructions(LDB,LDH,LDW,LDDW)LDx*Rn,Rm0000000000000004000000080000000C00000010Data32-bitsaddressFFFFFFFFDCBA0143218765FE90TheinstructionMVKLwillallowamoveofa16-bitconstantintoaregisterasshownbelow: MVKL.?a,A5 (‘a’isaconstantorlabel)Howmanybitsrepresentafulladdress?32bitsSowhydoestheinstructionnotallowa32-bitmove? Allinstructionsare32-bitwide(seeinstructionopcode).LoadingthePointerRnTosolvethisproblemanotherinstructionisavailable:

MVKH.?a,A5Finally,tomovethe32-bitaddresstoaregisterwecanuse:MVKL a,A5MVKH a,A5LoadingthePointerRnMVKL 0x1234FABC,A5A5=0xFFFFFABC;WrongExample1A5=0x87654321MVKL 0x1234FABC,A5A5=0xFFFFFABC(signextension)MVKH 0x1234FABC,A5A5=0x1234FABC;OKExample2

MVKH 0x1234FABC,A5A5=0x12344321AlwaysuseMVKLthenMVKH,lookatthefollowingexamples:

LoadingthePointerRnLDH,MVKLandMVKH.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.DDataMemory

MVKL pt1,A5MVKH pt1,A5MVKL pt2,A6MVKH pt2,A6LDH .D *A5,A0LDH .D *A6,A1

MPY .M A0,A1,A3ADD .L A4,A3,A4

CreatingaloopWiththeC6000processorstherearenodedicatedinstructionssuchasblockrepeat.TheloopiscreatedusingtheBinstruction.

SofarwehaveonlyimplementedtheSOPforonetaponly,i.e.Y=a1

*x1Solet’screatealoopsothatwecanimplementtheSOPforNTaps.Whatarethestepsforcreatingaloop1. Createalabeltobranchto.2. Addabranchinstruction,B.3. Createaloopcounter.4. Addaninstructiontodecrementtheloopcounter.5. Makethebranchconditionalbasedonthevalueintheloopcounter.1.Createalabeltobranchto

MVKL pt1,A5 MVKH pt1,A5 MVKL pt2,A6 MVKH pt2,A6loop LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4

MVKL pt1,A5 MVKH pt1,A5 MVKL pt2,A6 MVKH pt2,A6loop LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 B .? loop

2.Addabranchinstruction,B.DataMemoryWhichunitisusedbytheBinstruction?.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.S

MVKL .S pt1,A5 MVKH .S pt1,A5 MVKL .S pt2,A6 MVKH .S pt2,A6loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 B .S loop

DataMemory3.Createaloopcounter..M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.S

MVKL .S pt1,A5 MVKH .S pt1,A5 MVKL .S pt2,A6 MVKH .S pt2,A6 MVKL .S count,B0loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 B .S loop

Bregisterswillbeintroducedlater4.Decrementtheloopcounter.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.DDataMemory.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.S

MVKL .S pt1,A5 MVKH .S pt1,A5 MVKL .S pt2,A6 MVKH .S pt2,A6

MVKL .S count,B0loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4

SUB .S B0,1,B0 B .S loop

Whatisthesyntaxformakinginstructionconditional? [condition] Instruction Label e.g. [B0] B loop (1) Theconditioncanbeoneofthefollowingregisters:A1,A2,B0,B1,B2.(2) Anyinstructioncanbeconditional.5.MakethebranchconditionalTheconditioncanbeinvertedbyaddingtheexclamationsymbol“!〞asfollows: [!condition] Instruction Label e.g. [!B0] B loop;branchifB0=0 [B0] B loop ;branchifB0!=05.MakethebranchconditionalDataMemory.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.M.LA0A1A2A3A15RegisterFileA.

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.axprod32-bitsY.D.S

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6

MVKL .S2 count,B0loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0

[B0] B .S loop

5.MakethebranchconditionalCase1: B.S1 label

Relativebranch.Labellimitedto+/-220offset.

MoreontheBranchInstruction(1)Withthisprocessoralltheinstructionsareencodedina32-bit.Thereforethelabelmusthaveadynamicrangeoflessthan32-bitastheinstructionBhastobecoded.21-bitrelativeaddressB32-bitMoreontheBranchInstruction(2)Byspecifyingaregisterasanoperandinsteadofalabel,itispossibletohaveanabsolutebranch.Thiswillallowadynamicrangeof232.Case2: B.S2

registerAbsolutebranch.Operateson.S2ONLY!5-bitregistercodeB32-bitTestingthecodeThiscodeperformsthefollowingoperations:a0*x0+a0*x0+a0*x0+…+a0*x0However,wewouldliketoperform:a0*x0+a1*x1+a2*x2+…+aN*xN

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6

MVKL .S2 count,B0loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0[B0] B .S loop

ModifyingthepointersThesolutionistomodifythepointersA5andA6.

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6

MVKL .S2 count,B0loop

LDH .D *A5,A0 LDH .D *A6,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0[B0] B .S loop

IndexingPointersDescriptionPointerSyntaxPointer

Modified*RNoRcanbeanyregisterInthiscasethepointersareusedbutnotmodified.IndexingPointersDescriptionPointer+Pre-offset-Pre-offsetSyntaxPointer

Modified*R*+R[disp]*-R[disp]NoNoNo[ disp]specifiesthenumberofelementssizeinDW(64-bit),W(32-bit),H(16-bit),orB(8-bit).disp=Ror5-bitconstant.Rcanbeanyregister.InthiscasethepointersaremodifiedBEFOREbeingusedandRESTOREDtotheirpreviousvalues.IndexingPointersDescriptionPointer+Pre-offset-Pre-offsetPre-incrementPre-decrementSyntaxPointer

Modified*R*+R[disp]*-R[disp]*++R[disp]*--R[disp]NoNoNoYesYesInthiscasethepointersaremodifiedBEFOREbeingusedandNOTRESTOREDtotheirPreviousValues.IndexingPointersDescriptionPointer+Pre-offset-Pre-offsetPre-incrementPre-decrementPost-incrementPost-decrementSyntaxPointer

Modified*R*+R[disp]*-R[disp]*++R[disp]*--R[disp]*R++[disp]*R--[disp]NoNoNoYesYesYesYesInthiscasethepointersaremodifiedAFTERbeingusedandNOTRESTOREDtotheirPreviousValues.DescriptionPointer+Pre-offset-Pre-offsetPre-incrementPre-decrementPost-incrementPost-decrementSyntaxPointer

Modified*R*+R[disp]*-R[disp]*++R[disp]*--R[disp]*R++[disp]*R--[disp]NoNoNoYesYesYesYes[disp]specifies#elements-sizeinDW,W,H,orB.disp=Ror5-bitconstant.Rcanbeanyregister.IndexingPointersModifyandtestingthecodeThiscodenowperformsthefollowingoperations:a0*x0+a1*x1+a2*x2+...+aN*xN

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6

MVKL .S2 count,B0loop

LDH .D *A5++,A0 LDH .D *A6++,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0[B0] B .S loop

ThePointerA7isnowinitialised.

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6

MVKL .S2 pt3,A7 MVKH .S2 pt3,A7

MVKL .S2 count,B0loop LDH .D *A5++,A0 LDH .D *A6++,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0[B0] B .S loop

STH .D A4,*A7

StorethefinalresultWhatistheinitialvalueofA4?A4isusedasanaccumulator,soitneedstoberesettozero.

MVKL .S2 pt1,A5 MVKH .S2 pt1,A5 MVKL .S2 pt2,A6 MVKH .S2 pt2,A6 MVKL .S2 pt3,A7 MVKH .S2 pt3,A7

MVKL .S2 count,B0

ZERO .L A4loop LDH .D *A5++,A0 LDH .D *A6++,A1

MPY .M A0,A1,A3 ADD .L A4,A3,A4 SUB .S B0,1,B0[B0] B .S loop

STH .D A4,*A7

Howcanweaddmoreprocessingpowertothisprocessor?.S1.M1.L1.D1A0A1A2A3A4RegisterFileA.

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.DataMemoryA1532-bitsIncreasingtheprocessingpower!(1) Increasetheclockfrequency.(2) IncreasethenumberofProcessingunits..S1.M1.L1.D1A0A1A2A3A4RegisterFileA.

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.DataMemory32-bitsA15Increasingtheprocessingpower!TwosideProcessingunits(AandB)DataMemory.S1.M1.L1.D1A0A1A2A3A4RegisterFileA.

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.A1532-bits.S2.M2.L2.D2B0B1B2B3B4RegisterFileB.

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.B1532-bitsCantheyexchangeoperands?.S1.M1.L1.D1A0A1A2A3A4RegisterFileA.

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.A1532-bits.S2.M2.L2.D2B0B1B2B3B4RegisterFileB.

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.B1532-bitsDataMemoryTheanswerisYESbuttherearelimitations.Toexchangeoperandsbetweenthetwosides,somecrosspathsorlinksarerequired.Whatisacrosspath?AcrosspathlinksonesideoftheCPUtotheother.Therearetwotypesofcrosspaths:Data

crosspaths.Address

crosspaths.Data

CrossPathsDatacrosspathscanalsobereferredtoasregisterfilecrosspaths.Thesecrosspathsallowoperandsfromonesidetobeusedbytheotherside.Thereareonlytwocrosspaths:onepathwhichconveysdatafromsideBtosideA,1X.onepathwhichconveysdatafromsideAtosideB,2X.Datacrosspathsonlyapplytothe.L,.Sand.Munits.Thedatacrosspathsareveryuseful,howevertherearesomelimitationsintheiruse.DataCrossPathsDataCrossPathLimitationsA2x.L1.M1.S1B1x<src><src><dst>(1) Thedestinationregistermustbeonsamesideasunit.(2) Sourceregisters-uptoonecrosspathperexecutepacketperside.Executepacket:groupofinstructionsthatexecutesimultaneously.eg:

ADD .L1x A0,B2,A2 MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8||

ADD .L1x A0,B0,A2|| MeansthattheSUBandADDbelongtothesamefetchpacket,thereforeexecutesimultaneously.A2x.L1.M1.S1B1x<src><src><dst>DataCrossPathLimitationseg:

ADD .L1x A0,B2,A2 MPY .M1x A0,B6,A9

SUB .S1x A8,B2,A8||

ADD .L1x A0,B0,A2NOTVALID!DataCrossPathLimitationsA2x.L1.M1.S1B1x<src><src><dst>Data

CrossPathsforbothsidesA2x.L1.M1.S1B1x<src><src><dst>.L2.M2.S2<dst><src><src>Addresscrosspaths.D1AAddrDataLDW.D1T1*A0,A5STW.D1T1A5,*A0(1) Thepointermustbeonthesamesideoftheunit.Loadorstoretoeitherside.D1A*A0BData1A5Data2B5DA1=T1DA2=T2LDW.D1T1*A0,A5LDW.D1T2*A0,B5StandardParallelLoads.D1AA5*A0BB5.D2Data1

*B0LDW.D1T1*A0,A5||LDW.D2T2*B0,B5DA1=T1DA2=T2ParallelLoad/Storeusingaddresscrosspaths.D1AA5*A0BB5.D2Data1

*B0LDW.D1T2*A0,B5||STW.D2T1A5,*B0DA1=T1DA2=T2Filltheblanks...Doesthiswork?.D1A

*A0B

.D2Data1

*B0LDW.D1__*A0,B5||STW.D2__B6,*B0DA1=T1DA2=T2NotAllowed!

Parallelaccesses:bothcrossorneithercross.D1A

*A0BB5B6.D2Data1

*B0LDW.D1T2*A0,B5||STW.D2T2B6,*B0DA2=T2