Verilog测试平台的简介（Testbenches）

Chapter15:IntroductiontoVerilogTestbenchesObjectivesInthissection,youwilllearnaboutdesigningatestbench:CreatingclocksIncludingfilesStrategicuseoftasksandconcurrentstatementsControllingandobservingthedesignReportingwarningsanderrorsTheSimulationEnvironmentThisisasimplifiedpictureoftheoverallsimulationenvironment.Thissectionconcentratesontestbenchdevelopmentstrategies.designsourcemodellibrariestestbenchsourcefileinput:stimulus,responsesimulatorcompilesimulatefileoutput:testpats,reportsCreatingClocksExample1Youcandefinetheclockineitherthedesignoritstestbench.Youcandefinetheclockeitherbehaviorallyorstructurally.Hereareexamplesofasymmetricclock:0103050clkregclk;alwaysbegin#10clk=1;#10clk=0;endregstart;nand#10(clk,clk,start);initialbeginstart=0;#10start=1;endCreatingClocksExample2Hereareexamplesofasymmetricclockwithdelayedstartup:0204060clkregclk;initialbegin#20clk=1;foreverbegin

#10clk=0;

#10clk=1;endendregstart;nand#10(clk,clk,start);initialbegin#10start=0;#10start=1;endCreatingClocksExample3Hereareexamplesofanasymmetricclockwithdelayedstartup:0204060clkregclk;initialbegin#20clk=1;foreverbegin

#5

clk=0;

#15clk=1;endendregstart;nand#(15,5)(clk,clk,start);initialbegin#5

start=0;#15start=1;endDesigningYourTestbenchYoucanmakeyourtestbenchassimpleorascomolexasyouwant.Acomolextestbenchwouldperformresponseberifivation“on-the-fly”.controldesigncontrolobservedesignsophisticatedtestbenchsimpletestbenchUsingIncludeFilesUse`includefilestoensureproject-wideconsistencyofcommonsource.`include“defines.inc”moduleclkgen(clk);outputclk;reg

clk;alwaysbegin#(`PERIOD/2)clk=0;

#(`PERIOD/2)clk=1;endinitialbegin#(`TIMEOUT)$display(“TIMEOUTERROR”);$finish;endendmodule//defines.inc`timescale1ns/10ps`definePERIOD20`defineTIMEOUT10000000UsingVerilogTasksUseVerilogtasksinyourtestbenchtoencapsulaterepeatedoperations.clkdata_validdata_readdata_readtaskcpu_read;begin#30data_valid=1;wait(data_read==1)；#20cpu_data=data_in;wait(data_read==0);#20cpu_data=8`hzz;#30data_valid=0;endendtaskUsingConcurrentStatementsUsefork-joinblocksinyourtestbenchtoconcurrentlyactivateparalleltasks.initializemonitorexecuteforkjoinmoduleinline_tb;//declarevariables//instantiatedesignsinitialbegininitialize_design;forkmonitor_data;monitor_error;monitor_timeout;run_test;joinendendmoduleApplyingStimulusSomecommonstimulusapplicationtechniquesinclude:In-linestimulus,appliedfromaninitialblockStimulusappliedfromalooporalwaysblockStimulusappliedfromanarrayofvectorsorintegersStimulusthatisrecordedduringonesimulationandplayedbackinanothersimulationIn-LineStimulusIn-linestimulushasthefollowingcharacteristics:YoulistthevariablesonlywhentheirvalueschangeYoucaneasilydefinecomplextimingrelationshipsbetweensignalsThetestbenchcanbecomeverylongfortestsofrealdesignsmoduleinline_tb;wire[7:0]results;

reg[7:0]data_bus,addr;DUTu1(results,data_bus,addr);initialfork#10addr=8`h01;#10data_bus=8`h23;#20data_bus=8`h45;#30addr=8`h67;#30data_bus=8`h89;#40data_bus=8`hAB;#45$finish;joinendmoduleStimulusFromLoopsStimulusappliedfromaloophasthefollowingcharacteristics:ForeachiterationyouassignanewstimulusvectorThetimingrelationshipsbetweensignalsareregularinnatureThetestbenchiscompactmoduleloop_tb;

wrie[7:0]response;

reg[7:0]stimulus;

regclk;integeri;DUTu1(response,stimulus);

inititialclk=0;alwaysbegin#10clk=1;#10clk=0;endinitialbeginfor(i=0;i<=255;i=i+1）@(negedgeclk)stimulus=i;#20$finish;endendmoduleStimulusFromArraysStimulusappliedfromanarrayhasthefollowingcharacteristics:YoucanloadthestimulusfromadatafiledirectlyintothearrayForeachiterationyoureadanewstimulusvectorfromthearraymodulearray_tb;wire[7:0]response;

reg[7:0]stimulus,stim_array[0:15];integeri;DUTu1(response,stimulus);initialbegin$readmemb(“datafile”,stim_array);for(i=0;i<=15;i=i+1);#20stimulus=stim_array[i]；#20$finish;endendmoduleVectorCaptureandPlaybackYoucancapturemanufacturingtestvectorsattheboundaryofadevicemodel.parameterperiod=20wire[7:0]response;reg[7:0]stimulus;DUTu1(response,stimulus);alwaysapply(stimulus);alwaysverify(response);taskcapture_tb;integerMCDR,MCDS;beginMCDR=$fopen(“response.dat”);if(!MCDR)$finish;MCDS=$fopen(“stimulus.dat”);if(!MCDS)$finish;forever@(posedgeclk)#(period-1)begin$fdisplayb(MCDR,“%b”,response);$fdisplayb(MCDS,“%b”,stimulus);end

endendtaskVectorCaptureandPlaybackYoucanplaybackthesavedstimulusandresponsevectors.parameterMAX_VECTOR=255;wire[7:0]response;reg[7:0]stimulus,stim_array[0:255],resp_arry[0:255];DUTu1(response,stimulus);taskplayback_tb;integerMCDR,MCDS,i;begin$readmemb(“response.dat”,resp_array);

$readmemb(“stimulus.dat”,stim_array);@(negedgeclk)//synchronizetoinactiveclockstimulus=stim_array[0];//apply1ststimulusfor(i=0;i<=MAX_VECTOR;i=i+1)@(negedgeclk)beginif(response!==resp_array[i])begin//checkresponse$display(“ERROR:responseis%b,shouldbe%b”,response,resp_array[i],“\nTESTFALLED”);$finish;endif(i==MAX_VECTOR)begin$display(“TESTPASSED”);$finish;endstimulus=stim_array[i+1];//applynextstimulusendendendtaskForcingStimulusYoucanmaketwotypesofproceduralcontinuousassignments:Youcanassignanddeassign

aregister

assign<lvalue>=<expression>

Thisoverridesanyproceduralassignmenttotheregisterinitialbegin

#10assigntop.dut.fsm1.state_reg=`init_state;

#20deassigntop.dut.fsm1.state_reg;

endYoucanforceandreleasearegisterornet

Thisoverridesalldriversofthesignalinitialbegin

#10forcetop.dut.counter.scan_reg.q=0;

#20releasetop.dut.counter.scan_reg.q;

endReportingWarningsandErrorsUsefileoutputsystemtaskstoreporterrorsandwarnings.Amoresophisticatedtestbenchwould:ReportanerrortoacentralizederrorhandlerModifythetestflow,dependingupontheerrorsencounteredMaintainerrorstatistics,andreportthemattheendofthetesttaskpar_err_task;forever@(posedgepar_err)err_handle_task(`NONFATAL,`PARITY);endtasktaskcor_err_task;forever@(posedgecor_err)err_handle_task(`NONFATAL,`CORRECTABLE）；endtaskSummaryInthissection,youlearnedaboutdesigningatestbench:CreatingclocksIncludingfilesStrategicuseoftas