stm32f05x培训day2cortex系列处理器

“8/16-bit”“16/32-bit”“32-bit/DSC” ArchitectureInstructionsetThumb,Thumb-2SystemInstructionsThumb+Thumb-Thumb+Thumb-2,DSP,SIMD,FPBus133IntegratedNumber1-32+1-240+1-240+Interrupt4Breakpoints,4/2/0,8/4/0,8/4/0,MemoryProtectionUnitIntegratedtraceoptionFaultRobustSingleCycleYesHardwareWICBitbandingSinglecycleFloatingpointBusAHBAHBLite,AHBLite,CMSIS 集成可配置的带跳转预测的31条AHB-Lite可配置的中断控制器（带优先级的最多32个中断不带内存保护单元可选的调试&M0–低成本的Cortex-M处理 和16高性能，只比标准Cortex-M3架构的性能低25- Cortex-M3作为旗舰MCUCortex-M0NORMALISEDTOCORTEX-CORTEX-M0ENERGYNORMALISEDTOCORTEX-NormalisedCortex-M3performanceandenergyefficiencyvs.Cortex-M0foralgorithmEnergyefficiencybasedonCortex-M3andCortex-M0processorpowerestimates–ONLYrefferstoCPUconsumption,similarenergyatsystem 其中46剩余101条指令可以传输8/16/32没有IT（如果-就-否则）大多数指令都是16位以节约空间，只有6条指令32跳转指令根据是否带条件及是否带返回占用1~4 用于调试的断点和观察点数目减少，分别占4个和2位节约JTAG引脚只支持串行单线调试(SWD)，但是使用同只有一条AHBlite Verysimple,linear4GByteaddressR15Allregistersare32-bitRegistersR0–R7(LowRegistersR8–R12(High3registerswithspecialStackPointer(SP)LinkRegister(LR)ProgramCounter(PC)xPSR:ApplicationandExceptionProgramstatusbitsandflagsInitialInitialMainHardBusUsageDebug…的个数1-2-3-Hard----------- SystemHandlerSysTick的优先级IRQ

优先级掩码寄存器 低优先级中断的执行被抢占 异常和中断处理特性 VerylowlatencyinterruptInterruptibleLDM/STMforlowinterruptAutomaticprocessorstatesaveandProvideslowlatencyISRentryandAllowshandlertobewrittenentirelyinTheCortex-M3processorintegratesanadvancedNestedVectoredInterruptController(NVIC)TheNVICsupportsupto32dynamicallyreprioritizable4programmablepriorityAllowsearlyprocessingofSupportsadvancedfeaturesfornextgenerationreal-timeTail-chainingofpendingLate-arrivalinterrupthandlingandpriorityboosting/ExceptionalControlCapabilitiesThroughIntegratedInterrupt VerylowlatencyinterruptInterruptibleLDM/STMforlowinterruptAutomaticprocessorstatesaveandProvideslowlatencyISRentryandAllowshandlertobewrittenentirelyinTheCortex-M3processorintegratesanadvancedNestedVectoredInterruptController(NVIC)TheNVICsupportsupto240dynamicallyreprioritizableAllowsearlyprocessingofSupportsadvancedfeaturesfornextgenerationreal-timeTail-chainingofpendingLate-arrivalinterrupthandlingandpriorityboosting/ExceptionalControlCapabilitiesThroughIntegratedInterrupt Interrupthandlingismicro-coded.NoinstructionProcessorstateautomaticallysavedtothestackoverthe{PC,xPSR,R0-R3,R12,Then,ISRreadytostartexecutingassoonasstackPUSHLatearrivinginterruptwillrestartISRprefetch,butstatesavingdoesnotneedtobeProcessorstateisautomaticallyrestoredfromtheTheninterruptedinstructionisexecuteduponcompletionofstackStackPOPcanbeinterrupted,allowingnewISRtobeimmediatelyexecutedwithouttheoverheadofstatesaving. Interrupthandlingismicro-coded.NoinstructionProcessorstateautomaticallysavedtothestackoverthedata{PC,xPSR,R0-R3,R12,Inparallel,ISRisprefetchedontheinstructionISRreadytostartexecutingassoonasstackPUSHLatearrivinginterruptwillrestartISRprefetch,butstatesavingdoesnotneedtobeProcessorstateisautomaticallyrestoredfromtheInparallel,interruptedinstructionisprefetchedreadyforexecutionuponcompletionofstackPOP.StackPOPcanbeinterrupted,allowingnewISRtobeimmediatelyexecutedwithouttheoverheadofstatesaving. 4242ISRISRISRin ISR

InterrupthandlingassemblercodeInterrupt2626cyclesfromIRQ1toISR1enteredUpto42cyclesifLSM42cyclesfromISR1exittoISR2entry16cyclestoreturnfromISR216cyclesfromIRQ1toISR1?cyclesfromISR1exittoISR2entry16cyclestoreturnfromISR2InterruptResponse-InterruptResponse-Tail42ISRISRISRinISR66

12cyclesfrom12cyclesfromIRQ1toISR1entered12cyclesifLSM6cyclesfromISR1exittoISR2entry12cyclestoreturnfromISR2Interrupt26cyclesfromIRQ1toISR1enteredUpto42cyclesifLSM42cyclesfromISR1exittoISR2entry16cyclestoreturnfromISR2

ISR

ISR ISR

?

ISR 26cyclestoISR2enteredImmediatelypre-empted26cyclestoISR2enteredImmediatelypre-emptedbyIRQ1andtakesafurther26cyclestoenterISR1.ISR1completesandthentakes16cyclestoreturntoISR2.StackpushtoISR2isinterruptedStackingcontinuesbutnewvectoraddressisfetchedinparallel?cyclesfromlate-arrivaltoISR1entry.Tail-chainintoISR2InterruptInterruptResponse–Late

ISR

ISR ISR

6

ISR 26cyclestoISR2enteredImmediatelypre-empted26cyclestoISR2enteredImmediatelypre-emptedbyIRQ1andtakesafurther26cyclestoenterISR1.ISR1completesandthentakes16cyclestoreturntoISR2.StackpushtoISR2isinterruptedStackingcontinuesbutnewvectoraddressisfetchedinparallel6cyclesfromlate-arrivaltoISR1Tail-chainintoISR 0Windowwatchdog1Powervoltagedetectorinterrupt(EXTIline2RTCinterrupts(combinedEXTIlines17,19&3Flashglobal4RCCglobal5EXTIline0&16EXTIline2&37EXTIline4to158RoutingInterface(Touch-Sensecontroller)9DMAchannel1DMAchannel2&3DMAchannel4&5ADCandCOMPinterrupts(ADCcombinedwithEXTI21&TIM1break,update,triggerandcommutationTIM1CaptureCompareTIM2globalTIM3global TIM6global>>ReservedforfutureTIM14globalTIM15globalTIM16globalTIM17globalI2C1globalinterrupt(combinedwithEXTII2C2globalSPI1globalSPI2globalUSART1globalinterrupt(combinedwithEXTIUSART2globalinterrupt(combinedwithEXTI>>ReservedforfutureCECglobalinterrupt(combinedwithEXTI>>Reservedforfuture 8bitMicrocontrollerlikepowermodeSLEEP“WaitforInterrupt”instructionstoenterlowpowermodeNomorededicatedcontrolregistersettingssequence“WaitforEvent”instructionstoenterlowpowermodeNoneedofInterrupttowake-upfromsleepRapidresumefromSLEEPonSleeprequestdoneininterruptLowpowermodeenteredoninterruptVeryfastwakeuptimewithoutcontextsaving(6DEEPLongdurationFromproductside:PLLcanbestoppedorshutsdownthepowertodigitalpartsofthesystemEnableslowpowerSystemTimerFlexiblesystem24-bitself-reloadingdowncounterwithendofcountinterrupt2configurableClockSuitableforRealTimeOSorotherscheduledSameSameasSTM32LandSTM32F2xxwithsomechangesSystem 最大封装（64引脚）上多达55个多功能双向GPIO引脚占有率相比STM32F1系列的80%更增加到）几乎所有GPIO都是5V容忍（ADC引脚除外GPIO连在AHB总线，使得最高翻转速度高达输出斜率可配置，高达端口A和B上的引脚配置可通过LCKR55个引脚都可以配置成外部中断（可同时使能16个来把MCU Port [Port [0:9Port [Port [PortC Port 1PortF[0:1]226PortF[4:PortF[6:2GPIO占芯片所有引脚的86

I/O

InputDataAlternateFunctionInputToInputData

OutputPushOutputPushPullwithPull-upOutputPushPullwithPull-downOutputOpenOutputOpenDrainwithPull-upOutputOpenDrainwithPull-downAlternateFunctionPushPullAlternateFunctionPPPull-upAlternateFunctionPPPull-downAlternateFunctionOpenDrainAlternateFunctionODPull-upAlternateFunctionODPull-downInput

0TriggerInput

VDDorPull-Pull-Pull-I/O

InputwithPull- InputwithPull- Analog

BitSet/ResetReadBitSet/ResetOutputDataFromOn-chipPeripheralsAlternateOutputData

OpenDrain*Inoutputmode,theI/OspeedisconfigurablethroughOSPEEDRregister:2MHz,10MHzor50MHz

(1)VDD_FTisapotentialspecifictofive-volttolerantI/Osanddifferentfrom AF0(SPI1_MISO)AF1(TIM3_CH1)AF2PinxAF7I/OPortLogicDataAlternateFunctionIN/OUTPP_EN/DATA_OUTTrue输入/输入/模 /输出速度不超过2MHz，最大负载30 所有备份域端口，都是标准3.3V容忍【TCPC13PC14/15ADC占用端口，也是3.3V容忍【TTaPA0~PA7PB0~PB1PC0~PC5I2C1端口支持1MHz超快速总线【FTfPB6~7PB8~9其余端口都是5V容忍【FTHowmanyI/OsandportsthereareintheSTM32F0xxmicrocontrollerListalltheI/OconfigurationHowmanyExternalinterruptsandWake-uppins,existintheSTM32F0xxMMSGroup 开关开关1Cs23Chargecycle(Cx45Transfercycle(chargetransferredtoCs)67Cx

电极上的待测电容Cx向采样电容Cs电荷转移过程中个模拟开关是硬件做在GPIOChargeChargeCharge

每个电极上串联一个Rs用来提高ESD健壮性（通常

I/Ocontrol

Group

触摸感应控制器特性 每个I/O 触摸感应控制器特性 电荷转移频率可配置（最高每个I/O该触摸感应控制器搭配STMTouchtouchsensingfirmwarelibrary使用 STMTouchTouchSensing固件 校准、环境控制(ECS) 333333322333333330 只要使能了TSC即使该引脚处于GPIOHowmanychannelsaresupportedbySTM32F0xxmicrocontrollerCouldyoubrieflydescribethechargetransferacquisitionWhatistheimpactofatouchonthenumberofchargetransferWhattypeofsensorsaresupportedbytheSTMTouchtouchsensinglibrarySimilarsetasSTM32F100xSimilarsetasSTM32F100xTIMERSTimersMax4+16-484+4+UPonly01UPonly1+UPonly2+UPonly1+UPonly1+TimersTimerTIM15TIM2TIM3TIM17TIM1TIM15TIM3TIM14TIM1TIM2TIM15TIM14TIM2TIM3TIM16TIM17BREAKTIM1:COMP1,COMP2,HardFault,RAMparity,PVD,CSS,TIM15,TIM16,TIM17:HardFault,RAMparity,PVD,CSS,IRHowmany32-bittimersareembeddedinWhatarethepossiblebreakinputsexcepttheTIMx_BKINWhichtimersareusedforIRtransmitterNewIPcomingNewIPcomingSERIALPERIPHERALINTERFACE(SPI/I2S)SPI 32时钟极性、相位以及数据位序（MSB或LSB）硬件CRC（用于8位或16位长度的帧能触发中断的标志（TxE、RxNE、MODF、OVR、CRCERR、可配置的时钟速度fPCLK/2，高达BSY自动发送CRC的DMA传输（独立的发送、接收请求 更加灵活的片选信号NSS数据帧长度可配置：4位~16能分别触发DMA请求，各占4字节的发送FIFO和接收 数据帧长度可设置：4位~16数据位序可设置：MSB或 从设备的身份由MSTR@CR1=0 主设备的身份由MSTR=1NSSNSS 只能用于标准SPI 片选和时钟信号都由硬件管理，CPHA和CPOL该模式下SSM、SSI、SSOE、NSSP 至少需要3条线：MISO、MOSI和SCK（NSS可选 主发送/从接收：MOSI，MISO可做GPIO主接收/从发送：MISO，MOSI可做GPIO主设备只接收：一旦使能SPI!! 数据线：主设备的MOSI接从设备的当前的通信方向由BIDIOE方向的改变，需要关闭SPI 送数据，时钟信号会自动送出)* 门限值设置@FRXTH：达到8位或16位就触发RxNE事 FIFO当前的水平可通过FRLVL[1:0]门限值固定：包含的数据≤2个字节就触发 FIFO当前的水平可通过FTLVL[1:0] 对FIFO的访问宽度：8FTLVL[1:0],FRLVL[1:0],TxE,不超过8 当数据帧长度不超过1个字节，可通过对SPI_DR16位读写操作同时访问处理2 数据帧长度=4，数据位序=MSB，接收FIFO门限=2 等待发送FIFO为空等待最后一个数据发送完成读取所有收到的数据，直到接收FIFO为空关闭SPI在特殊时间窗口内关闭只接收模式@RXONLY=0等待最后一个数据传输结束读取所有收到的数据，直到接收FIFO为空关闭SPI (1)置位SPE使能(2)往SPI_DR(3(3)等待TxE(4)等待RxNE置位后从SPI_DR(5)等待RxNE(6)等待TxE置位后，再等待BSY清零，再关闭 BIDIMODE=0RXONLY(1)置位SPE使能(2)往SPI_DR(3(3)等待TxE重复以上步骤，直到所有数据都写入(4)等待TxE置位后，再等待BSY清零，再关闭

各自的使能控制各自的触发条件@TxE/RxNEDMA发送/接收通道的PSIZE=16数据帧长度不超过1

数据自动 发送、接收有各自的CRC统一的使能控制只提供CRC8和CRC16可编程的CRC奇数多项式CRC 发送：把最后一个数据写进SPI_DR后软件置位，来把TXCRCR的值放入发送自动完成对CRC的发送和接收，软件无需操作DMA发送通道：CNDTR=数据帧个数(或其一半DMA接收通道：CNDTR=数据帧个数(或其一半)+1(或 NSSpinneedstobekeptlowbetweendataphaseandCRCphaseVs.CRCcalculationtakesplaceevenifahighlevelonNSSpin 以下3关闭只接收模式@RXONLY=数据阶段结束，进入CRC阶段@CRCNEXT=

发送FIFO中现有数据少于或等于16位，硬件置位一旦发送FIFO中数据多于16位，硬件复位TxE接收FIFO门限CPU/DMA可以从接收FIFO读数据了（读以上情况不满足时，硬件复位RxNE 总线忙Busy以下情况也会硬件复位BSY 据和RXCRCR中计算出来 1设置波特率1设置波特率2设置时钟空闲电平和相位@CPOL&3设置通信模式@RXONLY&BIDIOE&45设置数据位序6根据应用配置片选管理方案@SSM&SSI&789如果使用DMA，配置LDMA_TX&WhatisamaximumSPIWhendatapackedmodeisWhatshouldbeinlinewhenaccesstheDoesamastertakeanycareoftheNSSsignallevelifitismanagedbySW?Howmanybytes(maximum)canbestoredintoTxFIFOtillitisfullwhen8-bitaccessisused?WhatshouldprecedebeforeSPIisINTER-INTEGRATEDCIRCUITINTERFACE(I2C) 兼容I2C3.0（V3版本硬件支持兼容硬件处理I2C总线特有的时序、协议、仲裁 被寻址时可把MCU 对SMBus20mA HSI（ 可滤除脉宽在0~15个tI2C_CLK之间的毛刺 域tPRESEC=(PRESC+1)*ttSCLDEL=(PRESC+1)*ttSDADEL=(PRESC+1)*ttSCLH=(PRESC+1)*ttSCLL=(PRESC+1)*t 会插入一个延迟，即tSDADEL数据输出的延时还要加上同步时间，即tSYNC1 来让数据有一定的建立时间，即tSCLDEL调整tSCLDEL来满足I2C协议中指定的tSCLDEL≥SCLDEL≥{[tr(max)+tSU;DAT(min)]/tPRESC}-tPRESC=(PRESC+1)*t-50ns、-260ns definitionoftimingforF/Stf:falltimeofSDA&SCL tr:risetimeofSDA&SCLtLOW:lowperiodofSCL tHIGH:highperiodofSCLtHD;DAT:holdtimeofdata tSU;DAT:setuptimeofdatatHD;STA:holdtimeofSTART tsu;STA:setuptimeofSTARTtSU;STP:setuptimeofSTOPtBUF:busfreetimebetweenaSTOPand SCL拉低后经过tSYNC1，I2C才内部检测到低电平，再SCL拉高后经过tSYNC2，I2C才内部检测到高电平，再tSCL=tSYNC1+tSYNC2+{[(SCLH+1)+(SCLL+1)]*(PRESC+1)*tSCLfallingedgeinternal Byte

OFF：ON：主设备总是开启；

【rw

表示NBYTE

【rw

载K*红

示只针对主*蓝色表示只针对从 个字节+STOP0100个字节+11备字节超过100x11EasyMastermodeForpayload<=255bytes:only1writeactionneeded!!(apartdatard/wr)I2Cx_CR2iswrittenw/: START=1SADD:slaveRD_WRN:transferNBYTES=N:numberofbytestobeAUTOEND=1:STOPautomaticallysentafterN0:SoftwareendEndoftransferSWcontrolafterNBYTESdatatransferTCflagisset.InterruptifTCisclearedwhenSTARTorSTOPissetbyIfSTART=1:RESTARTconditionis1:AutomaticendSTOPconditionsentafterNBYTESdataDatatransfermanagedbyInterrupts(TXIS/RXNE)orEasytouseeventForpayload>255:inaddition,RELOADmustbesetin0:NoNBYTESdatatransferisfollowedbySTOPor1:ReloadNBYTESisreloadedafterNBYTESdatatransfer(datatransferwillcontinue):TCRflagisset.InterruptifTCRisclearedwhenI2Cx_CR2iswri\enw/AUTOEND=0hasnoeffectwhenRELOADisSlaveBydefault:I2CslaveusesclockstretchingThiscanbedisabledbysettingReception:AcknowledgecontrolcanbedoneonselectedbytesinSlaveByteControl(SBC)modewithRELOAD=1SBC=1enablestheNBYTEScounterinslavemode(TxandRxSBC=1isallowedonlywhen0:SlaveByteAllreceivedbytesare1:SlaveByteControlIfRELOAD=1,afterNBYTESdataaretransferredTCRset&SCLstretchedbeforeACKpulseinTCRisclearedwhenI2Cx_CR2iswri\enw/ifI2Cx_CR2/NACK=1:receivedbyteisNOT 字节应答控制 使能可以配置为7位（默认）或10位地址@使能对广播地址地址应答的控制广播地址 NOSTRETCH 第8个时钟脉冲后会把移位寄存器中的内容拷贝到 SBC=1&RELOAD=1& TXDR为空时，置位TXIS每发送一个字节会收到ACK，且置位如果收到NACK如果收到STOPSSANAAA时钟延展&1stdata>>EV1(ADDRISR):时钟自动延展；查看ADDCODE和DIR，软>>EV2(TXIS):时钟自动延展；软件写入data1>>EV3(TXIS):data1开始传输时，TXIS再次置位，软件写入>>EV4(TXIS):data1和data2都发送完成后，TXDR中没有新数>>EV5(TXIS):data3开始传输时，TXIS再次置位，软件可以写时钟延展&without1stdata>>EV1(ADDRISR):时钟自动延展；查看ADDCODE和DIR>>EV2(TXIS):data1是事先放在TXDR中的；当它开始传输时，>>EV3(TXIS):data1和data2都发送完成后，TXDR中没有新数据>>EV4(TXIS):data3开始传输时，TXIS再次置位，软件可以写时钟不延展时钟不延展&without1stdata>>EV1(XISR):时钟不延展；data1要事先放在>>EV2(TXIS):data1开始传输时，TXIS再次置位(此次EV2)，软>>EV3(TXIS):data2开始传输时，TXIS再次置位(此次EV3)，软>>EV4(TXIS):data3开始传输时，TXIS再次置位，软件可以写>>EV5(STOPF):可以再次置位TXE和TXIS来flushTXDR；软件复；图标：主设备产生的从设备产生的；时钟延； 从设备要发送的第一个数据要事先放在TXDR从设备要发送的第一个数据可以事先放在TXDR或者在ADDR中断中把第一个数据写入但是要在STOPF如果下次传输开始时STOPF 数据放到RXDR置位RXNE时钟不支持延展出现溢出错误时，硬件自动回复从设备启动字节应答模式时（SBC=1&RELOAD=1&NBYTE=1），每收到一个字节数据时钟发生延展，可由收到STOP位，置位STOPFSPAAAA >>>>EV1(ADDRISR):时钟自动延展；查看ADDCODE和>>EV2(RxNE):2个数据data1和data2都已经收到，时钟自>>EV3(RxNE):软件读取>>EV4(RxNE):软件读取>>EV1(RxNE):软件读取>>EV2(RxNE):软件读取>>EV3(RxNE):软件读取 设置寻址的从设备地址@设置从设备的地址模式，7位或10配置传输方向传输字节数一旦检测到总线空闲(BUSY=0)，再经过规范要求的t该主设备发送的地址也出现在总线上后硬件复位= 【初始化&启动】HEAD10R=1；置位 TXDR为空时，置位TXIS每发送完一个字节会收到ACK，且置位如果收到NACK位（从设备启动字节应答控制SPAAAA

NBYTE=AUTOEN