基于BASYS2的简易数字钟

../***********************************verilog*************************************/moduleclock_final(clk,clr,switch,ad,adj,o_seg,a); inputclk,clr,switch,ad; input[3:0]adj;// output[2:0]led;//led灯 output[6:0]o_seg;//7段数码管 output[3:0]a;//扫描输出 reg[6:0]segs;//数码管存放器 reg[3:0]a; reg[15:0]temp;//显示过程的中间变量 wire[23:0]t;//走时模式和校时模式临时变量 wireen0,enp1,enp2,enp3,enp4,enp5,cp1hz,cp,out_500hz;//switch-N3转换信号分两个屏一个是小时/分钟，一个是分钟/秒//clr-E2清零信号//adj[3]控制小时的十位设置//adj[2]控制小时的个位设置//adj[1]控制分钟的十位设置//adj[0]控制分钟的个位设置 initialbegin a=4'b1110; end//初始化 assign cp=cp1hz,//判断ad是否等于1，如果等于，cp就输出cp10hz否那么就输出cp1hz, en0=(~ad)|(switch&adj[0]), enp1=~ad"(t[3:0]==4'd9):(adj[1]&switch), enp2=~ad"(t[7:4]==4'd5)&(t[3:0]==4'd9):(adj[0]&switch==0), enp3=~ad"(enp2&(t[11:8]==4'd9)):(adj[1]&switch==0), enp4=~ad"(enp3&(t[15:12]==4'd5)):(adj[2]&switch==0), enp5=~ad"(enp4&((t[19:16]==4'd9)|(t[23:20]==4'b0010&t[19:16]==4'd3))):(adj[3]&switch==0), o_seg=segs;in50MHz_out1Hzu0(clk,cp1hz);//输出频率1HZ in50MHz_out_8MHzu7(clk,out_500hz);//输出500HZ counter10u1(en0,clr,cp,t[3:0]);//second个位计数 counter6u2(enp1,clr,cp,t[7:4]);//second十位计数 counter10u3(enp2,clr,cp,t[11:8]);//minutes个位计数 counter6u4(enp3,clr,cp,t[15:12]);//minutes十位计数 counter10_hu5(enp4,clr,cp,t[19:16],t[23:20]);//hours个位计数 counter3u6(enp5,clr,cp,t[23:20]);//hours十位计数// //// always(ad)begin//显示模式选择// if((~ad))begintemp[15:0]<=t1[15:0];temp[31:16]<=t1[23:8];end// elsebegintemp[15:0]<=t;temp[31:16]<=t[23:8];end// end always(posedgeclk) begin if(switch==1'b0) temp<=t[23:8]; elseif(switch==1'b1) temp<=t[15:0]; endalways(posedgeout_500hz) begin if(a==4'b1110) a<=4'b1101;//M13 elseif(a==4'b1101) a<=4'b1011;//J12 elseif(a==4'b1011) a<=4'b0111;//F12 else a<=4'b1110;//K14endalways(posedgeclk) //数码管显示译码if(switch==1'b0) begin if(a==4'b1110)//K14begin case(temp[3:0]) 4'd0:segs<=7'b1000000;//0 4'd1:segs<=7'b1111001;//1 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; 4'd6:segs<=7'b0000010; 4'd7:segs<=7'b1111000; 4'd8:segs<=7'b0000000; 4'd9:segs<=7'b0010000;//9 defaultsegs<=7'b1111111; endcase end elseif(a==4'b1101)//M13 begin case(temp[7:4]) 4'd0:segs<=7'b1000000; 4'd1:segs<=7'b1111001; 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; defaultsegs<=7'b1111111; endcaseend elseif(a==4'b1011) begin case(temp[11:8])//hours个位 4'h0:segs<=7'b1000000; 4'h1:segs<=7'b1111001; 4'h2:segs<=7'b0100100; 4'h3:segs<=7'b0110000; 4'h4:segs<=7'b0011001; 4'h5:segs<=7'b0010010; 4'h6:segs<=7'b0000010; 4'h7:segs<=7'b1111000; 4'h8:segs<=7'b0000000; 4'h9:segs<=7'b0010000; 4'ha:segs<=7'b0001000; defaultsegs<=7'b1111111; endcase end elseif(a==4'b0111)begin case(temp[15:12])//hours十位 4'h0:segs<=7'b1000000; 4'h1:segs<=7'b1111001; 4'h2:segs<=7'b0100100; defaultsegs<=7'b1111111; endcaseendendelseif(switch==1)begin if(a==4'b1110) begin case(temp[3:0]) 4'd0:segs<=7'b1000000; 4'd1:segs<=7'b1111001; 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; 4'd6:segs<=7'b0000010; 4'd7:segs<=7'b1111000; 4'd8:segs<=7'b0000000; 4'd9:segs<=7'b0010000; defaultsegs<=7'b1111111; endcase end elseif(a==4'b1101) begin case(temp[7:4]) 4'd0:segs<=7'b1000000; 4'd1:segs<=7'b1111001; 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; // 4'd6:segs<=7'b0000010; // 4'd7:segs<=7'b1111000; // 4'd8:segs<=7'b0000000; // 4'd9:segs<=7'b0010000; defaultsegs<=7'b1111111; endcase endelseif(a==4'b1011) begin case(temp[11:8]) 4'd0:segs<=7'b1000000; 4'd1:segs<=7'b1111001; 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; 4'd6:segs<=7'b0000010; 4'd7:segs<=7'b1111000; 4'd8:segs<=7'b0000000; 4'd9:segs<=7'b0010000; defaultsegs<=7'b1111111; endcase end elseif(a==4'b0111) begin case(temp[15:12]) 4'd0:segs<=7'b1000000; 4'd1:segs<=7'b1111001; 4'd2:segs<=7'b0100100; 4'd3:segs<=7'b0110000; 4'd4:segs<=7'b0011001; 4'd5:segs<=7'b0010010; defaultsegs<=7'b1111111;endcase endend endmodule/***************分频模块***********************************************///分频模块1Hz modulein50MHz_out1Hz(in_50MHz,out_1Hz); inputin_50MHz; outputout_1Hz; regout_1Hz; reg[31:0]t;//usettocount always(posedgein_50MHz) beginif(t<32'd24999999)//计数到24999999 begin t<=t+1'B1; end elsebegint<=32'b0; out_1Hz<=~out_1Hz;//频率为1HZ end end endmodule modulein50MHz_out_8MHz(in_50MHz,out_500hz); inputin_50MHz; outputout_500hz; regout_500hz; reg[31:0]t;//usettocount always(posedgein_50MHz) beginif(t<32'd50000)// begin t<=t+1'B1; end elsebegint<=32'b0; out_500hz<=~out_500hz;//频率为1HZ end end endmodule//counter10(0~9) modulecounter10(en,clr,clk,q); inputen,clr,clk; output[3:0]q; reg[3:0]q; always(posedgeclk) begin if(clr)q<=4'd0;//clr=0时，清零 elseif(~en)q<=q;//EN=0，暂停计数 elseif(q==4'b1001)q<=4'b0000; elseq<=q+1;//计数器加1 end endmodule//counter10〔时针个位〕 modulecounter10_h(en,clr,clk,q,p); inputen,clr,clk; input[3:0]p; output[3:0]q; reg[3:0]q; always(posedgeclk) begin if(clr)q<=4'd0;//clr=0时，清零 elseif(~en)q<=q;//EN=0，暂停计数 elseif(p==4'b0010&q==4'b0011)q<=4'b0000; elseif((q==4'b1001)&~(p==4'b0010))q<=4'b0000; elseq<=q+1;//计数器加1 end endmodule/*****************计数模块********************************************///counter6.v(0~5) modulecounter6(en,clr,clk,q); inputen,clr,clk; output[3:0]q; reg[3:0]q; always(posedgeclk) begin if(clr)q<=4'b0000;//clr=0，清零 elseif(~en)q<=q;//EN=0，暂停计数 elseif(q==4'b0101)q<=4'b0000; elseq<=q+1'b1;//计数器增1 end endmodule//counter3(0~2) modulecounter3(en,ncr,clk,q); inputen,ncr,clk; output[3:0]q; reg[3:0]q; always(posedgeclk) begin if(ncr)q<=4'b0000;//NCR=0，同步清零 elseif(en==0)q<=q;//EN=0，暂停计数 elseif(q==4'd2) q<=4'b0000; elseq<=q+1'b1;//计数器增1 end Endmodule/***********************************ucf***************************************/NET"clk" LOC=B8|IOSTANDARD="LVCMOS33";NET"ad" LOC=G12|IOSTANDARD="LVCMOS33";NET"switch" LOC=N3|IOSTANDARD="LVCMOS33";NET"clr" LOC=E2|IOSTANDARD="LVCMOS