计算机组成与结构

ECE313Fall2006Lecture20-Memory1/89Roadmapfortheterm:majortopicsOverview/AbstractionsandTechnologyInstructionsetsLogic&arithmeticPerformanceProcessorImplementationSingle-cycleimplemenatationMulticycleimplementationPipelinedImplementationMemorysystems 3Input/Output

ECE313Fall2006Lecture20-Memory2/89Outline-MemorySystemsOverview 3MotivationGeneralStructureandTerminology(术语)MemoryTechnologyStaticRAMDynamicRAMDisksCacheMemoryVirtualMemoryECE313Fall2006Lecture20-Memory3/89MemorySystems-theBigPictureMemoryprovidesprocessorwithInstructionsDataProblem:memoryistooslowandtoosmallControlDatapathMemoryProcessorInputOutputInstructionsData“FiveClassicsComponents”PictureECE313Fall2006Lecture20-Memory4/89MemoryHierarchy-theBigPictureProblem:memoryistooslowandtoosmallSolution:memoryhierarchy（层次）-分层存储器FastestSlowestSmallestBiggestHighestLowestSpeed:Size:Cost:ControlDatapathSecondaryStorage(Disk)ProcessorRegistersL2Off-ChipCacheMainMemory(DRAM)L1On-ChipCacheECE313Fall2006Lecture20-Memory5/89WhyHierarchyWorksTheprincipleoflocality（局部性原理）Programsaccessarelativelysmallportionoftheaddressspaceatanyinstantoftime.-在任一瞬间，程序只访问地址空间中的一小部分

Temporallocality:recentlyaccesseddataislikelytobeusedagainSpatiallocality:datanearrecentlyaccesseddataislikelytobeusedsoonResult:theillusion(幻想)oflarge,fastmemoryAddressSpace02n-1ProbabilityofreferenceECE313Fall2006Lecture20-Memory6/89MemoryHierarchy-Speedvs.SizeControlDatapathSecondaryStorage(Disk)ProcessorRegistersL2Off-ChipCacheMainMemory(DRAM)L1On-ChipCache0.5-255,000,000(5ms)Speed(ns):80-250<1KSize(bytes):>100G<16G<16M0.25-0.5ECE313Fall2006Lecture20-Memory7/89MemoryHierarchy–Terminology术语ProcessorBlocksofDataHit:DatainUpperLevelMiss:DatanotinUpperLevel数据复制每次只在两个相邻层次间进行ECE313Fall2006Lecture20-Memory8/89存储器层次结构的几个术语Hit:处理器需要的数据出现在高层的某个块中(greenblock)HitRate:thefractionofmemoryaccessesthat“hit”HitTime:timetoaccesstheupperlevel

(timetodeterminehit/miss+accesstime)Miss:datamustberetrievedfromblockinlowerlevel(orangeblock)缺失率MissRate=1-(HitRate)MissPenalty:Timetoreplaceblockinupperlevel+TimetodeliverdatatotheprocessorHitTime<<MissPenaltyandHitRate>>MissRateECE313Fall2006Lecture20-Memory9/89TypicalMemoryHierarchy-DetailsRegisters-Small,fasteston-chipstorageManagedbycompilerandrun-timesystemCache-Small,faston-chipstorageAssociativelookup-managedbyhardwareMemory-Slower,Largeroff-chipstorageLimitedsize<16Gb-managedbyhardware,OSDisk-Slowest,Largestoff-chipstorageVirtualmemory–simulatealargememoryusingdisk,hardware,andoperatingsystemFilestorage-storedatafilesusingoperatingsystemECE313Fall2006Lecture20-Memory10/89存储器系统影响计算机的许多方面用于构造存储器系统的概念影响到计算机的许多方面，如：OS对存储器和I/O如何管理编译器如何生成代码应用程序如何使用计算机性能评估因而，设计人员花费了相当的精力开发复杂的机制以提高存储器系统的性能本章进行了大量抽象和简化ECE313Fall2006Lecture20-Memory11/89Outline-MemorySystemsOverview MotivationGeneralStructureandTerminologyMemoryTechnology 3StaticRAM DynamicRAMCacheMemoryVirtualMemoryECE313Fall2006Lecture20-Memory12/89MemoryTypesStaticRAMStorageusinglatchcircuits(门锁电路）Valuessavedwhilepoweron

DynamicRAMStorageusingcapacitors（电容）Valuesmustberefreshedbitbitword/rowselect1001word/rowselectbitCECE313Fall2006Lecture20-Memory13/89Tradeoffs-Staticvs.DynamicRAMStaticRAM(SRAM)-usedforL1,L2cacheFast-0.5-25nsaccesstime(lessforon-chip)Larger,MoreExpensiveHigherpowerconsumptionDynamicRAM(DRAM)-usedforPCmainmemorySlower-80-250nsaccesstime*Smaller,CheaperLowerpowerconsumptionECE313Fall2006Lecture20-Memory14/89DRAMOrganizationRowDecoderColumnSelector/Latch/IORowAddressColumnAddress/RAS/CASDATARowSelectLineBit(data)LineECE313Fall2006Lecture20-Memory15/8900010011DRAMReadOperationRowDecoderColumnSelector/Latch/IORowAddressColumnAddress/RAS/CASDATAECE313Fall2006Lecture20-Memory16/89DRAMTrends（趋势）RAMsize:4Xevery3yearsRAMspeed:2Xevery10years

DRAMYear Size CycleTime1980 64Kb 250ns1983 256Kb 220ns1986 1Mb 190ns1989 4Mb 165ns1992 16Mb 145ns1995 64Mb 120ns1997? 128Mb ??ns1999? 256Mb ??ns1980-1995Sizechange:

1000:1!1980-1995Speedchange:

2:1!ECE313Fall2006Lecture20-Memory17/89TheProcessor/MemorySpeedGapDRAM9%/yr.(2X/10yrs)110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformanceGap:

(grows50%/year)PerformanceTime“Moore’sLaw”ECE313Fall2006Lecture20-Memory18/89定位导致速度差异的原因

AddressingtheSpeedGapLatencydependsonphysicallimitationsBandwidthcanbeincreasedusing:并行Parallelism–transfer(传输)morebits/wordBursttransfers-transfersuccessivewordsoneachcycle在每个周期中传输连续的机器字So...usebandwidthtosupportmemoryhierarchy(层次)!UsecachetosupportlocalityofreferenceDesignhierarchytotransferlarge

blocksofmemoryECE313Fall2006Lecture20-Memory19/89CurrentDRAMPartsSynchronous同步的DRAM(SDRAM)-clockedtransferofburstsofdatastartingataspecificaddressDouble-DataRateSDRAM-transfertwobits/clockcycleQuad（方形）-DataRateSDRAM-transferfourbits/clockcycleRambusRDRAM-High-speedinterfaceforfasttransfersCurrentPCsusesomeformofSDRAM/RDRAMSDRAMw/PC100orPC133memorybusRDRAMw/PC800memorybusECE313Fall2006Lecture20-Memory20/89MemoryConfigurationinCurrentPCsProcessorSystemControllerL1CacheMainMemory(DRAM)L2/L3Cache(SRAM)(I/OBus)ECE313Fall2006Lecture20-Memory21/89主存是以存储芯片为基本单位构成用16K×1位的存储芯片组成64K×8位的存储器

32片当地址为65535时，此8片的片选有效8片16K×1位8片16K×1位8片16K×1位8片16K×1位ECE313Fall2006Lecture20-Memory22/890,015,015,70,7

读/写控制电路

地址译码器

字线015…………16×8矩阵…………07D07D位线读/写选通A3A2A1A0……存储芯片的译码驱动方式-线选法00000,00,7…0……07……D07D读/写选通ECE313Fall2006Lecture20-Memory23/89A3A2A1A0A40,310,031,031,31

Y地址译码器

X地址译码器

32×32矩阵……A9I/OA8A7A56AY0Y31X0X31D读/写……存储芯片的译码驱动方式-重合法00000000000,031,00,31……I/OD0,0读ECE313Fall2006Lecture20-Memory24/89静态RAM(SRAM)基本电路A´触发器非端1T4T~触发器5TT6、行开关7TT8、列开关7TT8、一列共用A

触发器原端T1~T4T5T6T7T8A´A写放大器写放大器DIN写选择读选择DOUT读放位线A位线A´列地址选择行地址选择T1~T4ECE313Fall2006Lecture20-Memory25/89A´T1

~T4T5T6T7T8A写放大器写放大器DIN写选择读选择读放位线A位线A´列地址选择行地址选择DOUT静态RAM基本电路的读

操作行选

T5、T6开T7、T8开列选读放DOUTVAT6T8DOUTECE313Fall2006Lecture20-Memory26/89T1~T4T5T6T7T8A´ADIN位线A位线A´列地址选择行地址选择写放写放读放DOUT写选择读选择静态RAM基本电路的写

操作行选T5、T6开两个写放DIN列选T7、T8开（左）

反相T5A´（右）

T8T6ADINDINT7ECE313Fall2006Lecture20-Memory27/89静态RAM芯片举例-Intel2114存储容量1K×4位......I/O1I/O2I/O3I/O4A0A8A9WECSCCVGNDIntel2114这些存储元件应该如何排列？才能给出一个存储单元的地址而一次读出4位信息。1、立体；2、平面ECE313Fall2006Lecture20-Memory28/89Intel2114RAM矩阵(64×64)读A3A4A5A6A7A8A0A1A2A915…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS第一组第二组第三组第四组ECE313Fall2006Lecture20-Memory29/8915…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS第一组第二组第三组第四组0000000000Intel2114RAM矩阵(64×64)读ECE313Fall2006Lecture20-Memory30/89第一组第二组第三组第四组15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000Intel2114RAM矩阵(64×64)读150311647326348…………ECE313Fall2006Lecture20-Memory31/89第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………ECE313Fall2006Lecture20-Memory32/8915…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读0163248CSWEECE313Fall2006Lecture20-Memory33/89第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECSCSWE150311647326348…………01632480000000000…………ECE313Fall2006Lecture20-Memory34/89第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000…………CSWE150311647326348…………0163248ECE313Fall2006Lecture20-Memory35/89第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000…………CSWE150311647326348…………0163248读写电路读写电路读写电路读写电路ECE313Fall2006Lecture20-Memory36/89第一组第二组第三组第四组Intel2114RAM矩阵(64×64)读15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000…………CSWE读写电路读写电路读写电路读写电路150311647326348…………0163248I/O1I/O2I/O3I/O4ECE313Fall2006Lecture20-Memory37/89A3A4A5A6A7A8A0A1A2A915…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写ECE313Fall2006Lecture20-Memory38/8915…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS第一组第二组第三组第四组0000000000Intel2114

RAM矩阵(64×64)写ECE313Fall2006Lecture20-Memory39/89第一组第二组第三组第四组15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000Intel2114

RAM矩阵(64×64)写150311647326348…………ECE313Fall2006Lecture20-Memory40/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………WECSECE313Fall2006Lecture20-Memory41/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4ECE313Fall2006Lecture20-Memory42/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4读写电路读写电路读写电路读写电路ECE313Fall2006Lecture20-Memory43/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4读写电路读写电路读写电路读写电路ECE313Fall2006Lecture20-Memory44/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写I/O1I/O2I/O3I/O415…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码WECS0000000000150311647326348…………读写电路读写电路读写电路读写电路I/O1I/O2I/O3I/O4WECSECE313Fall2006Lecture20-Memory45/89第一组第二组第三组第四组Intel2114

RAM矩阵(64×64)写I/O1I/O2I/O3I/O415…031…1647…3263…48150311647326348读写电路读写电路读写电路读写电路……………………0163015……行地址译码列地址译码WECS0000000000150311647326348…………I/O1I/O2I/O3I/O4读写电路读写电路读写电路读写电路WECS0163248ECE313Fall2006Lecture20-Memory46/89DD预充电信号读选择线写数据线写选择线读数据线VCgT4T3T2T11动态RAM(DRAM)-基本单元电路读出与原存信息相反读出时数据线有电流为“1”数据线CsT字线DDV010110写入与输入信息相同写入时CS充电为“1”放电为“0”T3T2T1T无电流有电流ECE313Fall2006Lecture20-Memory47/89单元电路读写控制电路列地址译码器………读选择线写选择线D行地址译码器001131311A9A8A7A6A531A4A3A2A1A0刷新放大器写数据线读数据线……………0…动态RAM芯片举例-三管动态RAM芯片(Intel1103)读00000000000D…00单元电路读写控制电路ECE313Fall2006Lecture20-Memory48/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0…三管动态RAM芯片(Intel1103)写ECE313Fall2006Lecture20-Memory49/8911111三管动态RAM芯片(Intel1103)写A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0…ECE313Fall2006Lecture20-Memory50/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0…11111…三管动态RAM芯片(Intel1103)写ECE313Fall2006Lecture20-Memory51/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……0100011111三管动态RAM芯片(Intel1103)写ECE313Fall2006Lecture20-Memory52/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……1111110100011三管动态RAM芯片(Intel1103)写ECE313Fall2006Lecture20-Memory53/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……D11111010001三管动态RAM芯片(Intel1103)写ECE313Fall2006Lecture20-Memory54/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……D11111010001三管动态RAM芯片(Intel1103)写读写控制电路ECE313Fall2006Lecture20-Memory55/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……D11111010001三管动态RAM芯片(Intel1103)写读写控制电路ECE313Fall2006Lecture20-Memory56/89A9A8A7A6A5读写控制电路列地址译码器………读选择线写选择线D单元电路行地址译码器00113131131A4A3A2A1A0刷新放大器写数据线读数据线……………0……D11111010001三管动态RAM芯片(Intel1103)写读写控制电路ECE313Fall2006Lecture20-Memory57/89存储器与CPU的连接-存储器容量的扩展(1)位扩展（增加存储字长）用2片1K

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4位存储芯片组成1K

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8位的存储器10根地址线8根数据线DD••••D0479AA0•••21142114CSWEECE313Fall2006Lecture20-Memory58/89(2)字扩展（增加存储字的数量）用2片1K

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8位存储芯片组成2K

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8位的存储器11根地址线8根数据线1K

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8位1K

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8位D7D0•••••••••••••••••WEA1A0•••A9CS0A10

1CS1ECE313Fall2006Lecture20-Memory59/89(3)字、位扩展用8片1K

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4位存储芯片组成4K

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8位的存储器8根数据线12根地址线WEA8A9A0...D7D0……A11A10CS0CS1CS2CS3片选译码................1K×41K×41K×41K×41K×41K×41K×41K×4ECE313Fall2006Lecture20-Memory60/89存储器与CPU的连接的一般步骤

(1)地址线的连接：首选低位地址；(2)数据线的连接：位数要相等；(3)读/写线的连接：直接相连；(4)片选线的连接：MREQ和空闲的高地址组合(5)合理选用芯片：RAM/ROM分清(6)其他时序、负载Attention:地址线不可悬空，多余的地址线作为控制线，地址线的特定组合决定控制逻辑的设计ECE313Fall2006Lecture20-Memory61/89例题：设CPU有16根地址线，8根数据线，用MREQ（低电平有效）作访存控制信号，用WR作读/写控制信号（高电平为读，低电平为写）。现有如下存储芯片：1Kx4位RAM；4Kx8RAM；8Kx8RAM；2Kx8位ROM；4Kx8ROM；8Kx8ROM，及74L138译码器和各种门电路。请画出CPU与存储器的连接图，要求：1、主存地址空间分配6000H~67FFH为系统程序区6800H~6BFFH为用户程序区2、合理选用上述芯片，说明各选几片？3、画出存储芯片的片选逻辑图ECE313Fall2006Lecture20-Memory62/89(1)写出对应的二进制地址码(2)确定芯片的数量及类型0110000000000000A15A14A13A11A10…A7…

A4A3…

A0…01100111111111110110100000000000…01101011111111112K×8位1K×8位RAM2片1K×4位ROM1片

2K×8位ECE313Fall2006Lecture20-Memory63/89(3)分配地址线A10~A0接2K

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8位ROM的地址线A9~A0接1K

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4位RAM的地址线(4)确定片选信号CBA0110000000000000A15A13A11A10…A7…

A4A3…

A0…01100111111111110110100000000000…01101011111111112K

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8位1片ROM1K

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4位2片RAMECE313Fall2006Lecture20-Memory64/892K

×8位ROM

1K

×4位

RAM1K

×4位

RAM………&PD/ProgrY5Y4G1CBAG2BG2A……MREQA14A15A13A12A11A10A9A0…D7D4D3D0WR…………CPU与存储器的连接图………ECE313Fall2006Lecture20-Memory65/89Outline-MemorySystemsOverview MotivationGeneralStructureandTerminologyMemoryTechnologyStaticRAM DynamicRAMCacheMemory 3VirtualMemoryECE313Fall2006Lecture20-Memory66/89CPUHit:DatainCache(nopenalty)Miss:DatanotinCache(misspenalty)CacheMemoryDRAMMemoryProcessoraddrdataaddrdataCacheOperationInsertbetweenCPU,MainMem.ImplementwithfastStaticRAMHoldssomeofaprogram’sdatainstructionsOperation:ECE313Fall2006Lecture20-Memory67/89FourKeyCacheQuestions:1. Wherecanblockbeplacedincache?

(blockplacement)2. Howcanblockbefoundincache?

(blockidentification)3. Whichblockshouldbereplacedonamiss?

(blockreplacement)4. Whathappensonawrite?

(writestrategy)ECE313Fall2006Lecture20-Memory68/89BasicCacheDesign以块的方式组织块的内容标记tag-extrabitstoidentifyblock(partofblockaddress)数据data-dataorinstructionwords -contiguousmemorylocations右边的例子:每块一个字(4byte)Tag为30位Cache中有2个块CPUCPUCPUtag0data0CPUCPUtag1data10x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemoryECE313Fall2006Lecture20-Memory69/89CacheExample(2)Assume:r1==0,r2==1,r4==21cycleforcacheaccess5cyclesformain.mem.access1cycleforinstr.executionAtcycle1-PC=0x00FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem

(5cyclepenalty)CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLMISSECE313Fall2006Lecture20-Memory70/89CacheExample(3)Atcycle6Executeinstr.addr1,r1,r2CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…000

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…0ECE313Fall2006Lecture20-Memory71/89CacheExample(4)Atcycle6-PC=0x04FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem

(5cyclepenalty)CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…0MISS6-10 FETCH

0x…4

ECE313Fall2006Lecture20-Memory72/89CacheExample(5)Atcycle11Executeinstr.bner4,r1,LCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…000

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…004

bner4,r1,L0x…111 0x…4 bner4,r1,L

1ECE313Fall2006Lecture20-Memory73/89CacheExample(6)Atcycle11-PC=0x00FetchinstructionfrommemoryHIT-instructionincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…1HIT11 0x…4 bner4,r1,L

111 FETCH0x…0 1ECE313Fall2006Lecture20-Memory74/89CacheExample(7)Atcycle12Executeaddr1,r1,2CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner1,r2,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 2ECE313Fall2006Lecture20-Memory75/89CacheExample(8)Atcycle12-PC=0x04FetchinstructionfrommemoryHIT-instructionincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x04HITECE313Fall2006Lecture20-Memory76/89CacheExample(9)Atcycle13Executeinstr.bner4,r1,LBranchnottakenCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,LECE313Fall2006Lecture20-Memory77/89CacheExample(10)Atcycle13-PC=0x08FetchInstructionfromMemoryMISS-notincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,L13 FETCH0x08MISSECE313Fall2006Lecture20-Memory78/89CacheExample(11)Atcycle17-PC=0x08PutinstructionintocacheReplaceexistinginstructionCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,L13-17 FETCH0x08

subr1,r1,r10x…2ECE313Fall2006Lecture20-Memory79/89CacheExample(12)Atcycle18Executesubr1,r1,r1CPUCPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

16-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0112 addr1,r1,2212 FETCH0x04213 bner4,r1,L213-17 FETCH0x08218 subr1,r1,r10

subr1,r1,r10x…2ECE313Fall2006Lecture20-Memory80/89CacheExample(13)Atcycle18FetchinstructionfrommemoryMISS-notincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0112 addr1,r1,2212 FETCH0x04213 bner4,r1,L213-17 FETCH0x082

subr1,r1,r118 subr1,r1,r1018 FETCH0x0CMISSECE313Fall2006Lecture20-Memory81/89CacheExample(14)Atcycle22PutinstructionintocacheReplaceexistinginstructionCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCy