高速串行接口技术详解

高速串行接口技术详解第一页，共41页。IntroductionHigh-speedI/OoverviewHotdesignissuesDesignexamplesSummaryOutline2第二页，共41页。IntroductionMoore’slawPerformance&densityimprovementindigitalsystem1001011021031041051061071081980198419881992199620002004Gatesdensity1001011021031041980198419881992199620002004CPUperformance3第三页，共41页。IntroductionMoore’slaw1001011021031041980198419881992199620002004CPUperformanceMemoryaccess1001011021031041051061071081980198419881992199620002004GatesdensitySignalpinsGrowinggaplimitssystemperformance!!4第四页，共41页。DigitalSystemPerformanceCommunication-boundComputation-boundPerformancebottleneckThecostofarithmeticoperationischeapnow“PentiumPro”10~20cycles/Arithmeticoperation70cycles/DRAMaccess“Pentium4”20~30cycles/Arithmeticoperation500~600cycles/DRAMaccess5第五页，共41页。ComputingSystemHigh-speedI/OisneededeverywhereNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OLongdistanceSAN6第六页，共41页。ParallelBus&SerialLinkGroupdata(Bus)SourcesynchronousMatchedtraceParallelBusCoreI/OClockDataCoreI/OSerialLinkCoreI/OSerialDataCoreI/OSingletracePlesiochronousClockembeddedindataClock&datarecovery7第七页，共41页。Parallelvs.SerialParallelBusSerialLinkHardwareComplexityLowHighLatencyShortLongSpeed~200Mbps/pin~10Gbps/pinormoreManufacturingCostHighLowWorldismovingtoward“seriallink”or“serial-link-likeparallelbus”!!8第八页，共41页。SerialLinkArchitectureReceiverTransmitterPLLFramerPCSSerializerDeframerClockrecoveryChannelPCSDeserializerTransmitter+Receiver=Transceiver9第九页，共41页。LinkComponentPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)Phase-lockedLoop(PLL)Frequencymultiplication:fout=M·finJitterfilterZero-delaybuffer10第十页，共41页。LinkComponentHigh-speed,lowvoltageswinginterfaceUsually,differentialSmallswing-~severalhundredsmVZ0Z0ChannelDCblockTermination(R=Z0)VTTVRRToCDRDriverLimitingamp11第十一页，共41页。LinkComponentClock&datarecovery(CDR)circuitsNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitDiDoCKr0110100100012第十二页，共41页。LinkPerformanceMetricEyediagram&jitterRandombitsequenceTbitEyediagramTbitTiminguncertainty:JitterJitterhistogramIdealRealistic13第十三页，共41页。LinkPerformanceMetricEyediagramexample–Nearend&farendPLLFramerDeframerClockrecoveryChannel14第十四页，共41页。LinkPerformanceMetricBit-errorrate(BER)Inmostseriallinkstandards,BER<10-12isspecifiedEyediagramJitterhistogramRecoveredclockBiterror!!JitterPDF=

f(x)15第十五页，共41页。High-SpeedLinkStandardsNorthBridgeCPUSouthBridgeMemoryGraphicDiskLANDisplaySwitchLocalI/OSANDVILVDSEthernetSATASONET/SDHFibreChannelInfiniBandPCIExpressHyperTransportRDRAMXDR16第十六页，共41页。IndustryRoadmaps0.1G1G10G100GData-rateEthernetSONET/SDHFastEthernetGigabitEthernet10GEthernetOC-48OC-192OC-768SATAOC-12XAUIGen1Gen2Gen3PCIExpressPCIe1.0PCIe2.0(?)FibreChannelFC-PI-1FC-PI-210GFCDVIVGAUXGASXGAYear2005,worldishere!!17第十七页，共41页。DigitalVisualInterface(DVI)PCdisplay–CRT(analog)LCD(digital)DVI–DigitalVisualInterfaceAnalogDigital18第十八页，共41页。DigitalVisualInterface(DVI)TMDSTransitionminimizeddifferentialsignalingEMIreductionTMDSencoderPLLGraphiccontrollerTMDSdecoderPLLDisplaycontroller19第十九页，共41页。HighDefinitionMultimediaInterface(HDMI)HDMIHigh-definitionmulti-mediainterfaceDigitalvideo+multi-channelaudiointerfaceforconsumerelectronicsCompatiblewithDVI20第二十页，共41页。SerialATA(SATA)NextgenerationATAbuswithinPCboxEliminatesfatATAcablesPoint-to-pointconnection–1.5G/3G/6GParallelATAcablingSerialATAcabling21第二十一页，共41页。TransceiverChipDesignTechnologyCMOS,InP,GaAs,SiGe,BiCMOS…CMOSwillbetheeventualwinner–Lowcost,high-integritySpeedPowerconsumptionAreaLevelofintegrationMixed-signalSoC–Seriallinkinterface+digitalcircuitryTrade-off!!22第二十二页，共41页。HotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiver23第二十三页，共41页。HotDesignIssuesPLLFramerDeframerClockrecoveryCMOSseriallinktransceiverPrecise-timinggeneration-High-frequency,lowjitterPLLHigh-performanceCDR-High-speedNRZPD-VariousCDRarchitecturesHigh-speedCMOScircuits-Logicgates,analogbufferChannellosscompensation-Equalizer24第二十四页，共41页。PreciseTiminggenerationVCOnoisePLLjitterDataeyejitterLownoise,high-frequencyVCOisrequiredPhaseDetectorLoop-FilterVoltage-ControlledOscillatorMCKi(fin)VctrerrorCKo(fout)25第二十五页，共41页。Voltage-ControlledOscillatorPoorNoiseGoodLowFrequencyHighWideTuningrangeNarrowLowCostHighRingoscillatorMstagesdMTf21=Td=C·V/ILCtankoscillatorParasiticresistanceNegativegmOn-chipspiralLOn-chipvaractorvarLCfp21=26第二十六页，共41页。High-SpeedCMOSCircuitsCurrent-modelogic(CML)ZLNMOSLogicRR+LR+T-coilCMOSlogicNMOSPull-downPMOSPull-upComplementaryIntermediateSpeedFastSmallAreaLargeSmallPowerconsumptionLargeHigh-speedlogicgates27第二十七页，共41页。High-SpeedCMOSCircuitsHigh-speedbufferwithon-chipinductorShuntpeaking–InsertsazeroathighfrequencySeriespeaking–IsolatesthebufferoutputnodefromloadcapacitanceNormalShuntpeakingShuntpeakingShuntseriespeakingSeriespeakingShuntdouble-seriespeakingSeriespeaking28第二十八页，共41页。High-SpeedCDR–NRZPDHoggephase-detector–LinearPDFull-rateoperationMatchedup/downwhenlocked–LessnoisyDQDQDNUPCKDABDCKABUPDNAreadifferencePhaseerrorVeryshortpulse!!Phaseerror–Clockearly29第二十九页，共41页。High-SpeedCDR–NRZPDAlexanderphase-detector–BinaryPDWithmulti-phaseclock–TimeinterleavingBang-bangcontrol–NoisyD0D1ABTClockearlyD0D1ABTClocklateUPDNDQDQDQDQBADNUPTCKD30第三十页，共41页。High-SpeedCDR–ArchitecturesPLL-basedCDR1PLL/channel–PrecisephasecontrolSuitableforhigh-speed,high-performancesystemNRZPhaseDetectorLoop-FilterVoltage-ControlledOscillatorDiVctrerrorDoCKrDecisioncircuitEitherlinearorbinary31第三十一页，共41页。ChannelLossBand-limitedchannelBondingwire,PCBtrace,connector,cable…SkineffectDielectricloss32第三十二页，共41页。ChannelLossEffectInter-symbolinterference(ISI)00010111Time-4TB-3TB-2TB-TBTB2TB3TB4TB0Amplitude33第三十三页，共41页。ChannelLossCompensationTX–Pre-emphasisWithpre-emphasisWithoutpre-emphasis34第三十四页，共41页。ChannelLossCompensationRX–EqualizationContinuoustimeequalizergDinDoutHigh-passfilterCapacitivedegeneration35第三十五页，共41页。DesignExamples40GbpstransmitterProcess–0.13CMOSPower–2.8WArea–2.5