内存基本知识4DRAM工作原理课件

DRAM工作原理DRAM工作原理DynamicRandomAccessMemoryEachcellisacapacitor+atransistorVerysmallsizeSRAMusessixtransistorspercellDividedintobanks,rows&columnsEachbankcanbeindependentlycontrolledDRAMDynamicRandomAccessMemoryDRMainMemoryEverythingthathappensinthecomputerisresidentinmainmemoryCapacity:around100Mbyteto100Gbyte

Randomaccess

Typicalaccesstimeis10-100nanosecondsWhyDRAMforMainMemory??Costeffective(smallchipareathanSRAM)HighSpeed(thanHDD,flash)HighDensity(~Gbyte)MassProduction……MainmemoryMainMemoryMainmemoryNotation:K,M,GInstandardscientificnomenclature,themetricmodifiersK,M,andGtorefertofactorsof1,000,1,000,000and1,000,000,000respectively.ComputerengineershaveadoptedKasthesymbolforafactorof1,024(210)K:1,024(210)M:1,048,576(220)G:1,073,741,824(230)DRAM’density256M-bit512M-bitNotation:K,M,GDRAMDensityDRAMDensityWhatisaDRAM?DRAMstandsforDynamicRandomAccessMemory.RandomaccessreferstotheabilitytoaccessanyoftheinformationwithintheDRAMinrandomorder.Dynamicreferstotemporaryortransientdatastorage.Datastoredindynamicmemoriesnaturallydecaysovertime.Therefore,DRAMneedperiodicrefreshoperationtopreventdataloss.WhatisaDRAM?Memory:DRAMpositionSemiconductormemorydeviceROM:NonvolatileMaskROMEPROMEEPROMFlashNAND:lowspeed,highdensityNOR:highspeed,lowdensityRAM:VolatileDRAM:DynamicRandomAccessMemorySRAM:StaticRandomAccessMemoryPseudoSRAMMemory:DRAMpositionDRAMTrend:FutureHighSpeed-DDR(333MHz~500MHz),DDR2(533~800Mbps),DDR3(800~1600Mbps)-Skew-delayminimizedcircuit/logic:post-chargelogic,wave-pipelining-NewArchitecture:multi-bankstructure,highspeedInterfaceLowPower-5.5V=>3.3V(sdr)=>2.5V(ddr)=>1.8V(ddr2)=>1.5v(ddr3)=>1.2v?-SmallvoltageswingI/Ointerface:LVTTLtoSSTL,opendrain-LowPowerDRAM(PASR,TCSR,DPD)HighDensity-Memorydensity:32MB=>64MB=>.....1GB=>2GB=>4GB-applicationexpansion:mobile,memoryDBforshock(thanHDD)-Processshrink:145nm(‘03)=>120nm(‘04)=>100nm=>90nm=>80nm…OtherTrends-CostEffectiveness,TechnicalCompatibility,Stability,Environment.ReliabilityDRAMTrend:FutureStaticRAMSRAMBasicstorageelementisa4or6transistorcircuitwhichwillholda1or0aslongasthesystemcontinuestoreceivepowerNoneedforaperiodicrefreshingsignaloraclockUsedinsystemcacheFastestmemory,butexpensiveSRAMElementEnableLine/BitLineBitLineStaticRAMSRAMSRAMElementEnabDynamicRAMDRAMDensertypeofmemoryMadeupofone-transistor(1-T)memorycellwhichconsistsofasingleaccesstransistorandacapacitorCheaperthanSRAMUsedinmainmemoryMorecomplicatedaddressingschemeDRAMCellWordLineBitLineDynamicRAMDRAMDRAMCellWordLRefreshinDRAMsCapacitorleaksovertime,theDRAMmustbe“REFRESHED”.

DRAMCellWordLineBitLineCapacitanceLeakageRefreshinDRAMsCapacitorleakSRAMvs.DRAMSRAMvs.DRAM内存基本知识4DRAM工作原理课件DRAMLeadFrameandWirebondingDRAMLeadFrameandWirebondiDRAMArchitectureDRAMArchitectureSDRAMhasthemultibankarchitecture.ConventionalDRAMwasproductthathavesinglebankarchitecture.Thebankisindependentactive.

memoryarrayhaveindependentinternaldatabusthathavesamewidthasexternaldatabus.Everybankcanbeactivatingwithinterleavingmanner.Anotherbankcanbeactivatedwhile1stbankbeingaccessed.(Burstreadorwrite)MultiBankArchitectureSDRAMhasthemultibankarchiDRAMMultiBankArchitectureDRAMMultiBankArchitectureDRAMSingleBankArchitectureDRAMSingleBankArchitecture内存基本知识4DRAM工作原理课件DRAMBlockDiagram(1)DRAMBlockDiagram(1)DRAMBlockDiagram(2)DRAMBlockDiagram(2)DRAMCoreArchitectureDRAMCoreArchitectureDRAMAddressDRAMAddressDRAMCoreArchitectureDRAMCoreArchitecture16bitDRAMCore16bitDRAMCoreDRAMDataPathDRAMDataPathDRAM1T-1CstructureDRAM1T-1CstructureRAS:rowaddressstrobeCAS:columnaddressstrobeWE:writeenableAddress:codetoselectmemorycelllocationDQ(I/O):bidirectionalchanneltotransferandreceivedataDRAMcell:storageelementtostorebinarydatabitRefresh:theactiontokeepdatafromleakageActive:sensedatafromDRAMcellPrecharge:standbystateDRAMKeywordRAS:rowaddressstrobeDRAMKeDRAMcellarrayconsistofsomanycells.Onetransistor&OnecapacitorSmallsenseamplifierLowinputgainfromchargesharingCS:Smallstoragecapacitor:25fFCBL:Largeparasiticcapacitor:over100fFVc:StoragevoltageVCP:halfVcforplatebiasVBLP:halfVcforBLprechargebias(initialbias)DRAMCellDRAMcellarrayconsistofsoDRAMArrayOverviewSimplifiedExampleDRAMArrayOverviewSimplifiedActivatingaRowActivatingaRowMustbedonebeforeareadorwriteJustlatchtherowaddressandturnonasinglewordlineActivatingaRowActivatingaRWritingWritingArowmustbeactiveSelectthecolumnaddressDrivethedatathroughthecolumnmuxStoresthechargeonasinglecapacitorWritingWritingReadingReadingArowmustbeactiveSelectthecolumnaddressThevalueinthesense-amplifierisdrivenbackoutReadingReadingTheSense-AmplifierSense-AmplifierApairofcross-coupledinvertersBasicallyanSRAMelementWeakerthanthecolumnmuxWritedatawill“outmuscle”thesense-amplifierKeepsthedataatfulllevelTheSense-AmplifierSense-AmpliPrechargePrechargeInactivestate(nowordlinesactive)PrechargecontrollinehighTiesthetwosidesofthesense-amptogetherThismakesthebitlinesstayatVDD/2Onlystableaslongastheprechargecontrollineishigh—otherwisethisisunstable!NocapacitorsconnectedPrechargePrechargeActivationRevisitedActivationTurnofftheprechargecontrollineMakesthesense-ampunstable—itwantstogotoeither0or1insteadofstayingatVDD/2Averyveryveryshorttimelater,turnonthewordlineoftherowtobeactivated.CouplesthecapacitorontothebitlinesThis“tips”thebitlinestoholdthestoredvalue.Thesense-ampamplifiesthecapacitorbacktofullvalue.(hencethename!)ActivationRevisitedActivationDRAMRefreshBecausethestoredmemoryvalueisstoredonacapacitor(thathasresistiveleakage),thememoryisconstantly“forgetting”itscontents.Eventually,thechargeonthecapacitorwon’tbeenoughtotipthesense-ampintherightdirection.But,activatingarowrestoresthecellsonthatrowtotheirfullvalue.Thereisanexplicitrefreshcommandthatjustactivatesandimmediatelydeactivatesarow.TheDRAMhasaninternalcounterthatcontainsthenextrowtoberefreshedandincrementseverytimearefreshcommandisissued.DRAMRefreshBecausethestoredDRAMRefreshDataRetentionTimeDRAMCellconsistsofcapacitancewhichhasleakageastimeRetentiontimeisperiodformaintainingitsdataespecially‘1’dataUsually,DRAMCellrefreshperiodis64msRefreshTimingtREF:Realcellretentiontime(Devicecharacteristic),ex)90ms(Hot)tRFC:Refreshcommandoperatingtime,ex)75nsRefreshSpec.BurstRefresh:64msDistributerefresh-128Mbdevice(12Rowaddress):64ms/4K=15.6us-256Mbdevice(13Rowaddress):64ms/8K=7.8usDRAMRefreshDataRetentionTimAUTORefreshWhenthiscommandisinputfromtheIDLEstate,thesynchronousDRAMstartsautorefreshoperation.Duringtheauto-refreshoperation,refreshaddressandbankselectaddressaregeneratedinsidetheSynchronousDRAM.Foreveryauto-refreshcycle,theinternaladdresscounterisupdated.Accordingly,8192timesarerequiredtorefreshtheentirememory.Beforeexecutingtheauto-refreshcommand,allthebankmustbeIDLEstate.Inaddition,sincethePrechargeforallbankisautomaticallyperformedafterauto-refresh,noPrechargecommandisrequiredafterauto-refresh.AUTORefreshWhenthiscoSelfRefreshSelf-RefreshEntry[SELF]:WhenthiscommandisinputduringtheIDLEstate,theSynchronousDRAMstartsself-refreshoperation.Aftertheexecutionofthiscommand,selfrefreshcontinueswhileCKEisLow.Sinceself-refreshisperformedinternallyandautomatically,externalrefreshoperationsareunnecessary.Self-RefreshExit[SELFX]:Whenthiscommandisexecutedduringself-refreshmode,theSyncDRAMcanexitfromself-refreshmode.Afterexitingfromself-refreshmode,theSyncDRAMenterstheIDLEstate.,noPrechargecommandisrequiredafterauto-refresh.SelfRefreshSelf-RefreshModeRegisterSpecialcommandtoinitializetheDRAMBurstlengthInterleavingCASLatency(readcommandtoreaddatainclocks)ForDDR,DLLresetisalsohereModeRegisterSpecialcommandtMRSBlockDiagramMRSBlockDiagramModeRegisterBecausethestoredmemoryvalueisstoredonaModeRegisterBecausethestoreExtendedModeRegisterSpecialcommandtoinitializeDDRDRAMDDRonly—don’tuseforSDRDLLEnableDriveStrengthExtendedModeRegisterSpecialDRAMInterfaceCommandSignalsCAS#,RAS#,WE#,CS#CS#+CAS#=ReadCS#+WE#+CAS#=WriteCS#+RAS#+CAS#=RefreshCS#+RAS#=ActivateCS#+WE#=BurstStopCS#+WE#+RAS#=PrechargeCS#+WE#+CAS#+RAS#=MRSorEMRSAllothers:NOPOthersignals:CLK,DATA[],DQSDRAMInterfaceCommandSignalsDRAMInterfaceAllsignalsgofromthehosttothememoryexceptDQSanddatawhicharebi-directional.DRAMInterfaceAllsignalsgofReadCycleTypicalReadCycleBurstLength4CASLatency=3ReadCycleTypicalReadCycleWriteCycleTypicalWriteCycleBurstLength4WritelatencyisalwayszeroWriteCycleTypicalWriteCycleDataClockingCLKisalwaysdrivenbythehostDQSisdrivenbywhoeverisdrivingthedataNVchipdrivesonwritecyclesMemorychipdrivesonreadcyclesThisschemeiscalled“source-synchronousclocking”EliminatesalotofthetimingheadachesfromSDRAddsmarginDataClockingCLKisalwaysdriLatenciesAllkindsActivatetoPrechargeLastwritedatatoprechargeActivatetoReadActivatetoWriteRefreshcycletimeRefreshintervalMinimumrowactivetimeYaddayaddayaddaControlledbyPFB_TIMING0,PFB_TIMING1,PFB_TIMING2LatenciesAllkindsWriteCycleWriteCycleDLLsADLLisaDelay-LockedLoopNotransistorcanswitchinzerotime,sotherewillbeadelaybetweenclockandDQSonreadsBut,itwouldmakeiteasierifDQSwasalwaysinphasewithclock.DLL-offclock->DQSdelaynotinthespecVariesbetweenmemoryvendorsRe-createsadelayedversionofitsinputclockKeepsDQSonreadsalignedwithclocksIt’sananalogcircuitandissensitivetonoiseCanloselockontheinputclockifthesignalisnotcleanortheDLLpowersupplyisnoisy.DLLsADLLisaDelay-LockedLoDLLsDLLonDLLoffDLLsDLLontAA,tAC,tOHtRCD,tRPSet-up/HoldtimeVih,VilVoh,VolIoh,IolTimingParameterstAA,tAC,tOHTimingParametSDRAMTimingDiagramSDRAMTimingDiagramtAA,tAC,tOH(SDRAM)tAA,tAC,tOH(SDRAM)Setup/holdtimeTimingforlatchingdatainInputbufferCLKrisingedgeisstrobefordata(SDRAM)DQSrising&fallingedgeisstrobefordata(DDRSDRAM)DuringSetup&time,thereisnoabnormalsignalallowedSetup/holdtimeTimingVIH/VILVIH/VILVOH/VOLVOH/VOLIOH/IOLIOH/IOLDCSpecDCSpecThanks!Thanks!DRAM工作原理DRAM工作原理DynamicRandomAccessMemoryEachcellisacapacitor+atransistorVerysmallsizeSRAMusessixtransistorspercellDividedintobanks,rows&columnsEachbankcanbeindependentlycontrolledDRAMDynamicRandomAccessMemoryDRMainMemoryEverythingthathappensinthecomputerisresidentinmainmemoryCapacity:around100Mbyteto100Gbyte

Randomaccess

Typicalaccesstimeis10-100nanosecondsWhyDRAMforMainMemory??Costeffective(smallchipareathanSRAM)HighSpeed(thanHDD,flash)HighDensity(~Gbyte)MassProduction……MainmemoryMainMemoryMainmemoryNotation:K,M,GInstandardscientificnomenclature,themetricmodifiersK,M,andGtorefertofactorsof1,000,1,000,000and1,000,000,000respectively.ComputerengineershaveadoptedKasthesymbolforafactorof1,024(210)K:1,024(210)M:1,048,576(220)G:1,073,741,824(230)DRAM’density256M-bit512M-bitNotation:K,M,GDRAMDensityDRAMDensityWhatisaDRAM?DRAMstandsforDynamicRandomAccessMemory.RandomaccessreferstotheabilitytoaccessanyoftheinformationwithintheDRAMinrandomorder.Dynamicreferstotemporaryortransientdatastorage.Datastoredindynamicmemoriesnaturallydecaysovertime.Therefore,DRAMneedperiodicrefreshoperationtopreventdataloss.WhatisaDRAM?Memory:DRAMpositionSemiconductormemorydeviceROM:NonvolatileMaskROMEPROMEEPROMFlashNAND:lowspeed,highdensityNOR:highspeed,lowdensityRAM:VolatileDRAM:DynamicRandomAccessMemorySRAM:StaticRandomAccessMemoryPseudoSRAMMemory:DRAMpositionDRAMTrend:FutureHighSpeed-DDR(333MHz~500MHz),DDR2(533~800Mbps),DDR3(800~1600Mbps)-Skew-delayminimizedcircuit/logic:post-chargelogic,wave-pipelining-NewArchitecture:multi-bankstructure,highspeedInterfaceLowPower-5.5V=>3.3V(sdr)=>2.5V(ddr)=>1.8V(ddr2)=>1.5v(ddr3)=>1.2v?-SmallvoltageswingI/Ointerface:LVTTLtoSSTL,opendrain-LowPowerDRAM(PASR,TCSR,DPD)HighDensity-Memorydensity:32MB=>64MB=>.....1GB=>2GB=>4GB-applicationexpansion:mobile,memoryDBforshock(thanHDD)-Processshrink:145nm(‘03)=>120nm(‘04)=>100nm=>90nm=>80nm…OtherTrends-CostEffectiveness,TechnicalCompatibility,Stability,Environment.ReliabilityDRAMTrend:FutureStaticRAMSRAMBasicstorageelementisa4or6transistorcircuitwhichwillholda1or0aslongasthesystemcontinuestoreceivepowerNoneedforaperiodicrefreshingsignaloraclockUsedinsystemcacheFastestmemory,butexpensiveSRAMElementEnableLine/BitLineBitLineStaticRAMSRAMSRAMElementEnabDynamicRAMDRAMDensertypeofmemoryMadeupofone-transistor(1-T)memorycellwhichconsistsofasingleaccesstransistorandacapacitorCheaperthanSRAMUsedinmainmemoryMorecomplicatedaddressingschemeDRAMCellWordLineBitLineDynamicRAMDRAMDRAMCellWordLRefreshinDRAMsCapacitorleaksovertime,theDRAMmustbe“REFRESHED”.

DRAMCellWordLineBitLineCapacitanceLeakageRefreshinDRAMsCapacitorleakSRAMvs.DRAMSRAMvs.DRAM内存基本知识4DRAM工作原理课件DRAMLeadFrameandWirebondingDRAMLeadFrameandWirebondiDRAMArchitectureDRAMArchitectureSDRAMhasthemultibankarchitecture.ConventionalDRAMwasproductthathavesinglebankarchitecture.Thebankisindependentactive.

memoryarrayhaveindependentinternaldatabusthathavesamewidthasexternaldatabus.Everybankcanbeactivatingwithinterleavingmanner.Anotherbankcanbeactivatedwhile1stbankbeingaccessed.(Burstreadorwrite)MultiBankArchitectureSDRAMhasthemultibankarchiDRAMMultiBankArchitectureDRAMMultiBankArchitectureDRAMSingleBankArchitectureDRAMSingleBankArchitecture内存基本知识4DRAM工作原理课件DRAMBlockDiagram(1)DRAMBlockDiagram(1)DRAMBlockDiagram(2)DRAMBlockDiagram(2)DRAMCoreArchitectureDRAMCoreArchitectureDRAMAddressDRAMAddressDRAMCoreArchitectureDRAMCoreArchitecture16bitDRAMCore16bitDRAMCoreDRAMDataPathDRAMDataPathDRAM1T-1CstructureDRAM1T-1CstructureRAS:rowaddressstrobeCAS:columnaddressstrobeWE:writeenableAddress:codetoselectmemorycelllocationDQ(I/O):bidirectionalchanneltotransferandreceivedataDRAMcell:storageelementtostorebinarydatabitRefresh:theactiontokeepdatafromleakageActive:sensedatafromDRAMcellPrecharge:standbystateDRAMKeywordRAS:rowaddressstrobeDRAMKeDRAMcellarrayconsistofsomanycells.Onetransistor&OnecapacitorSmallsenseamplifierLowinputgainfromchargesharingCS:Smallstoragecapacitor:25fFCBL:Largeparasiticcapacitor:over100fFVc:StoragevoltageVCP:halfVcforplatebiasVBLP:halfVcforBLprechargebias(initialbias)DRAMCellDRAMcellarrayconsistofsoDRAMArrayOverviewSimplifiedExampleDRAMArrayOverviewSimplifiedActivatingaRowActivatingaRowMustbedonebeforeareadorwriteJustlatchtherowaddressandturnonasinglewordlineActivatingaRowActivatingaRWritingWritingArowmustbeactiveSelectthecolumnaddressDrivethedatathroughthecolumnmuxStoresthechargeonasinglecapacitorWritingWritingReadingReadingArowmustbeactiveSelectthecolumnaddressThevalueinthesense-amplifierisdrivenbackoutReadingReadingTheSense-AmplifierSense-AmplifierApairofcross-coupledinvertersBasicallyanSRAMelementWeakerthanthecolumnmuxWritedatawill“outmuscle”thesense-amplifierKeepsthedataatfulllevelTheSense-AmplifierSense-AmpliPrechargePrechargeInactivestate(nowordlinesactive)PrechargecontrollinehighTiesthetwosidesofthesense-amptogetherThismakesthebitlinesstayatVDD/2Onlystableaslongastheprechargecontrollineishigh—otherwisethisisunstable!NocapacitorsconnectedPrechargePrechargeActivationRevisitedActivationTurnofftheprechargecontrollineMakesthesense-ampunstable—itwantstogotoeither0or1insteadofstayingatVDD/2Averyveryveryshorttimelater,turnonthewordlineoftherowtobeactivated.CouplesthecapacitorontothebitlinesThis“tips”thebitlinestoholdthestoredvalue.Thesense-ampamplifiesthecapacitorbacktofullvalue.(hencethename!)ActivationRevisitedActivationDRAMRefreshBecausethestoredmemoryvalueisstoredonacapacitor(thathasresistiveleakage),thememoryisconstantly“forgetting”itscontents.Eventually,thechargeonthecapacitorwon’tbeenoughtotipthesense-ampintherightdirection.But,activatingarowrestoresthecellsonthatrowtotheirfullvalue.Thereisanexplicitrefreshcommandthatjustactivatesandimmediatelydeactivatesarow.TheDRAMhasaninternalcounterthatcontainsthenextrowtoberefreshedandincrementseverytimearefreshcommandisissued.DRAMRefreshBecausethestoredDRAMRefreshDataRetentionTimeDRAMCellconsistsofcapacitancewhichhasleakageastimeRetentiontimeisperiodformaintainingitsdataespecially‘1’dataUsually,DRAMCellrefreshperiodis64msRefreshTimingtREF:Realcellretentiontime(Devicecharacteristic),ex)90ms(Hot)tRFC:Refreshcommandoperatingtime,ex)75nsRefreshSpec.BurstRefresh:64msDistributerefresh-128Mbdevice(12Rowaddress):64ms/4K=15.6us-256Mbdevice(13Rowaddress):64ms/8K=7.8usDRAMRefreshDataRetentionTimAUTORefreshWhenthiscommandisinputfromtheIDLEstate,thesynchronousDRAMstartsautorefreshoperation.Duringtheauto-refreshoperation,refreshaddressandbankselectaddressaregeneratedinsidetheSynchronousDRAM.Foreveryauto-refreshcycle,theinternaladdresscounterisupdated.Accordingly,8192timesarerequiredtorefreshtheentirememory.Beforeexecutingtheauto-refreshcommand,allthebankmustbeIDLEstate.Inaddition,sincethePrechargeforallbankisautomaticallyperformedafterauto-refresh,noPrechargecommandisrequiredafterauto-refresh.AUTORefreshWhenthiscoSelfRefreshSelf-RefreshEntry[SELF]:WhenthiscommandisinputduringtheIDLEstate,theSynchronousDRAMstartsself-refreshoperation.Aftertheexecutionofthiscommand,selfrefreshcontinueswhileCKEisLow.Sinceself-refreshisperformedinternallyandautomatically,externalrefreshoperationsareunnecessary.Self-RefreshExit[SELFX]:Whenthiscommandisexecutedduringself-refreshmode,theSyncDRAMcanexitfromself-refreshmode.Afterexitingfromself-refreshmode,theSyncDRAMenterstheIDLEstate.,noPrechargecommandisrequiredafterauto-refresh.SelfRefreshSelf-RefreshModeRegisterSpecialcommandtoinitializetheDRAMBurstlengthInterleavingCASLatency(readcommandtoreaddatainclocks)ForDDR,DLLresetisalsohereModeRegisterSpecialcommandtMRSBlockDiagramMRSBlockDiagramModeRegisterBecausethestoredmemoryvalueisstoredonaModeRegisterBecausethestoreExtendedModeRegisterSpecialcommandtoinitializeDDRDRAMDDRonly—don’tuseforSDRDLLEnableDriveStrengthExtendedModeRegisterSpecialDRAMInterfaceCommandSignalsCAS#,RAS#,WE#,CS#CS#+CAS#