虚拟器件和接口模型

第九章以及它们在大型数字系统设计中的前宏单元(MacrocellsMegacells)或核(Cores)是预先设计好的，其功能经过验证的、由总EDAROMRAM）或总线接口的行为模型等，往往是不可综合的，也没有必要综合成具体电路，口80518251中断控制器（如8259、并行输入输出接口(PIO)、直接器存取（DMA、数字信号处理(DSP)、RAM和ROM和PCI总线控制器以及PCI总线控制接口等口设计和服务。目前国际上有一个叫作虚拟接口(VSIA)的组织，它是协调虚拟器件和虚虚拟器件和虚拟接口模块的供应商American算术运算函数异步同FIFOUARTUSARTsRAM和ROM不RTL 于仿真ScenixNS&target8237不RTLSierraResearchandATMSAR622 控制器CPUR3000不RTLSiliconMicro不RTLLucentPCIMasterPCI不RTL（三种都可虚拟模块的设计了怎样根据和波形图来编写虚拟的接口模型。1].模数转换AD7886仿真模型（虚拟模块）的设计：ADCVerilog（下面简称类型的数据，来测试后续电路的功能，并可以随时根据测试要求更改数据，非常方便。虚说明问题起见，只介绍A/D模块有关数字接口的一部分功能，把这部分功能编写成虚拟模的而编写的简化虚拟模块,在仿真时仅能代替真实A/D的一部分功能。它类似一个数据发生器，根据输入控制信号和A/D自身的特性输出一个字节（8位）数据和“忙”信号。同时根能够一次投片成功。因此在ASIC系统的设计中应予以充分的重视。AD78868 控制,数据的存取由选片信号CSRD输入信号控制(低电平有效1A/D（CSRD句。输出的8位数据可以根据要求自己编制，从数据文件AD.DATA中。下面是一个名为`timescale adc(nconvst,nbusy, //A/D启动脉冲ST，即上图中 //A/D工作标志，即上图中 reg[7:0] wire[7:0]data;reg[7:0]data_mem[0:255]; always@(negedgenconvst)tconv=9500+{$random}%500;//(type950,max1000）ConversionTimet5={$random}%1000;//(max CONVSTtoBUSYPropagation//CL=t8= //(min20)CL=20pfDataSetupTimePriorto//(min10)t9=100+{$random}%900;//(min10,max100)BusRelinquishTimet12= //(type)BUSYHightoCONVSTLow,SHAAcquisition$readmemh("adc.data",data_mem);//从数据文件adc.data中数i=nbusy=link_bus=assigndatalink_bus?databuf:8'bzz;在信号nconvst的负跳降沿到来后，隔t5秒nbusy信号置为低，tconv是AD将模拟信号转nconvsttconvnbusy always@(negedge#t5nbusy=0;@(posedgenconvst)

#tconvnconvstt9always@(negedgenconvst)@(posedgenconvst) if(wideth<10000&&wideth>500)if(i==255)elsei=always@(negedgenconvst)

#t9link_bus=1'b0; @(posedgenconvst) 当nconvst输入信号的下一个转换的下降沿与nbusy信号上升沿之间时间延迟小于t12时，将会出现警告信息，通知设计者请求转换的输入信号频率太快，A/Dalways@(posedgenbusy)if(!nconvst)$display("Warning!SHAAcquisitionTimeistooshort!");//else$display("SHAAcquisitionTimeisenough!");always@(negedgenconvst)@(posedgenconvst)wideth=$time-wideth;if(wideth<=500||wideth>10000)

$display("nCONVSTPulseWidth=而且还希望能提示产生错误的原因。虚拟模块的精确与否，直接决定设计的成败。ASIC的投片此编写这样的模块是一件复杂而细致的工作，需要极其认真的工作态度和作风，必须认真对待。为了简单起见，本节介绍的模块只具有AD7886AD7886说，我们尽量利用商业化的虚拟模块来设计自己的电路系统。只有在没有办法得到商业化的虚拟模块时，才利用器件手册来编写虚拟模块，因为编写精确的虚拟模块需要花费很多时间和精力。虚拟接口模块的实例下面我们介绍两个常用的大规模集成通用串行收发控制器USART8251和In8085微处理器CPU这两VerilogHDL描述的虚拟接口的行为模块是由Verilog语言的创始人P.R.Moorby和D.E.Thomas合作编写的(这是我们从Internet网络上得到的)。因为商品化的虚拟器件和虚拟接口模型是知识简称IP，必须保设计所的参绝下面的模块从严格意义上说来并非是真正的虚拟接口模型，因为它们并不对用户设计的成败负责。把它们列在这里只是拿它们作为学习VerilogHDL[例1].“商业化”的虚拟模块之一：InUSART8251A(通用串行异步收发器CADENCEDESIGNSYSTEMS,Inc.doesnotguaranteetheaccuracyorcompletenessofthismodel.Anyonewhousingthisdoessoattheirownrisk.********************************************************************/显然这一模块只是一个参考的实例，在本我们姑且把它当作虚拟接口模型来看VriogDL821A8251AUSART8251AVrilogHL通用串行异步收发器8251的VerilogHDL源代码moduleI8251A(dbus,rcd,gnd,txc_,write_,chipsel_,read_,rxrdy,txrdy,syndet,cts_,txe,txd,clk,reset,dsr_,rts_,dtr_,rxc_,vcc);/*timingconstants,forA.C.timingcheck,onlynon-zerotimesarespecified,innano-sec*//*readcycle`defineTRR`defineTRD`defineTDF100//max.time/*writecycle`defineTWW`defineTDW`defineTWD`defineTRV6//intermsofclock/*othertiming`defineTTXRDY8//8clock rcd,//receivedatarxc_,//receiveclocktxc_,//transmitchipsel_,//chipselectedwhenlow mand/data_selectdsr_,//datasetreadycts_,//cleartosendreset,//resetwhen //atleast30timesofthetransmit/rexeibedatabitratesoutputrxrdy,//receivedatareadywhenhightxd,//transmitdatalonetxrdy,//transmitbufferreadytoacceptanotherbytetotransfertxe,//transmitbufferemptyrts_,//requesttosenddtr_;//dataterminalreadyinout[7:0] syndet;//outsidesynchonousdetectoroutputtoindicatesyn txd,rxrdy,txe,dtr_,rts_;reg[7:0] receivebuf,rdata,status;//*****ADDBYFWNreg[3:0]reg[7:0]instance_id;regread,chipel_; //ifrecvdrv1dbusisdrivenbyassigndbus=recvdrv?rdata:8'bz;//*****:,- dbus=statusdrv?status:8'bz;//*****:->;assignreg tdata_out,//databeingtransmittedtdata_hold,//datatobetransmittednextiftdata_outisfullsync1,sync2,//synchronousdatabytesand(txrdy,status[0],command[0],regtransmitter_reset, //setto1uponareset,cleareduponwritedata //1ifdataintdata_outhasnotbeentransmitted. //1ifdataintdata_holdhasnotbeen//totdata_outforserial //1iftdata_hold_fullanditwasctswhen wastransferredto 0iftdata_holdisemptyorisfullbut filledwhileitwasnotreg //0ifastopbitwasjustsentandwedonot//towaitforanegedgeontxcbeforereg[7:0]nmossyndet_gate1(syndet,status[6],reg //1(2)iflookingfor1st(2nd)synconregsyncs_received; //1ifsynccharsreceived,0iflookinfforsyncregrec_sync_index; //indicatingthesyn.charactertobematchedintegerbreakcount_period;//numberofclockperiodstocountasregsync_to_transmit; //1(2)if1st(2nd)synccharshouldbesentnextreg[7:0] //masksoffthedatabits(ifcharsizeisnot//temporaryreg[1:0]csel;//indicateswhatnextwritemeansif//(0=modeinstruction,1=s reg[5:0] //baudreg[7:0]tstoptotal; //no.oftranmitclockpulsesforstopbit(0ifsyncmodereg[3:0]databits; //no.ofdatabitsinacharacter(5,6,7or8)reg //adatabyteisreadinifregwas_cts_when_received;//0:ifcts_washighwhencharwas//1:ifcts_waslowwhebcharwas (andsocharwassentbefore resete,start_receiver_e,hunt_sysnc1_e;regreceive_in_progress; COMMUNICATION taskframe_error;$display("I8251A(%h)at%d:***frameerror",instance_id,$time);taskparity_error;beginif(dflags[4])$display("I8251A(%h)at%d:***parityerrordata:%b",instance_id,$time,receivebuf);taskoverrun_error;$display("I8251A(%h)at%d:***oerrunerror",instance_id,$time); TIMINGVIOLATIONS integertime_dbus_setup,between_write_clks;//tocheckbetweenwrite reset_signal_in;//tochecktheresetsignalpulsewidthtime_dbus_setup=-time_write_begin=- =- =- =-between_write_clks=`TRV; //start:TRVclkperiodssincelastwrite/***Timingysisforreadcycles***/always@(negedgeread_)if(chipsel_==0)time_read_begin=$time;/*Timingviolation:readpulsemustbeTRRns*/always@(posedgeread_)if(chipsel_==0)disableread_address_watch;time_read_end=$time;if(dflags[3]&&(($time-time_read_begin)<$display("I8251A(%h)at%d:***readpulsewidthviolation",instance_id,$time);/*Timingviolation:address(comdat_andchipsel_)mustbestable stablethroughoutread taskread_address_watch;@(comdat_or //ifthe"address"if(read==0) //andread_didnotchangeatthesametimeif(dflags[3])$display("I8251A(%h)at%d:***addressholderroroninstance_id,/**Timingysisforwritecycles**/always@(negedgewrite_)if(chipsel_==0)time_write_begin=$time;/*Timingviolation:readpulsemustbeTRRns/*Timingviolation:TDWnsbussetuptimebeforeposedgewrite_/*Timingviolation:TWDnsbusholdtimeafterposedgewrite_always@(posedgewrite_)if(chipsel_==0)disablewrite_address_watch;if(dflags[3]&&(($time-time_write_begin)<$display("I8251A(%h)at%d:***writewidthtime_dbus_setup=if(dflags[3]&&(($time-time_write_end<$display("I8251A(%h)at%d:***dataholdviolationoninstance_id Timingviolation:address(comdat_andchipsel_)mustbe stablethroughoutwrite taskwrite_address_watch;@(comdat_orchipsel_)//ifthe"address"if(write_==0) //andwrite_didnotchangeatthesametimeif(dflags[3])$display("I8251A(%h)at%d:***addressholderroroninstance_id,/*Timingviolation:minimumofTRVclkcyclesbetweenwrites*/always@(negedgewrite_)if(chipel_==0)if(dflags[3]&&between_write_clks<$display("I8251A(%h)at%d:***betweenwriterecoveryalways@(negedgerepeat(`TRV)@(posedgeclk)between_write_clks=between_write_clks+1;/**Timingysisforresetsequence Timingviolation:resetpulsemustbe6clkcyclesalways@(posedgereset)begin:reset_blockrepeat(6)@(posedgeclk);//external->always@(negedgereset)if(dflags[3]&&$display("I8251A(%h)at%d:***resetpulsetooshort",instance_id$time);//lackofdisablereset_block;/***BEHAVIORAL /*Resetsequence*/begin//power-onreset->always@resete$display("I8251A(%h)at%d:performingresetinstance_id,status=4;//onlytxeissettxd=1;//lineatmarkstateuponresetuntildatais//assignnotallowedforstatus

//syndatisresettooutputlowsync_to_transmit=1;//transmitsyncchar#1whensyncaretransmitbetween_write_clks=`TRV;disableread_address_watch;disablewrite_address_watch;disabletrans1;disabletrans2;disabletrans3;disabletrans4;disablercv_blk;disablesync_hunt_blk;disabledouble_sync_hunt_blk;disableparity_sync_hunt_blk;disablesyn_receive_internal;disableasyn_receive;disablebreak_detect_blk;disablebreak_delay_blk;always@(negedgeread_)if(chipsel_==0)#(`TRD)//timefordatatoshowonthedatabusif(comdat_==0)//8251ADATA==>DATABUSrdatain=0;//noreceivebyteisreadyelse//8251ASTATUS==>DATAif(modreg[1:0]==2'b00)//ifsyncmode //resetsyndetuponstatusready//note:isonlyresetuponresetorrxd=1inasyncalways@(posedgeread_)#(`TDF)//datafromreadstaysonthebusafterposedgeread_always@(negedgewrite_)status[2]=0;//transmitternotemptyafterreceivingdatastatus[0]=0;//transmitternotreadyafterreceivingalways@(posedgewrite_) //readthecommand/datafromtheCPUif(chipsel_==0)if(comdat_==0) //DATABUS==>8251ADATAcase(command[0]&~ //ifitisnotcleartosendtdata_hold_full=1;//thenmarkthedataasreceivedandtdata_hold_cts=0;//thatitshouldbesentwhencts //ifitiscleartosendif(transmitter_reset)//…andthisis1stdatasinceresettdata_out_wait=1;// thenwaitforanegedgeontxctdata_out_full=1;// andtransmitthedata@(posedgeclk); //andsetthetxrdystatusbit

tdata_hold=dbus;//thenmarkthedataasbeingreceivetdata_hold_cts=1;//itesnotcts,//butdonotsetthetxrdystatusbit DATABUS==>case //case0:MODE //synchronousmodetstoptotal=0;//nostopbitforsynch. //synchronousmodebaudmx=1;//1Xbaudif(modreg[1:0]==2'b10)baudmx=16;if(modreg[1:0]==2'b11)//setupthestopbitsinclockststoptotal=tstoptotal+baudmx/2;tstoptotal=databits=modreg[3:2]+5;//bitsperchardata_mask=255>>(3-modreg[3:2]); //case1:1stSYNCCHAR-SYNC/*thesyn.characterwillbeadjustedtothemostsignificantbittosimplifysyn,hunt,syncmaskisalsosettotestthetopdatabits case(modreg[3:2])

sync1=sync1<<2; sync1=sync1<<1;

//ifindoublesynccharmode,get2

//ifinsinglesynccharmode,get1 //case2:2ndSYNCCHAR-SYNCcase(modreg[3:2])0:sync2=sync2<<1:sync2=sync2<<2:sync2=sync2<<1; //Trick:forcedelaytxtdypinifdtr_=! //ifsendbreakassign //settxd=0(ignores/override***** //laternon-assignassignmentdeassigntxd;status[5:3]=0;//ClearFrame/Parity/Overrunrts_=!command[5];if(command[6])->resete; //internalresetif(modreg[1:0]==0&&command[7])//ifsyncmodeandenterhuntdisablesyn_receive_internal;//disasblethesyncreceiverdisablesyn_receive_external;

//resetreceivebuffer-> //restartsyncmode->

repeat(`TTXRDY)@(posedgeclk);reg[7:0]serial_data;regparity_bit;alwayswait(tdata_out_full==1)begin:trans1$display("I8251A(%h)at%d:transmittingdata:instance_id,$time, //ifthedataarrivedanyoldtime@(negedgetxc_); //waitforanegedgeontxc_//butifastopbitwasjust//donotif(tstoptotal!=0) //ifasyncmode... //thensendastartbit1strepeat(baudmx)@(negedgetxc_); //sendallstart,databitsrepeat(baudmx)@(negedgetxc_);if(modreg[4]) //ifparityisenabled...parity_bit=^(tdata_out&if(modreg[5]==0)parity_bit=~parity_bit;//odd

repeat(baudmx)@(negedge if(tstoptotal!=0) //ifsyncmode //thensendoutthestopbit(s @(negedgetxc_);tdata_out_full=0;//blockthisroutineuntildata/syncchartobe//isimmediaytransferredto- //decidewhatdatashouldbesent(data/sync/stopeventalways@txende //endoftransmitteddata/synccharacterbegin:trans2case(command[0]& //ifitsisnotnow//butdatawasreceivedwhileitwasif(tdata_hold_full&&-> //thensendthedata- //elsesendsyncchar(s)or1stop //ifitsisnowif(tdata_hold_full)//ifacharacterhasbeen//butnowyetransmitted->transmit_held_data_e;//thensendthedatachar //else(nocharacterhasbeenreceived->transmitter_idle_e;//sendsyncchar(s)or1stopalways@(transmitter_idle_e) //iftherearenodatacharstosend...,begin:trans3 //mardtransmitterasbeingemptyif(tstoptotal!=0||command[0]==0||cts_//ifasyncmodeorafteraresetorTxEnable=falseorcts=falseif$display("I8251A(%h)at%d:transmittingdata:1(stopinstance_id,$time); //thensendout1stopbitandmakeanywrites //gototdata_holdrepeat(baudmx)@(negedge- //ifsyncmodecase(sync_to_transmit)tdata_out=sync1>>(8- //withoutwaitingonnegedgetif(modreg[7]==0)//ifdoublesyncmodesync_to_transmit=2;//send2ndsyncafter1sttdata_out=sync2>>(8-tdata_out_wait=0;//withoutwaitingonnegedgettdata_out_full=1;sync_to_transmit= //send1stsyncchar

always@(transmit_held_data_e)//ifacharacterhasbeenreceived*****add()begin:trans4 //butnottransmitted...tdata_out_wait=0; //thendonotwaitonnegedgetxctdata_out_full=1; //andsendthecharimmediaytdata_hold_full=0;repeat(`TTXRDY)@(posedgestatus[0]= //andsetthetxrdystatus//*************************RECEIVERPORTIONOFTHE8251A//dataisreceivedatleadingedgeoftheclockeventbreak_detect_e, event //huntforthe1stsynchunt_sync2_e,//huntforthe2ndsyncchar(doublesyncmode)sync_hunted_e,//syncchar(s)wasfound(onabitalignedbasisexternal_syndet_watche;//externalsyncmode:wheneversyndetpin//goeshigh,setthesyndetstatusalways@start_receiver_ebegin:rcv_blkreceive_in_progress=1;case(modreg[1:0])2'b00:if(modreg[6]==0)//ifinternalsyndetmode...if$display("I8251A(%h)at%d:startinginternalsyncreceive",instance_id,$time);if(dflags[5]&&if(modreg[7]==1)//ifenterhuntmode$display("I8251A(%h)at%d:receiverwaitingonsyndet",instance_id,$time);->hunt_sync1_e;//startsearchforsyncchar(s@(posedgesyndet);

$display("I8251A(%h)at%d:receiverDONEwaitingonsyndet",instance_id,$time);

//startsyncmode$display("I8251A(%h)at%d:startingexternalsyncreceive",instance_id,$time);if(dflags[5]&&$display("I8251A(%h)at%d:huntingforsyncs",instance_id,$time);- //wheneversyndetpingoesto//setsyndetstatusif(command[7]==1)

//assemblecharswhilewaiting@(posedgesyndet) //afterrisingedgeofsyndet@(negedgesyndet) //waitforfallingedgedisableexternal_syn_hunt_blk; //startexternalsyncmodereceivingdefault://ifasyncmode...$display("I8251A(%h)at%d:startingasynchronousreceiver",instance_id,$time); //startcheckforrcd=0toolong //andstartasyncmodereceiver

/*****EXTERNALSYNCHRONOUSMODERECEIVEtasksyn_receive_rexternal;repeat(databits)//Whetherinhuntmodeornot,assembleacharacter

@(posedgereceivebuf={rcd,

//receiveandcheckparitybit,ifanymark_char_received;//setrxrdyline,ifenalbedalways@(external_syndet_watche)@(posedgerxc_)/****INTERNALSYNCHRONOUSMODERECEIVE Huntforthesync (ifinsynchronousinternalsyncdetectmode)/*Syndetissethighwhenthesync(s)arefoundalways@(hunt_sysnc1_e)//searchfor1stsynccharinthedatastreambegin:sync_hunt_blkwhile(!(((receivebuf^sync1)&syncmask)===8'b0000_0000))@(posedgereceivebuf={rcd,if(modreg[7]==0)//ifdoublesync->hunt_sync2_e;//checkfor2ndsyncchardirectlyagter

-> //ifsinglesyncmode,synchuntisalways@(hunt_sync2_e)//findthesecondsynchronouscharacterbegin:double_sync_hunt_blk@(posedgerxc_)if((receivebuf^sync2)&->sync_hunted_e;//ifsync2followedsyn1,synchuntis->hunt_sync1_e;//elsehuntforsync1

//Note:thedatastream[sync1sync1sync2]willhavesync//Suppose //Then[110011001100sync2]willNOTbedetected//Ingeneral:neverletasuffixofsync1alsobeaprefixofalways@(sync_hunted_e)begin:parity_sync_hunt_blkstatus[6]=1;//setsyndetstatusbit(synccharsdetectedtasksyn_receive_internal;repeat(databits)//nolongerinhuntmodesoreadentirecharsand //thenlookforsyncs(insteadofonbitboundaries)@(posedgerxc_)case //iflookingfor2ndsyncchar...if(((receivebuf^sync2)&syncmask)===0) //...and2ndsynccharisfoundsync_to_receive=1;//thenlookofr1stsync(ordata) //andmarksyncdetectedelseif(((receivebuf^sync1)&syncmask)===0) //...and1stsynccharisfoundsync_to_receive=2;//thenlookfor2ndsyncif(((receivebuf^sync1)&syncmask)===0)//...and1stsyncisfoundif(modreg[7]==0)//ifdoulbesyncmodesync_to_receive=2;//lookfor2ndsynctofoll

//anddatawasfound,do

//receiveandcheckparitybit,ifanytasksyn_receive_external;//havenotfoundtheoriginalprogramstaskget_and_check_parity;receivebuf=receivebuf>>(8-databits);if(modreg[4]==1)@(posedgeif((^receivebuf^modreg[5]^rcd)!=1)taskmark_char_received; //ifreceivingisenabledrxrdy=1;//setreceivereadstatusbitstatus[1]=1;//ifpreviousdatawasnotreadif(rdatain==1)overrun_error;//overrunerror //latchthedatardatain=1;//markdataasnothavingbeenreadend$display("I8251A(%h)at%d:receivedata:%b",/*************ASYNCHRONOUSMODERECEIVER/*CHECKFORBREAKDETECTION(RCDLOWTHROUGH2/*RECEIVESEQUENCESINTHEASYNCHRONOUSMODEalways@(break_detect_e)begin:break_detect_blk#1/*tobesurebreak_delay_clkiswaitingonbreak_delay_eafterittriggeredbreak_detect_e*/->break_delay_e;//start+databits+parity+stopbitbreakcount_period=1+databits+modreg[4]+(tstoptotal!=0);//thenumberofrxcperiodsneededfor2receivesequencebreakcount_period=2*breakcount_period*baudmx;//ifrcdstayslowthrough2//(start,data,prity,stop)sequences...@(posedgestatus[6]=1;//...thensetbreakdetect(status[6])always@(break_delay_e)begin:@(posedgercd)//butifrcdgoeshighduringthattimebegin:break_delay_blkdisablestatus[6]=0;//...thensetthebreakdetectlow@(negedgercd)//andwhenrcdgoeslowagain...- //...startthebreakdetection/********ASYNCHRONOUSMODERECEIVETASK******************/taskasyn_receive;@(negedgercd)//thereceivelinewenttozero,maybeastartbitt=baudmx/2;if(baudmx==1) t)@(posedgerxc_);//afterhalfabit...if(rcd==0)//ifitisstillastartbitt=repeat(databits)//receivethedatabits t)@(posedgerxc_);#1receivebuf={rcd,receivebuf[7:1]};repeat t)@(posedge//shiftthedatatothelowpartreceivebuf=receivebuf>>(8-databits);if(modreg[4]==1)///ifparityisenabledif((^receivebuf^modreg[5]^rcd)!=1) //checkforaparityerror t)@(posedge#1if(rcd==0) //ifmiddleofstopbitis0frame_error;//frameerror(shouldbe1)

[例2].“商业化”的虚拟模块之二:In8085a微处理器的行为描述模In8085a微处理器仿真模块的Verilog源代码modulein(clock,x2,resetff,sodff,sid,trap,rst7p5,rst6p5,rst5p5,intr,intaff,ad,a,s0,aleff,writeout,readout,s1,iomout,ready,nreset,clockff,hldaff,hold);reg dflags=//diag//1=trace//2=traceINandOUT//3=traceinstructionresetff,sodff,intaff,s0,writeout,readout,s1,iomout,clockff,hldaff;inout[7:0]ad,a;

clock,x2,sid,trap,rst7p5,rst6p5,rst5p5,intr,ready,nreset,hold; //program //stack //address //interruptmaskand // // // // // // // // //data

//addresslatchenable //statusline0 //statusline1 //holdacknowledge //internalhold //interruptacknowledge //trapinterrupt //trapexecutionforRIMinstruction//previousstateofinterruptenableflag //interruptacknowledgeinprogressvalidint,//interruptpending //haltrequest //resetoutputclockff,//clockoutput//serialoutputdata //readrequestsignal //writerequestsignal //i/omemoryselectacontrol,//addressoutputcontroldcontrol,//dataoutputcontrol //datasource //signcondition //zerocondition //auxcarryconditioncode //parityconditioncode //carrycondition

s0=s0ff&~haltff,s1=s1ff&ad=dcontrol?(s?data:addr[7:0]):'bz,a=acontrol?addr[15:8]:'bz;

readout=acontrol?read:'bz,writeout=acontrol?write:'bz,iomout=acontrol?iomff:'bz;ec1,//clock1eventec2;//clock2//internalclockgenerationalwaysbegin@(posedgeclock)->ec1;@(posedgeclock)->integerinstruction;//instructioncountinitialinstruction=0;alwaysbegin:run_processor#1reset_sequence; //Instructions //inparallelwithreset@ec2disablerun_processor;//control.Resetwill //disable //andalltasks//functionsenabled//itwhennresetsettotaskreset_sequence;$display("Performing8085(%m)resetsequence");read=1;write=resetff=dcontrol=@ec1//synchronizedwithclock1eventpc=0;ir=intmask[3:0]=intaff=acontrol=aleff=intmask[7:5]=sodff=trapff=trapi=iomff=haltff=holdff=hldaff=validint=int=0;

//Check,inparallelwiththedisablerun_processor;//resetsequence,that //remainsatwait(nreset)@ec1@ec2resetff=/*fetchandexecuteinstructions*/taskexecute_instructions;foreverinstruction=instruction+1;$display("executinginstruction%d",@ec1//clockcycle1addr=pc;s=iomff=read=write=acontrol=dcontrol=aleff=1;if(haltff)haltff=s0ff=s1ff=0;elses0ff=s1ff=

aleff=@ec1//clockcycle2read=0;dcontrol=@ec2//clockcycle3read=1;data=ad;ir=ad;@ec1//clockcycle4if(do6cycles(ir))begin//doa6-cycleinstructionfetch@ec1@ec2//conditionalclockcycle5if(hold)beginholdff=1acontrol=dcontrol=0;@ec2hldaff=1;else

holdff=hldaff=@ec1;//conditionalclockcycleif(holdff)holdit;while(hold)@ec2beginacontrol=0;dcontrol=

holdff=hldaff=0;if(validint)functiondo6cycles;input[7:0]ireg;do6cycles=0;0,4,5,7:if(ireg[7:6]==3)do6cycles=1:if((ireg[3]==1)&&(ireg[7:5]==7))do6cycles=3:if(ireg[7:6]==0)do6cycles=1;taskcheckint;if((intmask[3]==1)&&(intmask[1]==0))intmask[6]=intmask[6]=if((intmask[3]==1)&&(intmask[0]==0))intmask[5]=intmask[5]=if({intmask[7],intmask[3:2]}==6)intmask[4]=1;intmask[4]=validint=(intmask[6:4]==7)|trapff|//concurentlywithexecuting//processprimaryinputsforprocessorinterruptalways@(posedgetrap)trapff=1;always@(negedgetrap)trapff=0;always@(posedgerst7p5)intmask[7]=1;/*checkconditionofreadyandholdinputs*/taskready_hold;while(!ready)@ec2;if(hold)beginholdff=1;@ec2hldaff=1;/*hold*/while(hold)@ec2beginacontrol=0;dcontrol=

holdff=0;@ec2hldaff=0;/*haltrequest*/taskhaltreq;foreverbeginif(validint)beginhaltff=0;disablehaltreq;elsewhile(hold)@ec2hldaff=1;hldaff=0;

@ec1dcontrol=acontrol=0;/*memoryread*/taskmemread;output[7:0]rdata;input[15:0]raddr;

addr=raddr;s=0;acontrol=dcontrol=1;iomff=int;s0ff=int;s1ff=1;aleff=aleff=

dcontrol=0;

intaff=read=

intaff=read=1;rdata=ad;if(holdff)/*memorywrite*/taskmemwrite;input[7:0]wdata;input[15:0]waddr;

aleff=s0ff=s1ff=s=iomff=0;addr=waddr;acontrol=dcontrol=aleff=

data=wdata;write=0;s=write=if(holdff)/*readsfromani/oport*/taskioread;input[7:0]sa;aleff=s0ff=s1ff=s=iomff=addr={sa,sa};acontrol=1;dcontrol=aleff=

dcontrol=0;intaff=read=

intaff=read=1;acc=ad;$display("IN data=%h",sa,/*writesintoi/oport*/taskiowrite;input[7:0]sa;addr={sa,aleff=s0ff=s1ff=s=iomff=acontrol=dcontrol=aleff=

data=acc;write=0;s=$display("OUT data=%h",sa,

write=1;if(holdff)holdit;taskinterrupt;if(hold)beginholdff=1;@ec2hldaff=if(trapff)inte=intmask[3];trapi=1;pc='h24;trapi=trapff=elseif(intmask[7])beginpc='h3c;intmask[7]=0;elseif(intmask[6])beginpc='h34;intmask[6]=0;elseif(intmask[5])beginpc='h2c;intmask[5]=0;elseif(intr)aleff=s0ff=s1ff=s=iomff=1;addr=pc;read=1;write=acontrol=dcontrol=

@ec2aleff=0;@ec1dcontrol=0;repeat(4)@ec1;push2b(pc[15:8],/*executeinstruction*/taskdo_instruction;$display("C%bZ%bM%bE%bI%bA=%hB=%h%hD=%h%hH=%h%hS=%hP=%hIR=%h",cc,cz,cs,cp,cac,acc,regb,regc,regd,rege,regh,regl,sp,pc,ir);pc=pc+@ec2//instructiondecodesynchronizedwithclock2event

0:1:if(ir[3])addhl;elselrpi;2:sta_lda;3:4:5:6:4:1:if(ir[3])decode1;elsepop;3:decode2;5:if(ir[3])decode3;elsepush;6:immacc;/*moveregistertoregister*/taskmove;0:rmov(regb);//MOV-,B1:rmov(regc);//MOV-,C2:rmov(regd);//MOV-3:rmov(rege);//MOV-,E4:rmov(regh);//MOV-,H5:rmov(regl);//MOV-,Lif(ir[5:3]==6)haltff=1;//HLTelsebegin//MOV-,Mmemread(data,{regh,regl});7:rmov(acc);//MOV-,A/*enabledonlybymove*/taskrmov;input[7:0]fromreg;0:regb=fromreg;//MOVB,-1:regc=fromreg;//MOVC,-2:regd=fromreg;//MOVD,-3:rege=fromreg;//MOVE,-4:regh=fromreg;//MOVH,-5:regl=fromreg;//MOVL,-6:memwrite(fromreg,{regh,regl});//MOVM,-7:acc=fromreg;//MOVA,-/*moveregisterandmemoryimmediate*/taskmovi;0:memread(regb,pc);//MVIB1:memread(regc,pc);//MVIC2:memread(regd,pc);//MVID3:memread(rege,pc);//MVIE4:memread(regh,pc);//MVIH5:memread(regl,pc);//MVIL6://MVIMmemread(data,pc);memwrite(data,{regh,regl});

7:memread(acc,pc);//MVIApc=pc+/*incrementregisterandmemorycontents*/taskinr;0:nc(regb);//INRB1:nc(regc);//INRC2:nc(regd);//INRD3:nc(rege);//INRE4:nc(regh);//INRH5:nc(regl);//INRL6://INRMmemread(data,{regh,regl});memwrite(data,{regh,7:nc(acc);//INRA/*enabledonlyfromin*/tasknc;inout[7:0]sr;cac=sr[3:0]=='b1111;sr=sr+1;/*decrementregisterandmemorycontents*/taskdcr;0:dodec(regb);//DCRB1:dodec(regc);//DCRC2:dodec(regd);//DCRD3:dodec(rege);//DCRE4:dodec(regh);//DCRH5:dodec(regl);//DCR6://DCRmemread(data,{regh,regl});memwrite(data,{regh,7:dodec(acc);//DCRA/*enabledonlyfromde*/taskdodec;inout[7:0]sr;cac=sr[3:0]==0;sr=sr-1;/*registerandmemoryaccinstructions*/taskrmop;0:1:2:3:4:5:memread(data,{regh,regl});7:doacci(acc);/*immediateaccinstructions*/taskimmacc;memread(data,

pc=pc+1;/*operateonaccumulator*/taskdoacci;input[7:0]sr;reg[3:0]null4;reg[7:0]0://ADD{cac,null4}=acc+{cc,acc}={1'b0,acc}+sr;1://ADC{cac,null4}=acc+sr+{cc,acc}={1'b0,acc}+sr+cc;2://SUB{cac,null4}=acc-{cc,acc}={1'b0,acc}-sr;3://SBB{cac,null4}=acc-sr-{cc,acc}={1'b0,acc}-sr-cc;4://ANAacc=acc&sr;cac=1;cc=5://XRAacc=acc^sr;cac=0;cc=0;6://ORAacc=acc|sr;cac=0;cc=0;7://CMP{cac,null4}=acc-{cc,null8}={1'b0,acc}-sr;/*rotateaccandspecialinstructions*/taskracc_spec;0://acc={acc[6:0],acc[7]};cc=acc[7];1://acc={acc[0],acc[7:1]};cc=acc[0];2://{cc,acc}={acc,3://{acc,cc}={cc,4://DAA,decimaladjustif((acc[3:0]>9)||cac)acc=acc+if((acc[7:4]>9)||cc){cc,acc}={1'b0,acc}+5://acc=6://cc=7://cc=/*incrementanddecrementregisterpair*/taskinx_dcx;0:{regb,regc}={regb,regc}+1;//INXB1:{regb,regc}={regb,regc}-1;//DCXB2:{regd,rege}={regd,rege}+1;//INXD3:{regd,rege}={regd,rege}-1;//DCXD4:{regh,regl}={regh,regl}+1;//INXH5:{regh,regl}={regh,regl}-1;//DCXH6:sp=sp+ //INX7:sp=sp-1; //DCXSP/*loadregisterpairimmediate*/tasklrpi;0:adread({regb,regc});//LXIB1:adread({regd,rege});//LXID2:adread({regh,regl});//LXIH3: //LXI/*addintoregh,reglpair*/taskaddhl;0:{cc,regh,regl}={1'b0,regh,regl}+{regb,regc};//DADB1:{cc,regh,regl}={1'b0,regh,regl}+{regd,rege};//DADD2:{cc,regh,regl}={1'b0,regh,regl}+{regh,regl};//DADH3:{cc,regh,regl}={1'b0,regh,regl}+ //DAD/*storeandloadinstruction*/tasksta_lda;reg[15:0]0:memwrite(acc,{regb,regc});//STAXB1:memread(acc,{regb,regc});//LDAXB2:memwrite(acc,{regd,rege});//STAXD3:memread(acc,{regd,rege});//LDAX4://memwrite(regl,ra);memwrite(regh,ra+1);5://memread(regl,ra);memread(regh,ra+1);6://memwrite(acc,ra);end//memread(acc,ra);/*pushregisterpairfromstack*/taskpush;0:push2b(regb,regc);//PUSHB1:push2b(regd,rege);//PUSHD2:push2b(regh,regl);//PUSH3:push2b(acc,{cs,cz,1'