数字电路与逻辑设计 基于VHDL的数字逻辑设计2

基于VHDL的数字逻辑设计时序逻辑部分二、常用时序逻辑电路设计（1）触发器设计（D）（2）计数器设计（分频器）（3）移位寄存器设计（4）状态机设计：序列检测器

（1）触发器设计DQCPCPDQn+1无变化XQn0->1000->111D触发器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdffISPORT(cp,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDdff;ARCHITECTUREaOFdffISBEGINprocess(cp)beginifcp'eventandcp='1'thenq<=d;endif;endprocess;ENDa;(2)-A简单计数器设计计数器CLKQ3Q2Q1Q0四位加计数器LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenq<=q+1;

endif;

endprocess;ENDa;四位加计数器计数器CLKCLR(2)-B带同步清零、同步置数功能的计数器LDQ3Q2Q1Q0D3D2D1D0控制信号CLR、LD：具有更高优先级LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenif(clr='1')then

q<="0000";elsif(ld='1')thenq<=d;

elseq<=q+1;

endif;endif;endprocess;ENDa;计数器CLKCLR(2)-C带异步清零、同步置数功能的计数器LDQ3Q2Q1Q0D3D2D1D0LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

else

if(clk'eventandclk='1‘)

thenif(ld='1')then

q<=d;

elseq<=q+1;

endif;

endif;endif;

endprocess;ENDa;(2)-D带进位计数器设计计数器CLKQ3Q2Q1Q0四位加计数器COUTLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0);cout:outstd_logic);ENDcounter;ARCHITECTUREaOFcounterISBEGINprocess(clk) variabletmp:std_logic_vector(3downto0);begin

if(clk'eventandclk='1')thenq<=q+1;tmp:=q+1;

if(tmp=15)thencout<='1';

elsecout<='0';

endif;

endif;endprocess;ENDa;(3)分频器设计Tclk=1usTcout=10us计数器就是对时钟脉冲计数，同时计数器还是一个分频器。（4）移位寄存器设计4位右移移位寄存器Reset:异步清零右移移位寄存器dinresetclkQAQBQCQDlibraryieee;useieee.std_logic_1164.all;ENTITYshifterISPORT(

din:instd_logic;reset,clk:instd_logic;QA,QB,QC,QD:bufferstd_logic);

ENDshifter;ARCHITECTUREbehaveOFshifterISBEGINProcess(reset,clk)Begin

if(reset='1')

then

QA<='0';QB<='0';QC<='0