静态时序分析基本原理和时序分析模型

Quartus®IISoftwareDesignSeries:TimingAnalysis-Timinganalysisbasics第一页，共二十七页。2ObjectivesDisplayapleteunderstandingoftiminganalysis第二页，共二十七页。3Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirementsCatchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boardtestingDesignermustentertimingrequirements&exceptionsUsedtoguidefitterduringplacement&routingUsedtopareagainstactualresultsINCLKOUTDQCLRPREDQCLRPREbinationaldelaysCLR第三页，共二十七页。4TimingAnalysisBasicsLaunchvs.latchedgesSetup&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackanalysisI/OanalysisRecovery&removalTimingmodels第四页，共二十七页。5Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous –clock&datapathsAsynchronous* –clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters第五页，共二十七页。6Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge: theedgewhich“launches”thedatafromsourceregisterLatchEdge: theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1cycle)第六页，共二十七页。7Setup&HoldSetup: Theminimumtimedatasignalmustbestable BEFOREclockedgeHold: Theminimumtimedatasignalmustbestable AFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.第七页，共二十七页。8DataArrivalTimeDataArrivalTime=launchedge+Tclk1+Tco+TdataCLKREG1.CLKTclk1DataValidREG2.DTdataLaunchEdgeDataValidREG1.QTcoThetimefordatatoarriveatdestinationregister’sDinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdata第八页，共二十七页。9ClockArrivalTimeClockArrivalTime=latchedge+Tclk2

CLKREG2.CLKTclk2LatchEdgeThetimeforclocktoarriveatdestinationregister’sclockinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2第九页，共二十七页。10DataRequiredTime-SetupDataRequiredTime=ClockArrivalTime-Tsu-SetupUncertaintyCLKREG2.CLKTclk2LatchEdgeTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterTsuDataValidREG2.DDatamustbevalidhereREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Tsu第十页，共二十七页。11DataRequiredTime-HoldDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintyCLKREG2.CLKTclk2LatchEdgeTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterThDatamustremainvalidtohereDataValidREG2.DREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Th第十一页，共二十七页。12Tclk2SetupSlackREG2.CLKThemarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthelatchingrequirement.TsuCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTco

SetupSlackLaunchEdgeLatchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Tsu第十二页，共二十七页。13SetupSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetSetupSlack=DataRequiredTime –DataArrivalTime第十三页，共二十七页。14HoldSlackREG2.CLKTclk2Themarginbywhichtheholdtimingrequirementismet.Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge.ThCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTcoHoldSlackLatchEdgeNextLaunchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Th第十四页，共二十七页。15HoldSlack(cont’d)PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmetHoldSlack=DataArrivalTime –DataRequiredTime第十五页，共二十七页。16FPGA/CPLDorASSPASSPorFPGA/CPLDI/OAnalysisAnalyzingI/OperformanceinasynchronousdesignusesthesameslackequationsMustincludeexternaldevice&PCBtimingparametersreg1PREDQCLRreg2PREDQCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCDataArrivalPathDataArrivalPathDataRequiredPath*Representsdelayduetocapacitiveloading第十六页，共二十七页。17Recovery&RemovalRecovery: Theminimumtimeanasynchronoussignalmust bestableBEFOREclockedgeRemoval: Theminimumtimeanasynchronoussignalmust bestableAFTERclockedgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC第十七页，共二十七页。18Asynchronous=Synchronous?AsynchronouscontrolsignalsourceisassumedsynchronousSlackequationsstillapplydataarrivalpath=asynchronouscontrolpathTsu

≈Trec;Th

≈TremExternaldevice&boardtimingparametersmaybeneeded(Ex.1)ASSPreg1PREDQCLRFPGA/CPLDreg2PREDQCLROSCFPGA/CPLDreg1PREDQCLRreg2PREDQCLRExample1Example2DataarrivalpathDataarrivalpathDatarequiredpathDatarequiredpath第十八页，共二十七页。19WhyAreTheseCalculationsImportant?CalculationsareimportantwhentimingviolationsoccurNeedtobeabletounderstandcauseofviolationExamplecausesDatapathtoolongRequirementtooshort(incorrectanalysis)

Largeclockskewsignifyingagatedclock,etc.TimeQuesttiminganalyzerusesthemEquationstocalculateslackTerminology(launchandlatchedges,DataArrivalPath,DataRequiredPath,etc.)intimingreports第十九页，共二十七页。20TimingModelsinDetailQuartusIIsoftwaremodelsdevicetimingattwoPVTconditionsbydefaultSlowCornerModelIndicatesslowestpossibleperformanceforanysinglepathTimingforslowestdeviceatmaximumoperatingtemperatureandVCCMINFastCornerModelIndicatesfastestpossibleperformanceforanysinglepathTimingforfastestdeviceatminimumoperatingtemperatureandVCCMAXWhytwocornertimingmodels?EnsuresetuptimingismetinslowmodelEnsureholdtimingismetinfastmodelEssentialforsourcesynchronousinterfacesThirdmodel(slow,min.temp.)availableonlyfor65nmandsmallertechnologydevices(temperatureinversionphenomenon)第二十页，共二十七页。21GeneratingFast/SlowNetlistSpecifyoneofthedefaulttimingmodelstobeusedwhencreatingyournetlistDefaultistheslowtimingnetlistTospecifyfasttimingnetlistUse-fast_modeloptionwithcreate_timing_netlistmandChooseFastcornerinGUIwhen executingCreateTimingNetlist

fromNetlistmenuCANNOTselectfastcorner fromTasksPane第二十一页，共二十七页。22SpecifyingOperatingConditionsPerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistTakesprecedenceoveralreadygeneratednetlistRequiredforselectingslow,min.temp.modelandothermodels(industrial,military,etc.)dependingondeviceUseget_available_operating_conditionstoseeavailableconditionsfortargetdevice第二十二页，共二十七页。ReferenceDocumentsQuartusIIHandbook,Volume3,Chapter7TheQuartusIITimeQuestTimingAnalyzeraltera/literature/hb/qts/qts_qii53018.pdfQuickStartTutorialaltera/literature/hb/qts/ug_tq_tutorial.pdfCookbookaltera/literature/manual/mnl_timequest_cookbook.pdf第二十三页，共二十七页。ReferenceDocumentsSDCandTimeQuestAPIReferenceManualaltera/literature/manual/mnl_sdctmq.pdfAN481:ApplyingMulticycleExceptionsintheTimeQuestTimingAnalyzeraltera/literature/an/an481.pdfAN433:ConstrainingandAnalyzingSource-SynchronousInterfacesaltera/literature/an/an433.pdf第二十四页，共二十七页。25Instructor-LedTraining

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altera/trainingViewtrainingclassschedule®isterforaclassLearnMoreThroughTechnicalTraining第二十五页，共二十七页。26AlteraTechnicalSupportReferenceQuartusIIsoftwareon-linehelpQuartusIIHandbookConsultA