数字设计原理与实践：第六章 COMBINATIONAL LOGIC DESIGN PRACTICES-part 2

1CommonlyUsedMSICombinationalLogicDevice

（常用中规模组合逻辑器件）Decoders(编码器)Encoders(译码器)Multiplexers(多路复用器)ParityCircuits(奇偶校验)Comparators(比较器)Adders(加法器)

2DecoderandEncoder

(译码器和编码器)Multiple-Input,Multiple-OutputLogicCircuit(多输入、多输出电路)EnableInputsmustbeAssertedtoperformNormalMappingFunction(使能输入有效才能实现正常映射功能)EnableInputs(使能输入)(输入编码)(输出编码)Map映射InputCordWordOutputCordWord

3Decoder（译码器）

NormallyOutputCodehasMorebitsthanitsInputCode

(一般来说，输出编码比输入编码位数多)Encoder（编码器）

OutputCodehasFewerbitsthanitsInputCodecalledanEncoder(输出编码比输入编码位数少，则常称为编码器)DecoderandEncoder

(译码器和编码器)

4MostCommonlyUsedCase

(一种最常用的情况)使能输入编码输出编码Map映射Decoder（译码器）Encoder（编码器）N-BitBinaryCode(n位二进制码)2n

中取1码使能输入编码输出编码Map映射2n中取1码n位二进制码(One-out-of2n)

56.4Decoder（译码器）BinaryDecoder

(二进制译码器)2-to-4DecoderY0Y1Y2Y3I0I1EN

0XX00001000001101001011001001111000(2-4二进制译码器真值表)TruthTablefora2-to-4BinaryDecoderInputsENI1I0OutputsY3Y2Y1Y0OutputsY3Y2Y1Y0OutputsY3Y2Y1Y0

6

0XX00001000001101001011001001111000InputsENI1I0OutputsY3Y2Y1Y0(2-4二进制译码器真值表)Y0=EN·(I1’·I0’)Y1=EN·(I1’·I0)Y2=EN·(I1·I0’)Y3=EN·(I1·I0)Yi=EN·mi6.4Decoder（译码器）TruthTablefora2-to-4BinaryDecoder

7二进制译码器n个输入有2n种状态分析下图所示电路功能Y0-L&&&&&&&&E1-LE2-LE3&&A2A1A0111111Y1-LY2-LY3-LY4-LY5-LY6-LY7-L

8逻辑函数表达式由电路图可求逻辑函数表达式

90000000100000010000001000000100000010000001000000100000010000000000001010011100101110111I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8二进制译码器真值表)3-to-8DecoderI2I1I0Y0Y1Y711111110111111011111101111110111111011111101111110111111011111116.4Decoder（译码器）TruthTablefora3-to-8BinaryDecoderYi=EN·miYi_L=Yi’=(EN·mi

)’EN=G1·G2A·G2B=G1·G2A_L’·G2B_L’

10

LogicSymbolsforLarge-ScaleElement(大规模元件的逻辑符号)Y0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139G_LABY0_LY1_LY2_LY3_L

11The74x1383-to-8Decoder

(3-8译码器74x138)G1G2A_LG2B_LY3=G1·G2A·G2B·C’·B·AEnable(使能)Select(选择)Y3_L=Y3’=(G1·G2A_L’·G2B_L’·C’·B·A)’=

G1’+G2A_L+G2B_L+C+B’+A’

12N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L用74x138设计4-16译码器思路：16个输出需要

片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2任何时刻只有一片在工作。4个输入中，哪些位控制片选哪些位控制输入CascadingBinaryDecoders

(级联二进制译码器）

13Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138设计5-32译码器)Howmany74x138chipstobeusedwith32outputs?(32个输出需要多少片74x138？)Controlthatonlyonechipworksinanytime(控制任何时刻只有一片工作)

——

UsetheEnableInputs(利用使能端)

14Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?

(思考：用74x138设计5-32译码器)Controlinputsofthreelow-orderbitsofa5-bitcodeword(5个输入的低3位控制输入)Controlchipsoftwohigh-orderbitsofa5-bitcodeword

(5个输入的高2位控制片选)

Use2-to-4Decoder(利用2-4译码器)

图6－37

15补充：用译码器和逻辑门实现逻辑函数F=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)对于二进制译码器：Yi=EN·mi

当使能端有效时，Yi=mi对低电平有效输出：Yi_L=Yi’当使能端有效时，Yi_L=mi’=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138

16补充：用译码器和逻辑门实现逻辑函数ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)当使能端有效时Yi=mi

17补充：用译码器和逻辑门实现逻辑函数ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)

18=M1·

M2·M4·M5=m1’

·

m2’

·m4’

·m5’F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF

19BCDDecoder(二－十进制译码器)Inputs:4-bitBCDcodeOutputs:1-out-of10CodeY0Y9I0I1I2I3多余的6个状态如何处理？输出均无效：拒绝“翻译”作为任意项处理

——电路内部结构简单

20二-十进制译码器00000001001000110100010101100111100010011010101111001101111011110111111111101111111111011111111110111111111101111111111011111111110111111111101111111111011111111110111111111111111111111111111111111111111111111111111111111111I3

I2

I1

I00123456789Y0_L

Y9_L伪码任意项

21Seven-SegmentDecoders

(七段显示译码器)abcdefgdp公共阴极abcdefgdpNormallyuse(常用的有)：Light-EmittingDiodes（LED,半导体数码管）Liquid-CrystalDisplay（LCD,液晶数码管）abcdefgdp公共阳极

22Inputcode:4-bitBCD

[输入信号：BCD码（用A3A2A1A0表示）]OutputCode:Seven-SegmentCode[输出：七段码（的驱动信号）a~g]1表示亮(On)，0表示灭(Off)abcdefg111111011011011011111Seven-SegmentDecoders

(七段显示译码器)

238421BCD码-七段译码驱动电路设计XXXXXX9876543210XXXXXXX1111XXXXXXX0111XXXXXXX1011XXXXXXX0011XXXXXXX1101XXXXXXX010111011111001111111100010000111111011111010110110110110101100110001010011111100101101101000000110100001111110000gfedcbaDCBA七段数码输出（共阴极）BCD码输入

24XX1110XXXX11110111110010110100ABCD卡诺图化简XX1110XXXX11111011110010110100ABCDXX1110XXXX111111011110010110100ABCDXX1110XXXX1111011110010110100ABCD

25卡诺图化简练习：画电路图思考题：4位循环码的七段数码管显示电路如何设计？XX1110XXXX1111101110010110100ABCDXX1110XXXX111110110010110100ABCDXX110XXXX11101110010110100ABCD

266.5Encoder（编码器）BinaryEncoderA0A1A2I0I1I71000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)

2nInputsnOut-putsTruthTablefora8-to-3Encoder

27Guarantee:

TheInputsareassertedatmost

oneatatime.

(前提：任何时刻只有一个输入端有效。)1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)6.5Encoder（编码器）TruthTablefora8-to-3Encoder

28A0=I1+I3+I5+I7A1=I2+I3+I6+I7A2=I4+I5+I6+I7Trouble:WhenmorethanOneInputsareasserted?(问题：当某时刻出现多个输入有效？)Priority（优先级）1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二进制编码器的真值表)6.5Encoder（编码器）TruthTablefora8-to-3Encoder

29PriorityEncoder

(优先编码器)A2A1A0IDLEI7I6I5I4I3I2I1I0ChangeI0～I7to

H0～H7,MakeSuretheInputsareassertedatmostoneatatime.

(将I0～I7转换为H0～H7，保证其中，任何时刻只有一个有效)Highest-Priority(数大优先)6.5Encoder（编码器）

30PriorityEncoder

(优先编码器)A2A1A0IDLEI7I6I5I4I3I2I1I0H7=I7H6=I6·I7’H5=I5·I6’·I7’…H0=I0·I1’·I2’·…·I6’·I7’A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7Highest-Priority(数大优先)6.5Encoder（编码器）

31PriorityEncoder

(优先编码器