spi进阶1之ewen功能练习参考代码

at93c46_ewen模 test_at93c46_ewen模 和ASIC FPGA的。at93c46_ewen模moduleat93c46_ewen( input //reg;;;;reg work_flagreg[ reg cnt_sclkreg @(posedgeclkornegedgerst_n)begincnt_1us<=elseif(work_flag!=2'b0)begincnt_1us<=elsecnt_1us<=cnt_1us+elsecnt_1us<= @(posedgeclkornegedgerst_n)begincnt_sclk<=elseif(work_flag==2'b01)beginif(cnt_1us==99&&cnt_sclk==9)begincnt_sclk<=elseif(cnt_1us==99)begincnt_sclk<=cnt_sclk+1;else

cnt_sclk<= @(posedgeclkornegedgerst_n)begindout<=elseif(work_flag==2'b0&&wr)begindout<={3'b100,addr}; @(posedgeclkornegedgerst_n)beginwork_flag<=elseif(work_flag==2'b0&&wr)beginwork_flag<=2'b1;elseif(work_flag==2'b1&&cnt_1us==99&&cnt_sclk==9)beginwork_flag<=2'b10;elseif(work_flag==2'b10&&cnt_1us==99)beginwork_flag<=2'b00; @(posedgeclkornegedgerst_n)beginsk<=elseif(work_flag==2'b01)beginsk<=elseif(cnt_1us==99)sk<=1'b0;elsesk<= @(posedgeclkornegedgerst_n)begindi<=elseif(work_flag==2'b00&&wr)begindi<=1'b1;elseif(work_flag==2'b01&&cnt_1us==99)begindi<=

di<= @(posedgeclkornegedgerst_n)begincs<=elseif(work_flag==2'b00&&wr)begincs<=1'b1;elseif(work_flag==2'b01&&cnt_1us==99&&cnt_sclk==9)begincs<=1'b0; rdy=1'b0;elseif(|work_flag)rdy=

rdy=test_at93c46_ewen模`timescale1ns/1module parameterCYCLE =10;parameterRST_TIME=3 initialclk=0;initialbeginrst_n=rst_n=0;rst_