2014《数字逻辑设计》期末考试-试题及参考解答

1、学院姓名学号任课老师考场教室_选课号/座位号密封线以内答题无效 2013 -2014 二 末 A 卷课程名称：_数字逻辑设计及应用_ 考试形式： 闭卷考试时长：_120_分钟考试日期：20 14 年 07 月 10 日课程成绩构成：平时 30 % ， 期中 30 % ， 实验本试卷试题由_六_部分构成，共_8_页。0%， 期末 40 %题号得分合计得 分I. Fill out your answers in the blanks (3 X 10=30)1. A circuit with 10 flip-flops can store (states at most.10 ) bit binar

2、y numbers, that is, include (1024 或 2 )102. A 5-bit linear feedback shift-register (LFSR) counter with no self-correction can have (normal states.31 或 2 -1 )53. A modulo-24 counter circuit needs (5 ) D filp-flops at least. A modulo-500 counter circuit needs(3 ) 4-bit counters of74x163 at least.4. If

3、 an 74x148 priority encoder has its 1, 3, 4, and 5 inputs at the active level, the active LOW binary output is( 010 ) .5. State/output table for a sequential circuit is shown as Table 1. X is input andZ is output. Assume that theninitial state is S , if the input sequence is X = 01110101, the output

4、 sequence should be (11001100 或0110011000 ). 【可以确定的输出序列应该有 9 位】Table 1 State/output tableTable 2 Transition/output tableXX21SSSS30001101110/100/001/001/00120110/000/100/012S /0S /020S /0S /010/020S /ZQ *Q */Yn+1n21.6. Transition/output table for a sequential circuit is shown in Table 2, X is input a

5、nd Y is output, the sequentialcircuit is a modulus ( 3 ) up/down counter.第 1 页 共 9 页学院姓名学号任课老师考场教室_选课号/座位号密封线以内答题无效7. A serial sequence generator by feedback shift registers 74x194 is shown in Figure 1, assume the initial state isQ Q Q = 100, the feedback function LIN = Q Q + Q Q , the output sequen

6、ce in Q is ( 100110 循环输21021202出 ).Figure 18. When the input is 01100000 of an 8 bit DAC,the corresponding output voltage is The output voltage28 12 +225596range for the DAC is ( 0 9.99 或 3.76或 3.76)V. 【本题并未对误差范围进行要求，65一般可保留 2 位小数。由于考试时没有计算器，写出算式也可】得 分II. Please select the only one correct answer in

7、 the following questions.(2 X 5=10)1. The output signal of (A.binary decoderA)circuit is 1-out-of-M code.B.binary encoderdecade counterC. seven-segmentdecoderD.2. An asynchronous counter differs from a synchronous in (B).A.the number of states in its sequenceC. the type of flip-flop usedB.the method

8、 ofclockingthe value of the modulusD.3. There are (D) unused states for an n-bit Jonson counter.A. nB. 2nC. 2 -nD. 2 -2nnn4. The capacity of a memory that has 12 bits address bus and can store 8 bits at each address is (A.32768 B.8192 C.20 D.256A).5. Consider the following 44 “two-dimensional arbite

9、r” shown in Figure 2 with inputs R0,0,R0,1,R0,2,R0,3,R1,0,R1,1,R1,2,R1,3, R3,0,R3,1,R3,2,R3,3 (“requests”) and outputs G0,0,G0,1,G0,2,G0,3,G1,0,G1,1,G1,2,G1,3, G3,0,G3,1,G3,2,G3,3 (“grants”). Wi,0s and N0,j s are also inputs, and Ei,4s and第 2 页 共 9 页学院姓名学号任课老师考场教室_选课号/座位号密封线以内答题无效S4,j s are also out

10、puts. Assume1ns gate delay for all gates (i.e., 2-AND and INV). The longest delay in Fig. 2 (inns) is (B).A.19B.21C.23D.25Figure 2. 4 4 two-dimensional arbiter.Figure 3. Logic for rectangle box.【提示：不要被上图的气势所吓倒。从 Figure 3可知，每个小方盒的最大延迟是 3 个门，即 3ns；从 Figure 2 7 37 = 21ns 】得 分第 3 页 共 9 页学院姓名学号任课老师考场教室_选

11、课号/座位号密封线以内答题无效III. Analyze the clocked synchronous state machine shown in Figure 4.(1) Write out the excitation equations, the state transition equations and the output equations of the circuit. (4)(2) Fill out the transition/output table (6)(3) Assume initial state is 000, draw the state transitio

12、n /output diagram. Important: Only include reachablestates in the diagram (3)(15)(4) With initial state = 000, what states, if any, are not reacheable? Please list the unreachable states.(2)Q2IQ1F(2) The transition /output table:Q2*Q1*Q0* FI Q2Q1Q00 0000 0010 0100 0110 1000 1010 1100 1111 0001 0011

13、0101 0111 1001 1011 1101 111D Q0000 0111 0000 0111 0000 0111 0000 0111 1011 0000 0011 0000 0011 0000 0011 0000 1CPFigure 4参考答案：(1) The excitation equation :D0 = D1 = IQ0 + IQ0, D2 = IQ0The state equation :Q0* = Q1* = D0 = D1 = IQ0 + IQ0, Q2* = D2 = IQ0The output equation :F = Q2Q1Q0，第 4 页 共 9 页学院姓名学

14、号任课老师考场教室_选课号/座位号密封线以内答题无效(3) The sate transition /output diagram:(4) With initial state = 000, the unreachable states are: 001, 010, 100, 101, 110得 分Consider the following Mealy machine with initial state A. (“d” means dont care.)(15)I = 0 I = 1 I = 0 I = 1Assume the following state encoding:ABCDCA

15、DDDCCB011dd101State Q2Q1Q0A 000B 011C 100D 010(1) Please fill out the transition/output table .(8)参考答案：Transition/output tableI010, d100, 1100, 0011, 1FQ2*Q1*Q0*,(2) Fill-in K-Map of D2,D1,D0, and output F if realized with D flip-flops.(3)参考答案：第 5 页 共 9 页学院姓名学号任课老师考场教室_选课号/座位号密封线以内答题无效D2I Q2 0010Q Q

16、100d1011110ddddD001 11I 2 0010dQ Q100001ddd1110dd1(3) Derive the minimum two-level logic for D2,D1,D0 and F.(4)参考答案：D2 = IQ2Q1 + IQ2 + IQ0 或 D2 = (I+Q2+Q0) (I+Q2) (I+Q1)D1 = IQ2Q1 + IQ2 + Q1Q0 或 D1 = IQ2Q0 + IQ2 + Q1Q0 或 D1 = Q0(I+Q2)(I+Q2+Q1)D0 = IQ1Q0F = IQ2 + Q1 或 F = (Q2+Q1) (I+Q2) 或 F = (Q2+Q1)

17、 (I+Q1)得 分Consider the following sequential logic diagram in Figure 5. Assume the gate delay is 1 ns for2-AND and 2ns for 2-XOR. Assume the positive edge-trigged flip-flop delay is TdelayFF = 1 ns, and Assumethe positive edge-trigged flip-flop setup time is also TsetupFF = 1 ns.Fill out the rest of

18、the timing diagram for B, C, D, and Q.(15)第 6 页 共 9 页学院姓名学号任课老师考场教室_选课号/座位号密封线以内答题无效Figure 5参考答案：Figure 4得 分VI.74X163 is a synchronous 4-bit binary counter with synchronous load and synchronous clearinputs, the basic function table is shown as follow. Design a modulo-13 counter, using one 74X163 and somenecessary gates, with the following counting sequence: 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13