数字逻辑设计及应用教学课件：6-1组合逻辑设计实践

1、 class exersise F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )Use the duality, find a minimal product-of-sums expression(和之积) for the following logic function F. 1、先将F转为或与表达式， F= A,B,C,D （0，2，8，9，10，11，13）2、直接卡诺图圈零化简。 F=（B+D）（A+B） （A+C+D）F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )CDAB00 01 11 1000011

2、110000000011、先将F转为或与表达式， 得F= A,B,C,D （0，2，8，9，10，11，13）2、求F的对偶式。 FD=A,B,C,D ( 2, 4, 5, 6, 7, 13, 15 )3、 FD的最简与或式为： FD =BD+AB+ACD4、 FD的对偶式（FD）D =F。 F=（B+D）（A+B） （A+C+D）CDAB00 01 11 10000111101111111F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )21、先将F转为或与表达式， 得F= A,B,C,D （0，2，8，9，10，11，13）2、求F的反演式。 F=A,

3、B,C,D (0， 2, 8, 9, 10, 11, 13)3、 F的最简与或式为： F =BD+AB+ACD4、 F的反演式（F） =F。 F=（B+D）（A+B） （A+C+D）CDAB00 01 11 10000111101111111F = A,B,C,D ( 1, 3, 4, 5, 6, 7, 12, 14, 15 )3 C h a p t e r 6 Combinational Logic Design Practices 组合逻辑设计实践We will studay.6.1 6.96.10 Combinational Logic Design

4、6.1 Documentation Standards Documentation(文档)：(P343)1、ciruit specification：线路的详细说明。2、block diagram：方框图.系统的主要功 能模块及其基本互连的非正式图示说明。3、schematic diagram：原理图.4 . bill of materials(BOM)：材料清单。5、timing diagram：定时图(波形图)，输入、输出等波形的时间关系，包括其延时.Combinational Logic Design6. programmable logic device(PLD)： 可编程 逻辑器件。

5、 field-programmable gate array(FPGA)： 现场可编程门阵列。 application-specific integrated circuit(ASIC)： 专用集成电路。7、circuit description：电路描述.8. bus：总线. 在框图中总线用双线或黑线表示。 总线的位数用斜杠加数字说明或总线名加方括号(例inbus31.0，inbus31:0)。6.1.1 block diagram(方框图)：(P345) 显示系统的输入、输出、功能模块内部数据通路和重要控制信号. BUS :(总线) (P344)bus is a collection of

6、 two or more related signal lines. In a block diagram, buses are drawn with a double or heavy line.size denoted in the bus name INBUS31.0 or INBUS31:0). block diagramThe flow of control and data(控制流和数据流) in a block diagram should be clearly indicated. schematic diagram 原理图6.1.2 Gate Symbols 逻辑门的符号A

7、small circle, called an inversion bubble6.1.3 Signal Names and Active Levels (信号名与有效电平)(P347)Each signal name should have an active level (有效电平)associated with it.A signal is active high(高电平有效)if it performs the named action or denotes the named condition when it is HIGH or 1. A signal is active low

8、(低电平有效)if it performs the named action or denotes the named condition when it is LOW or 0. Asserted(有效) , deasserted or nagated(无效) .6.1.3 Signal Names and Active LevelsActive lowActive highREADY-READY+ERROR.LERROR.HADDR15(L)ADDR15(H)RESET*RESETENABLEENABLEGOGO/RECEIVERECEIVETRANSMIT_LTRANSMIT Disti

9、nguish (区别) (P348)signal namesexpressions equations READYREADY , READY-LREADY-L=READY 6.1.4 Active Levels for Pins 引脚的有效电平(P349)(a) AND gate (74X08) (b) NAND gate(74X00)(c) NOR gate (74X02) (d) OR gate (74X32) Active Levels for Pins6.1.5 Bubble-to-Bubble Logic Design “ 圈到圈”的逻辑设计 (P351)6.1.6 Drawing

10、Layout (布局图)A complete schematic page should be drawn with system inputs on the left and outputs on the right, and the general flow of signals should be from left to right. 手工画图计算机绘图6.1.6 Drawing Layout (布局图)1.A multipleschematic usually has a “flat” structure(平面结构).2. Much like programs, schematics

11、 can also be constructed hierarchically, the “top-level” schematic. 层次展开(自顶向下)6.1.9 Additional Schematic InformationIC types type (IC型号)reference designators (参考标志符)pin numbers (引脚). (P360-361)an open-drain or open-collector output. (漏极开路或集电极开路输出) hysteresis. (滞后)6.2 Circuit Timing (电路定时)“Timing is

12、everything”in investing, in comedy, and yes, in digital design. 6.2.1 Timing Diagrams(定时图)(P363)causality 6.2.2 Propagation Delaythe propagation delay of a signal path asthe time that it takes for a change at the input of the path to produce a change at the output of the path. from LOW to HIGH ( tpL

13、H) from HIGH to LOW (tpHL) 6.2.3 Timing Specifications 定时规格说明 Maximum. 最大延迟Typical 典型延迟Minimum 最小延迟worst-case delay 最坏情况延迟Tsetup 建立时间Thold 保持时间建立时间和保持时间建立时间：建立时间（Tsu：set up time）是指在时钟沿到来之前数据从不稳定到稳定所需的时间，如果建立的时间不满足要求那么数据将不能在这个时钟上升沿被稳定的打入触发器； 建立时间和保持时间保持时间：保持时间（Th：hold time）是指数据稳定后保持的时间，如果保持时间不满足要求那么数

14、据同样也不能被稳定的打入触发器。 NEXT CLASS 6.4 decoders6.5 encodersStandard MSI functions 中规模集成电路Decoder 译码器Encoder 编码器Multiplexer 多路复用器parity circuit 奇偶校验Comparator 比较器Adder subtractor 加法器减法器使能输入编码输出编码映射6.4 decoder 译码器6.4 decoder (P384) A decoder is a multiple-input(多输入), multiple-output (多输出)logic circuit that c

15、onverts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is a one-to-one mapping(一对一映射) from input code words into output code words. In a one-to-one mapping, each input code word produces a diffe

16、rent output code word. The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n different coded values . The most commonly used output code is a 1-out-of-m code, which contains m bits, where one bit is asserted at any time.使能输入编码输出编码映射6.4 Decoder（译码器）P3846.

17、4.1Binary Decoder (二进制译码器)n-to- 2n decoderThe most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code and a 1-out-of-2n output code. 6.4.1Binary Decoder (二进制译码器)n-to- 2n decoder2-to-4 decoderY0Y1Y2Y3I0I1EN使能输入编码输出编码映射n位二进制码2n中取1码 0 X X 0 0 0

18、 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary decoder6.4.1Binary Decoder (二进制译码器)n-to- 2n decoder2-to-4 decoderY0Y1Y2Y3I0I1ENYi = EN mi使能输入编码输出编码映射n位二进制码2n中取1码 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1

19、1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary decoder当输入使能端(EN)有效时Yi = miDont care notation(无关符号)使能输入编码输出编码映射n位二进制码2n中取1码 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for a 2-to-4 binary deco

20、derDesign it !Y3=EN.I1.I0Y2=EN.I1.I0Y1=EN.I1.I0Y0=EN.I1.I02-to-4 decoder logic diagram. Example 1 :Position encoding for a 3-bit mechanical encoding disk Example 2:What is the BCD decoders structrure?I3I2I1I0ENY0Y9THE IMPORTANCE OF 74-SERIES LOGIC (P342)well look at commonly used 74-series ICs that

21、perform well structured logic functions. These parts are important building blocks in a digital designers toolbox . Even when you design for PLDs, FPGAs, or ASICs, understanding 74-series MSI functions is important. In PLD-based design, standard MSI functions can be used as a starting point for deve

22、loping logic equations for more specialized functions. And in FPGA and ASIC design, the basic building blocks (or “standard cells” or “macros”) provided by the FPGA or ASIC manufacturer may actually be defined as 74-series MSI functions, even to the extent of having similar descriptive numbers.6.4.2 Logic Symbols for Larger-Scale Elements