数字集成电路英文课件：Chapter 2 MOS Transistors

1、Chapter 2: MOS TransistorsDigital Integrated CircuitsFaculty of Materials and Energy, GDUT2OutlineIntroductionStructure and Operation of the MOS TransistorThreshold voltage of the MOS transistorFirst-order Current-Voltage CharacteristicsDerivation of Velocity-Saturated Current EquationsSubthreshold

2、ConditionCapacitance of the MOS transistorDigital Integrated CircuitsFaculty of Materials and Energy, GDUT32.1 IntroductionAs the transistor scaling, MOS VLSI circuits make up a dominant percentage of the total market for digital ICs.Years-PMOS- NMOS- CMOSThe great advantage of CMOS digital circuits

3、 is that they maybe designed with low static power consumption in the steady stage condition, but it also increase in fabrication complexity and chip area compared to basic NMOS.The contents in this chapter: Structure and operation of the MOS transistorCalculation of threshold voltageCurrent equatio

4、nCapacitance of the MOS transistorDigital Integrated CircuitsFaculty of Materials and Energy, GDUT42.2 Structure and Operation of the MOS Transistor -1The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage controlled device. This means that a voltage at the gate control the curr

5、ent flows from the drain to the source. Four terminals: gate/G, drain/D, source/S, bulk/B (body or substrate)G: metal (early technology) or ploy-Si (heavily doped to keep its resistance low), controlled the formation of a conducting channelD/S: heavily doped to achieve Ohmic contact within metal ele

6、ctrode. The structure is symmetrical, one cannot distinguish between the source and drain of an unbiased device.B (NMOS): connected to the lowest potential, typically GND, to keep the BD/BS pn+ junction reverse-biased.Digital Integrated Circuits52.2 Structure and Operation of the MOS Transistor -2Tw

7、o Simple operation modes: On and Off.Determined by the gate voltageIn the off condition, no current flows in the deviceIn the on condition, electron current flows from source to drainA voltage is applied to the gate node to set up an electric field that creates a conductive channel between source an

8、d drain regions, and current flows when a potential difference exists between two nodes.Faculty of Materials and Energy, GDUTDigital Integrated CircuitsFaculty of Materials and Energy, GDUT62.2 Structure and Operation of the MOS Transistor -3Important device dimension parameters:Channel length/L: ty

9、pically in the range of 350nm and 22nm, this dimension will continue to scale according to Moores lawChannel width/W: typically much larger than the minimum length, depending on the desired current handling capabilityGate oxide thickness/Tox: typically less than 5nm, it determines the vertical elect

10、rical field and hence the device currents, but limited by the device reliability, e.g. breakdown voltageJunction depth/xj: 70-150nm, to calculate the junction capacitanceThickness of the depletion layer thickness/xd: to calculate the threshold voltageDigital Integrated CircuitsFaculty of Materials a

11、nd Energy, GDUT72.2 Structure and Operation of the MOS Transistor -4The silicon surface is comprised of active and field regions.Active region: device (or transistor). It should be defined in the layout design.Field region: it serves to isolate transistors. A thick layer of silicon dioxide over the

12、field regions is to minimize unwanted capacitance from interconnecting metal to the body and limit the current of parasitic transistors.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT2.3 Threshold voltage of the MOS transistor -1Definition of threshold voltage: VT is defined as the

13、applied gate voltage required to create the inversion layer charge. (The electron concentration at the surface is the same as the hole concentration in the bulk material)VT is defined as the applied gate voltage required to achieve the threshold inversion point. The threshold inversion point is defi

14、ned as the condition when the surface potential is s=2fp for p-type semiconductor and s=2fn for n-type semiconductor.8Digital Integrated CircuitsFaculty of Materials and Energy, GDUT92.3 Threshold voltage of the MOS transistor -2The three main terms of threshold voltage are:The difference in work fu

15、nctions between the gate material and the silicon substrate on the channel side.The positive charge Qox present in the oxide and the interface between the oxide and the bulk silicon. It contributes a negative quantity to the threshold voltage of Qox/Cox.The flat-band voltage: A voltage at the gate p

16、roduces flat energy bands in the MOS system.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT102.3 Threshold voltage of the MOS transistor -3The three main terms of threshold voltage are:A gate voltage (-2F-QB/Cox) is needed to change the surface potential to the strong inversion cond

17、ition and to offset the induced depletion-layer charge QB.The threshold voltage can be calculated by:Where:Digital Integrated CircuitsFaculty of Materials and Energy, GDUT112.3 Threshold voltage of the MOS transistor -4As Vb becomes more negative, more holes are attracted to the substrate connection

18、, leaving a larger negative charge behind. The threshold voltage is a function of the total charge in the depletion region because the gate charge must mirror QB before an inversion layer is formed. Thus, as VB drops and QB increase, VT also increases. This is the body effect or the back gate effect

19、.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT122.3 Threshold voltage of the MOS transistor -5For body effect to manifest itself, the bulk potential need not change; if the source voltage varies with respect to bulk potential, the same phenomenon occurs. Digital Integrated Circuit

20、sFaculty of Materials and Energy, GDUT132.3 Threshold voltage of the MOS transistor -6Problem: A 130nm technology employs carrier concentrations in the p-well in the range of 31017cm-3. Estimate the degree of band-bending required for strong inversion at room temperature, relative to the flat-band c

21、ondition.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT142.3 Threshold voltage of the MOS transistor -7Problem: A P-type well in a 130nm technology has NA= 31017cm-3. Find the limiting value of depletion-layer width and the total charge contained in the depletion region.Digital Int

22、egrated CircuitsFaculty of Materials and Energy, GDUT152.3 Threshold voltage of the MOS transistor -8Problem: Determine values of Cox and , if tox=2.2nm and NA= 31017cm-3. Digital Integrated CircuitsFaculty of Materials and Energy, GDUT162.3 Threshold voltage of the MOS transistor -9Problem: Calcula

23、te the zero-bias threshold voltage for an NMOS silicon-gate transistor that has well doping NA= 31017cm-3, gate doping ND= 1020cm-3, gate oxide thickness tox=2.2nm, and 21010cm-2 singly charged positive ions per unit area at the oxide silicon interface. Digital Integrated CircuitsFaculty of Material

24、s and Energy, GDUT172.3 Threshold voltage of the MOS transistor -10The breakdown voltage and junction capacitance maybe affected by the variation of doping concentration in the gate and oxide capacitance.The value of threshold voltage is determined by ion implanting dopant atoms into the channel reg

25、ion.A p-type threshold implant (boron) will make the threshold voltage more positive.A N-type threshold implant (phosphorus) will make the threshold voltage more negative.Problem: Calculation of threshold voltage implant dosage.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT182.4 Fi

26、rst-order Current-Voltage Characteristics-1Digital Integrated CircuitsFaculty of Materials and Energy, GDUT18Digital Integrated CircuitsFaculty of Materials and Energy, GDUT192.4 First-order Current-Voltage Characteristics-2The current flows through a semiconductor bar can be described as :Qn: charg

27、e density along the direction of currentV: velocity of the chargeDigital Integrated CircuitsFaculty of Materials and Energy, GDUT202.4 First-order Current-Voltage Characteristics-3The charge density can be calculated by:Cox: Capacitance of gate oxide per unit areaTox: thickness of gate oxideV(y): ch

28、annel potential at yDigital Integrated CircuitsFaculty of Materials and Energy, GDUT212.4 First-order Current-Voltage Characteristics-4If VdsVgs-VT, the device is operated in the triode region.Vgs-VT: overdrive voltage W/L: aspect ratioDigital Integrated CircuitsFaculty of Materials and Energy, GDUT

29、222.4 First-order Current-Voltage Characteristics-5If Vds2(Vgs-VT), thenThe MOSFET is operated as a resistor whose value is controlled by the overdrive voltage. With the condition VdsVgs-VT, Ids becomes relatively constant and we define the device is operated in the saturation region.Why?The density

30、 of inversion layer charge is proportional to Vgs-V(y)-VT. If channel potential V(y) approaches Vgs-VT, then Qn(y) drops to zero and the channel is pinch off. As Vds increase further, the point at which Qn equals to zero gradually moves toward the source.Digital Integrated CircuitsFaculty of Materia

31、ls and Energy, GDUT242.4 First-order Current-Voltage Characteristics-7The I-V equation of MOSFET in the saturation region can be derived as:In the long channel devices, the saturated MOSFET can be used as a current source connected between the drain and source. The current is controlled by the overd

32、rive voltage.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT25Design of Analog CMOS Integrated CircuitsDME, GDUT252.4 First-order Current-Voltage Characteristics-8As the device is operated in the saturation region, the actual length of the inverted channel gradually decreases as the

33、 potential difference between the gate and the drain increases. In other words, L is in fact as a function of Vds. This effect is defined as channel length modulation. Channel length modulation is more significant in the short channel devices and can be ignored in the long channel devices.Digital In

34、tegrated CircuitsFaculty of Materials and Energy, GDUT262.5 Velocity-Saturated Current Equations-1 In the long channel devices, saturation occurs when Vds=Vgs-VTIn the deep submicron devices, saturation occurs when the carriers reach velocity saturationthat is, when they reach the speed limit of the

35、 carriers in silicon.Velocity saturation is due to the high horizontal and vertical fields.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT272.5 Velocity-Saturated Current Equations-2The vertical field can be approximated as Ex=VGS-VT/tox.For high gate voltages, a large number of mob

36、ile carriers are induced in the inversion layer near the interface. The mobility of these carriers decreases due primarily to electron scattering caused by dangling bonds at the Si-SiO2 interface. The effect of the vertical field on mobility can be modeled as:The vertical field (5.5106V/cm) is very

37、large than the horizontal field (1.2105V/cm), and the effective mobility is reduced by a factor of 2 relative to the nominal mobility in the presence of low fields. (NMOS:540-270cm2/V-s)Digital Integrated CircuitsFaculty of Materials and Energy, GDUT282.5 Velocity-Saturated Current Equations-3The ho

38、rizontal field is given by Ey=VDS/LThe horizontal field acts to push the carriers to their velocity limit and this cause early saturation.The horizontal field acts to reduce the mobility. As Ey goes up, the carriers continue to increase in speed. Actually their velocity saturates a limit at approxim

39、ately vsat=107cm/s.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT292.5 Velocity-Saturated Current Equations-4initially, as Ey increase, the carrier velocity also increases, the mobility is keep constant.The field increase beyond a certain critical electrical field, EC, the carrier

40、velocity saturates at its limit in silicon. The horizontal fields are so high in DSM devices that they tend to saturate very quickly as VDS increases.The horizontal field is given by Ey=VDS/LThe horizontal field acts to push the carriers to their velocity limit and this cause early saturation.The ho

41、rizontal field acts to reduce the mobility. As Ey goes up, the carriers continue to increase in speed. Actually their velocity saturates a limit at approximately vsat=107cm/s.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT302.5 Velocity-Saturated Current Equations-5The saturation ve

42、locity for both electrons and holes is 8106cm/s at T=400K. The critical field values are:T=300K, vsat=107cm/sDigital Integrated CircuitsFaculty of Materials and Energy, GDUT312.5 Velocity-Saturated Current Equations-6The horizontal electric field, Ey, can be expressed as:Digital Integrated CircuitsF

43、aculty of Materials and Energy, GDUT322.5 Velocity-Saturated Current Equations-7Current equations for velocity-saturated devices (linear region):?Digital Integrated CircuitsFaculty of Materials and Energy, GDUT332.5 Velocity-Saturated Current Equations-8Current equations for velocity-saturated devic

44、es (saturation region):For long channel devices, ECLVGS-VT, For short channel devices, ECLVGS-VTDigital Integrated CircuitsFaculty of Materials and Energy, GDUT342.6 Subthreshold ConditionDigital Integrated CircuitsFaculty of Materials and Energy, GDUT352.7 Capacitance of the MOS transistor-1The swi

45、tching speed of MOS digital circuits is limited by the time required to charge and discharge the capacitances at internal node, which must be calculated from device dimensions and dielectric constants.Two nonlinear or voltage dependent capacitances:Thin oxide capacitances: Cgs, Cgd, CgbJunction capa

46、citances: Csb, CdbLinear and voltage independent capacitanceOverlap capacitance: ColDigital Integrated CircuitsFaculty of Materials and Energy, GDUT362.7 Capacitance of the MOS transistor-2The two plates of the thin oxide capacitance are defined as the gate and the channel. The dielectric material i

47、s the oxide sandwiched between these two plates. The total capacitance of the thin oxide is:Cox is the capacitance per unit area of the gate dielectric.Cg has remained constant for over 25 years. The reason is that both L and tox are scaled at the same rate.Digital Integrated CircuitsFaculty of Mate

48、rials and Energy, GDUT372.7 Capacitance of the MOS transistor-3When the device is cutoff, the channel is not existed between the drain and source. The gate-to-drain and gate-to-source capacitance is zero, that is, Cgs=Cgd=0. the gate-to-bulk capacitance is approximated to: Cgb=WLCox.In the linear re

49、gion, Cgs and Cgd are approximately equal to (1/2) Cg since the channel extends from source to drain.In the saturation region, the channel extends most of the way from source to drain, so most of the gate capacitance can be attributed to the source node, and a negligible amount to the drain node. Cg

50、s=(2/3) Cg and Cgd=0.Digital Integrated CircuitsFaculty of Materials and Energy, GDUT382.7 Capacitance of the MOS transistor-4Cg=Cgs+Cgd+CgbCg has a minimum value (2/3CoxWL) in the saturation region and maximum value (CoxWL) in the linear and cutoff region2.7 Capacitance of the MOS transistor-5The source and drain regions and the substrate from pn junctions that give rise to two additional capacitances: Csb and Cdb (n+p source/drain