外文翻译-基于单片机的水浴温度检测系统的软件设计

1、毕业设计论文中英文文献 题 目 S T C 8 9 C 5 2 芯 片 介 绍专 业 名 称 班 级 学 号 学 生 姓 名 指 导 教 师 20 年 3 月 9 日STC89C52芯片介绍译文特点：*与MCS-51产品指令和引脚完全兼容*8K字节可重擦写Flash闪速存储器*寿命：1000次擦写周期*全静态操作:0HZ-24MHZ*三级加密程序存储器*256*8字节内部RAM*32个可编程I/O口线*3个16位定时/计数器*8个中断源*可编程串行UART通道*低功耗空闲和掉电模式功能特性描述：STC89C52是一种低电压，高性能CMOS8位单片机，片内含8K BYTES的可反复擦写的只读程序

2、存储器(EPROM),器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准的80C51和80C52产品的指令系统和引脚兼容，芯片擦写允许程序存储器在系统内部或一个普通的非易失存储器的程序员所改写。片内置通用8位中央处理器CPU和FLASH存储单元，功能强大的STC89C52单片机适用于许多较为复杂控制应用场合。STC89C52提供以下标准功能：8K字节FLASH闪速存储器，256字节内部RAM，32个I/O口线，3个16位定时/计数器，一个6向两级中断结构，一个全双工串行通信口，片内振荡器及时时钟电路：同时，STC89C52可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。

3、空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。引脚功能说明*VCC：电源电压*GND：地*P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口P0写“1”时，可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址低8位和数据总线复用，在访问期间激活内部上拉电阻。在FLASH编程时，P0口接收指令字节，而在程序校检时，输出指令字节，校检时，要求外接上拉电阻。*P

4、1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动吸收或输出电流4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉倒高电平，此时可作输入口。作输入口使用，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流I。与STC89C51不同之处是，P1.0和P1.1还可分别作为定时/计数器2的外部计数输入(P1.0/T2)和输入(P1.1/T2EX),参见表1。FLASH编程和程序校检期间，P1接收8位地址.“1”，通过内部的上拉电阻把端口拉到高电平,此时可作输入口,作输入口使用时,因为内部存在上拉电阻。某个引脚被外部信号拉低时会输出一个电流(I)。在访问外

5、部程序存储器或16位地址的外部数据存储器(例如执行MOVX DPTR指令)时，P2口输出P2锁存器的内容。FLASH编程或校检时，P2亦接收高位地址和一些控制信号。*P3口: P3口是一组带有内部上拉电阻的8位双向I/O口，P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。此时，被外部拉低的P3口将用上拉电阻输出电流(I)。P3口除了作为一般的I/O口线外,更重要的用途是它的第二功能，如下列图所示:P3口还接收一些用于FLASH闪速存储器编程和程序校验的控制信号。*RST:复位输入.当振荡器工作时，RST引脚出现两个机器

6、周期以上高电平将使单片机复位。*ALE/PSEN: 注:表示反信号当外部程序存储器或数据存储器时,ALE(地址锁存允许)输出脉冲用于锁存。地址的底8位字节.一般情况下，ALE仍以时钟振荡频率的1/6输出固定的脉冲信号,因此它可对外输出时钟或用于定时目的，要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对FLASH存储器编程期间,该引脚还用于输入编程脉冲(PROG)。如有必要，可通过对特殊功能存放器(SFR)区中的8EH单元的D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令才能将ALE激活。此外，该引脚会被微弱抬高,单片机执行外部程序时，应设置ALE禁止位无效。

7、*PSEN：程序存储允许PSEN输出是外部程序存储器(地址为0000H-FFFFH)，EA端必须保持低电平(接地)。须注意的是：如果加密位LBI被编程,复位时内部会锁存EA端状态。如EA端为高电平(接VCC端)，CPU那么执行内部程序存储器中的指令。FLASH存储器编程时,该引脚加上+12V编程允许电源VPP，当然这必须是该器件是使用12V的编程电压VPP。*XTAL1：振荡器反相放大器的及内部时钟发生器的输入端。*XTAL2：振荡器反相放大器的输出端.。特殊功能存放器:表1 STC89C52 SFR 映像及复位状态。在STC89C52片内存储器中，80H-FFH共128单元为特殊功能存放器(

8、SFE)，SFR的地址空间映像如表2所示：并非所有的地址都被定义，从80H-FFH共128字节只有一局部被定义，还有一局部没有定义。对没有定义的单元读写将是无效的，读出的数据将部确定，而写入的数据也将丧失。不应将数据“1写入未定义的单元,由于这些单元在将来的产品中可能赋予新的功能,在这种情况下，复位后这些单元数值总是“0。STC89C52除了与STC89C51所有的定时/计数器0和定时/计数器1外，还增加了一个定时/计数器2。定时/计数器2的控制和状态位位于T2CON(参见表2)T2MOD(参见表3)，存放器对(RCA02H，RCAP2L)是定时器2在16位捕获方式或16位自动重装载方式下的捕

9、获/自动重装载存放器。表2 定时/计数器2控制存放器T2CON中断存放器STC89C52有6个中断源，2个中断优先级,IE存放器控制各中断位，IP存放器中6个中断源的每一个可定为2个优先级。数据存放器STC89C52有256个字节的内部RAM，80H-FFH高128个字节与特殊功能存放器(SFR)地址是重叠的，也就是高128字节的RAM和特殊功能的地址是相同的，但物理上它们是分开的。当一条指令访问7FH以上的内部地址单元时,指令中使用的寻址方式是不同的，也即寻址方式决定是访问高128字节RAM还是访问特殊功能存放器。如果指令是直接寻址方式那么为访问特殊功能存放器。例如，下面的直接寻址指令访问特

10、殊功能存放器0A0H(即P2口)地址单元。MOV 0A0H,#DATA间接寻址指令访问高128字节RAM，例如,下面的间接寻址指令中，R0的内容为0A0H，那么访问数据字节地址为0A0H,而不是P2口(0A0H)。MOV R0,#DATA堆栈操作也是间接寻址方式，所以高128位数据亦可作为堆栈区使用。定时器0和定时器1：STC89C52的定时器0和定时器1的工作方式与AT89C51相同。定时器2:定时器2是一个16位定时/计数器.它既可当定时器使用,也可作为外部事件计数器使用,其工作方式由特殊功能存放器T2CON(如表2)的C/T2位选择。定时器2有三种工作方式：捕获方式：自动重装载(向上或向

11、下计数)方式和波特率发生器方式，工作方式由T2CON的控制位来选择，参见表3。表3 定时器2工作方式定时器2由两个8位存放器TH2和TL2组成，在定时器工作方式中，每个机器周期TL2存放器的值加1，由于一个机器周期由12个振荡时钟构成，因此计数速率为振荡频率的1/12。在计数工作方式时,当T2引脚上外部输入信号产生由1至0的下降沿时，存放器的值加1。在这种工作方式下,每个机器周期的5SP2期间,对外部输入信号进行采样。假设在第一个机器周期中采到的值为1，而在下一个机器周期中采道德值为0，那么在紧跟着的下一个周期的S3P1期间存放器加1。由于识别1至0的跳变需要2个机器周期(24个振荡周期)，因

12、此最高计数速率为振荡频率的1/24。为确保采样的正确性，要求输入的电平在变化前至少保持一个完整周期的时间，以保证输入信号至少被采样一次。The introduction of STC89C52Features Compatible with MCS-51 Products 8K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x

13、8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down ModesDescriptionThe STC89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only

14、 memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memo

15、ry programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel STC89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.The STC89C52 provides the following standard features: 8K bytes of Flas

16、h, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the STC89C52 is designed with static logic for operation down to zero frequency and supports two software se

17、lectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin Desc

18、riptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address

19、/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit

20、 bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) b

21、ecause of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes duringFlash programmi

22、ng and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externa

23、lly being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pu

24、ll-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8

25、-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current

26、 (IIL) because of the pull ups. Port 3 also serves the functions of various special features of the STC89C52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillat

27、or is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the osci

28、llator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MO

29、VC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the STC89C52 is executing code from external program memory, PSEN is a

30、ctivated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note,

31、however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal programexecutions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.XTAL1Input to the invertin

32、g oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Table 1. STC89C52 SFR Map and Reset ValuesSpecial Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note

33、 that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since th

34、ey may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCA

35、P2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Data MemoryThe STC89C52 implements 2

36、56 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the

37、 address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data In

38、structions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accessesthe data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are availableas stack space.Timer 0 and 1Timer 0 and Timer 1 in the STC89C52 operate the same way as Timer 0 and Timer 1 in the STC89C52.Timer 2Timer 2 is a 16