第九章同步状态机.

1、2022-4-1812022-4-1822022-4-1832022-4-1842022-4-1852022-4-186StateNext_Statein/outin/out2022-4-1872022-4-1882022-4-189GF2022-4-1810GF2022-4-18112022-4-18122022-4-1813Idle Start Stop Clear A/G=0 !A A/F=1 !Reset /F=0 G=0!Reset /F=0 G=0 !Reset | !A/F=0 G=1 状态转移图!Reset /F=0 G=02022-4-18142022-4-18152022-

2、4-18162022-4-1817例12022-4-18182022-4-18192022-4-1820例22022-4-18212022-4-18222022-4-1823module fsm (Clock, Reset, A, F, G);input Clock, Reset, A;output F,G;reg 1:0 state, Nextstate;parameter Idle = 2b00, Start = 2b01, Stop = 2b10, Clear = 2b11;always (posedge Clock) begin if (!Reset) begin state = Id

3、le; end else state = Nextstate; end2022-4-1824always ( state or A ) begin F=0; G=0; if (state = Idle) begin if (A) Nextstate = Start; else begin Nextstate = Idle; G=1; end end else if (state = Start) if (!A) Nextstate = Stop; else Nextstate = Start;else if (state = Stop) if (A) Nextstate = Clear; el

4、se Nextstate = Stop; else if (state = Clear) begin if (!A) Nextstate = Idle; else Nextstate = Clear; F=1; end else Nextstate= Idle; endendmodule 黄色是我加的，怀疑老师写错了例32022-4-18252022-4-18262022-4-1827assign G=state3;assign F=state0;parameter /- G_ i_ j_ F-/ Zero=4b0_0_0_0, Idle=4b0_0_0_0, start=4b0_0_0_0,

5、 stop=4b0_0_0_0, clear=4b0_0_0_0,例42022-4-18282022-4-18292022-4-18302022-4-18312022-4-18322022-4-18332022-4-18342022-4-18352022-4-18362022-4-18372022-4-18382022-4-18392022-4-18402022-4-18412022-4-18422022-4-18432022-4-18442022-4-18452022-4-1846always (posedge clk) begin if(reset) begin /*置输出为置输出为0*/ end else if(set) begin