VHDL与数字系统课程设计简单处理器设计

1、施立工於孝隈FujianUniversityofTechnology课程设计报告实践课题：VHDL与数字系统课程设计学生:XXX指导老师:XXX、XXX系别:电子信息与电气工程系专业:电子科学与技术班级:XXX学号:XXX一、设计任务用VHDL设计一个简单的处理器，并完成相关的仿真测试。、设计要求：图1就是一个处理器的原理图，它包含了一定数量的寄存器、一个复用器、一个加法/减法器（Addsub）,一个计数器与一个控制单元数据传输实现过程：16位数据从DIN输入到系统中，可以通过复用器分配给R0R7与A,复用器也允许数据从一个寄存器传通过Bus送到另外一个寄存器。加法与减法的实现过程：复用器先将

2、一个数据通过总线放到寄存器A中，然后将另一个数据放到总线上，加法/减法器对这两个数据进行运算，运算结果存入寄存器G中,G中的数据又可根据要求通过复用器转存到其她寄存器中。卜表就是该处理所支持的指令。操作功能mv Rx, Rymvi Rx, #Dadd Rx, Rysub Rx, RyRxRyRxDataRx-Rx+RyRxRx-Ry1) RxRy:将寄存器Ry中的内容复制到Rx;2) MviRx,#D:将立即数存入寄存器Rx中去。所有指令都按9位编码(取自DIN的高9位)存储在指令存储器IR中,编编码规则为IIIXXXYYY,III表示指令,XXX表示Rx寄存器,YYY表示Ry寄存器。立即数#

3、D就是在mvi指令存储到IR中之后通过16位DIN输入的。有一些指令，如加法指令与减法指令，需要在总线上多次传输数据，因此需要多个时钟周期才能完成。控制单元使用了一个两位计数器来区分这些指令执行的每一个阶段。当Run信号置位时，处理器开始执行DIN输入指令。当指令执行结束后，Done信号置位，下表列出四个指令在执行过程中每一个时间段置位的控制信号。寸问指令T0T1T2T3(mv):IoIRinRYout,RXin,Done(mvi):11IRinDINout,RXin,Done(add):l2IRinRXout,AinRYout,Gin,AddsubGout,RXin,Done(sub):l3

4、IRinRXout,AinRYout,Gin,AddsubGout,RXin,Done、实现功能说明2、1mvRx,Ry实现的功能：将寄存器Rx的值赋给寄存器Ry(以mvR0,R5为例)(1 )计数器为“。丽指令寄存器的置位控制信号输入端 的控制信号如图3加粗黑线所示。IRin=1有效，将DIN输入的数据的高 9位锁存。置位RunReset图3(2)计数器为“1”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制彳t号让R5的值输出到总线上，然后控制单元控制寄存器R0将总线上的值锁存，完成整个寄存器对寄存器的赋值过程。置位的控制信号与数据流如图4加粗黑

5、线所示。2、2mviRx,#D实现的功能：将的立即数#D赋给寄存器Rx(以mvR0,#D为例)计数器为“0的，指令寄存器的置位控制信号输入端IRin=1有效，将DIN输入的数据的高9位锁存。置位的控制信号如图5加粗黑线所示。R0 | | R1-| R2 | | R3 | | R4 | R5 | R6 R7 | 仄Bus' Control UnitResetDone(2)计数器为“1”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制彳t号让DIN的值输出到总线上，然后控制单元控制寄存器R0将总线上的值锁存，完成整个立即数对寄存器的赋值过程。置位

6、的控制信号与数据流如图6加粗黑线所示。2、3addRx,Ry与subRx,Ry实现的功能：将寄存器Ry的值加上/减去寄存器Rx的值并赋给寄存器Rx(以add/subR0,R1为例)。(1)计数器为“0的，指令寄存器的置位控制信号输入端IRin=1有效，将DIN输入的数据的高9位锁存。置位的控制信号如图7加粗黑线所示。(2)计数器为“1”时,首先控制单元根据设计器为“00”时输入的指令，向复用器发出选通控制信号，复用器根据该控制彳t号让R0的值输出到总线上，然后控制单元控制寄存器A将总线上的值锁存。置位的控制信号与数据流如图8加粗黑线所示。(3)计数器为10”时,首先控制单元根据设计器为“00”

7、时输入的指令，向复用器发出选通控制信号，复用器根据该控制彳t号让R1的值输出到总线上，然后控制单元控制加法/减法器addsub将寄存器A的值与总线上的值相加/相减并输出，接着寄存器G将加法/减法器addsub的计算结果锁存。置位的控制信号与数据流如图9加粗黑线所示。Dir JR7R2RO R1* AddSub/BusF?unControl UnitDoneG的值输出与数据流如图10加粗黑线所示。图10置位的控制信号(4)计数器为11 ”时,首先控制单元向复用器发出选通控制信号，复用器根据该控制信号让寄存器到总线上，寄存器R0将总线上的值进行锁存，完成整个寄存器与对寄存器见加减法的运算过程。三、

8、单元模块设计说明4、1寄存器Registe寄存器R0R7、寄存器A或寄存器G:用于数据的存储。当时钟输入clk的上升沿到来且rin=1时,将数据输入端rxin15、0的数据锁存到寄存器中并从数据输出端rxout15、0输出；当rin=0时,输出端保持原来的值不变。registeclkrxout15.0rinrxin15.0inst1寄存器Registe的VHDlK码：LIBRARYIEEE;USEIEEE、STD_LOGIC_1164、ALL;ENTITYregisteisport(clk:instd_logic;rin:instd_logic;rxin:instd_logic_vector(

9、15downto0);rxout:outstd_logic_vector(15downto0);endentityregiste;architectureoneofregisteisbeginprocess(clk)beginifclk'eventandclk='1'thenifrin='1'thenrxout<=rxin;endif;endif;endprocess;endone;4、2指令寄存器IR指令寄存器IR用于对输入的16为指令进行处理，取其高9位。当时钟输入clk的上升沿到来且rin=1时，取数据输入端rxin15、0的高9位将其锁存到

10、寄存器中并从数据输出端rxout8、0输出；当rin=0时，输出端保持原来的值不变。IRclkrxout8.01rinrxin15.0inst4指令寄存器IR的VHDL代码：LIBRARYIEEE;USEIEEE、STD_LOGIC_1164、ALL;ENTITYIRisport(clk:instd_logic;rin:instd_logic;rxin:instd_logic_vector(15downto0);rxout:outstd_logic_vector(8downto0);endentityIR;architectureoneofIRisbeginprocess(clk)begini

11、fclk'eventandclk='1'thenifrin='1'thenrxout<=rxin(15downto7);endif;endif;endprocess;endone;4、3力口/减法器addsub0,当控制端Addsub=1时，两个0输出；当控制端Addsub=0时,0输出。力口/减法器addsub用于处理两个输入的数据datain215、0与datain115、数据输入端datain215、0与datain115、0相加并从数据输出端dataout15、数据输入端datain215、0减去datain115、0,结果从数据输出端da

12、taout15、addsubain15.0about15.01bin15.0adsubaddsub力口/减法器addsub的VHDL代码：LIBRARYIEEE;USEIEEE、STD_LOGIC_1164、ALL;useieesstd_logic_unsigned、all;ENTITYaddsubisport(ain:instd_logic_vector(15downto0);bin:instd_logic_vector(15downto0);adsub:inbit;about:outstd_logic_vector(15downto0);endentityaddsub;architectu

13、reoneofaddsubissignala,b:std_logic_vector(15downto0);beginprocess(adsub,ain,bin)beginifadsub='0'thenabout<=ain+bin;elsifadsub='1'thenabout<=ain-bin;endif;endprocess;endone;4、4计数器counterclear=0 时(清零端 clear>10>11>00 不断计数器counter用于产生控制单元的输入脉冲，对控制单元的工作时序进行控制。无效），时钟输入clk每来一

14、个上升沿，输出count1、0加1,所以输出为00>01循环;当clear=1时（清零端clear有效），对输出Q1、0同步清零，与时钟有关。counterclkcount1.0clearcounter计数器counter的VHDL代码：libraryieee;useieesstd_logic_1164、all;useieesstd_logic_unsigned、all;entitycounterisport(clk:instd_logic;clear:instd_logic;count:outstd_logic_vector(1downto0);endcounter;architect

15、ureoneofcounterissignalc:std_logic_vector(1downto0);beginprocess(clk,clear)beginifclk'eventandclk='1'thenif(clear='1')thenc<="00"elsec<=c+1;endif;endif;endprocess;count<=c;endone;4、5复用器multiplexers复用器根据控制单元的控制信号将指定的输入数据输出到总线上。来自控制单元的控制信号为R0outR7out、Gout、DINout,

16、输入数据位来自寄存器R0R7、寄存器A、数据输入端DIN,当控制信号的某一位为1时，将其对应的输入数据输出到总线上。multiplexers.din15.0dout15.0gin15.0r015.0r115.0r215.0'r315.0r415.0r515.0r615.0'r715.0ren7.0gendineninst3复用器multiplexers的VHDl代码:libraryieee;useieesstd_logic_1164、all;entitymultiplexersisport(din:instd_logic_vector(15downto0);gin:instd_

17、logic_vector(15downto0);r0:instd_logic_vector(15downto0);r1:instd_logic_vector(15downto0);r2:instd_logic_vector(15downto0);r3:instd_logic_vector(15downto0);r4:instd_logic_vector(15downto0);r5:instd_logic_vector(15downto0);r6:instd_logic_vector(15downto0);r7:instd_logic_vector(15downto0);ren:inbit_ve

18、ctor(7downto0);gen:inbit;dinen:inbit;dout:outstd_logic_vector(15downto0);endmultiplexers;architecturebhvofmultiplexersisbegindout<=ginwhengen='1'elser0whenren(0)='1'elser1whenren(1)='1'elser2whenren(2)='1'elser3whenren(3)='1'elser4whenren(4)='1'else

19、r5whenren(5)='1'elser6whenren(6)='1'elser7whenren(7)='1'elsedinwhendinen='1'else"00000"endbhv;4、6控制单元control，完成指定的操作。控制单元根据计数器发出的脉冲与DIN输入的操作指令对整个系统的其她模块进行控制instdoneginaddsubainr7inr6inr5inr4inr3inr2inr1inr0inrout7.0dinoutirin8.0goutclk1.0iroutrunclearresetco

20、ntrol控制单元control的VHDL代码:libraryieee;useieee.std_logic_1164、all;useieee.std_logic_unsigned、all;entitycontrolisport(reset:instd_logic;run:instd_logic;clk:instd_logic_vector(1downto0);irin:instd_logic_vector(8downto0);clear:outstd_logic;irout:outstd_logic;gout:outstd_logic;dinout:outstd_logic;rout:outs

21、td_logic_vector(7downto0);r0in:outstd_logic;r1in:outstd_logic;r2in:outstd_logic;r3in:outstd_logic;r4in:outstd_logic;r5in:outstd_logic;r6in:outstd_logic;r7in:outstd_logic;ain:outstd_logic;addsub:outstd_logic;gin:outstd_logic;done:outstd_logic);endcontrol;architectureoneofcontrolisbeginprocess(clk,run

22、,reset,irin)beginif(reset='0')thenclear<='1'irout<='0'gout<='0'dinout<='0'rout<="00000000"r0in<='0'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in&

23、lt;='0'ain<='0'addsub<='0'gin<='0'done<='0'elsecaseclkiswhen"00"=>clear<='0'gout<='0'dinout<='1'rout<="00000000"rOin<='O'r1in<='0'r2in<='0'r3in<='0&#

24、39;r4in<='0'r5in<='0'r6in<='0'r7in<='0'ain<='0'addsub<='0'gin<='0'done<='0'ifrun='O'thenirout<='1'elseirout<='0'endif;when"01"=>if(irin(8downto6)="000")thencle

25、ar<='r；irout<='0'gout<='0'dinout<='0'ain<='0'addsub<='0'gin<='0'done<='1'caseirin(5downto3)iswhen"000"=>r0in<='r；r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5i

26、n<='0'r6in<='0'r7in<='0'when"001"=>r1in<='r；r0in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"010"=>r2in<='r；r0in<='0'r1i

27、n<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"011"=>r3in<='1'rOin<='O'r1in<='0'r2in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'

28、;when"100"=>r4in<='r；r0in<='0'r1in<='0'r2in<='0'r3in<='0'r5in<='0'r6in<='0'r7in<='0'when"101"=>r5in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0

29、'r4in<='0'r6in<='0'r7in<='0'when"110"=>r6in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r7in<='0'when"111"=>r7in<='1'rOin<

30、;='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'whenothers=>null;endcase;caseirin(2downto0)iswhen"000"=>rout<="00000001"when"001"=>rout<="00000010"when"010

31、"=>rout<="00000100"when"011"=>rout<="00001000"when"100"=>rout<="00010000"when"101"=>rout<="00100000"when"110"=>rout<="01000000"when"111"=>rout<="10000000&

32、quot;whenothers=>null;endcase;elsif(irin(8downto6)="001")thenclear<='1'irout<='0'gout<='0'dinout<='1'rout<="00000000"ain<='0'addsub<='0'gin<='0'done<='1'caseirin(5downto3)iswhen"000

33、"=>r0in<='r；r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"00r->r1in<='r；r0in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'

34、;r6in<='0'r7in<='0'when"010"=>r2in<='r；r0in<='0'r1in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"011"=>r3in<='1'rOin<='O'r1in<='0

35、'r2in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"100"=>r4in<='r；r0in<='0'r1in<='0'r2in<='0'r3in<='0'r5in<='0'r6in<='0'r7in<='0'when"101&q

36、uot;=>r5in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r6in<='0'r7in<='0'when"110"=>r6in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<

37、;='0'r5in<='0'r7in<='0'when"111"=>r7in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'whenothers=>null;endcase;elsif(irin(8downto6)="010"

38、;oririn(8downto6)="011")thenclear<='0'irout<='0'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'ain<='1'addsub<='0'gin<='0'

39、done<='0'caseirin(5downto3)iswhen"000"=>rout<="00000001"when"001"=>rout<="00000010"when"010"=>rout<="00000100"when"011"=>rout<="00001000"when"100"=>rout<="00010000&

40、quot;when"101"=>rout<="00100000"when"110"=>rout<="01000000"when"111"=>rout<="10000000"whenothers=>null;endcase;elseclear<='1'irout<='0'gout<='0'dinout<='0'rout<="00000

41、000"rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'ain<='0'addsub<='0'gin<='0'done<='0'endif;when"10"=>if(irin(8downto6)="010")thenclear<='0'iro

42、ut<='0'gout<='0'dinout<='0'rOin<='O'r1in<='O'r2in<='0'r3in<='0'r4in<='O'r5in<='0'r6in<='0'r7in<='0'ain<='0'addsub<='0'gin<='1'done<='0'

43、caseirin(2downto0)iswhen"000"=>rout<="00000001"when"001"=>rout<="00000010"when"010"=>rout<="00000100"when"011"=>rout<="00001000"when"100"=>rout<="00010000"when"101&q

44、uot;=>rout<="00100000"when"110"=>rout<="01000000"when"111"=>rout<="10000000"whenothers=>null;endcase;elsif(irin(8downto6)="011")thengout<='0'dinout<='0'rOin<='O'r1in<='0'r2in&

45、lt;='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'ain<='0'addsub<='1'gin<='1'done<='0'caseirin(2downto0)iswhen"000"=>rout<="00000001"when"001"=>rout<

46、="00000010"when"010"=>rout<="00000100"when"011"=>rout<="00001000"when"100"=>rout<="00010000"when"101"=>rout<="00100000"when"110"=>rout<="01000000"when"111&

47、quot;=>rout<="10000000"whenothers=>null;endcase;elseclear<='1'irout<='0'gout<='0'dinout<='0'rout<="00000000"rOin<='O'r1in<='0'n<='0'；r3in<='0'r6in<='0'r7in<='0

48、9;ain<='0'addsub<='0'gin<='0'done<='0'endif;when"11"=>if(irin(8downto6)="010"oririn(8downto6)="011")thenclear<='0'irout<='0'gout<='1'dinout<='0'rout<="00000000"ain<

49、;='0'addsub<='0'gin<='0'done<='1'caseirin(5downto3)iswhen"000"=>r0in<='r；r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"00r->r1in<

50、='r；r0in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"010"=>r2in<='r；r0in<='0'r1in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<=

51、9;0'r7in<='0'when"011"=>r3in<='1'rOin<='O'r1in<='0'r2in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'when"100"=>r4in<='r；r0in<='0'r1in<='0'r2in<

52、='0'r3in<='0'r5in<='0'r6in<='0'r7in<='0'when"101"=>r5in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r6in<='0'r7in<='0'when"110"=>

53、r6in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r7in<='0'when"111"=>r7in<='1'rOin<='O'r1in<='0'r2in<='0'r3in<='0'r4in<='0&

54、#39;r5in<='0'r6in<='0'whenothers=>null;endcase;elseclear<='0'irout<='0'gout<='0'dinout<='0'r2in<='0'r3in<='0'r4in<='0'r5in<='0'r6in<='0'r7in<='0'ain<='0'a

55、ddsub<='0'gin<='0'done<='0'endif;whenothers=>null;endcase;endif;endprocess;endone;4、7数码管显示led采集寄存器R0R7的值作为led的输入，将各寄存器值的低四位以19、AF分别显示在8个数码管，从而观察各寄存器值的变化。ledout6、0为数码管段码输出端，control2、0为第几个数码管有效的数码管选择端输出。ledclkledout6.0reg_015.0control2.0'reg_115.0reg_215.01reg_3

56、15.0reg_415.01reg_515.01reg_615.0reg_715.0inst2数码管显示led的VHDL代码:libraryieee;useieee.std_logic_1164、all;useieee.std_logic_unsigned、all;entityledisport(clk:instd_logic;reg_0:instd_logic_vector(15downto0);reg_1:instd_logic_vector(15downto0);reg_2:instd_logic_vector(15downto0);reg_3:instd_logic_vector(15

57、downto0);reg_4:instd_logic_vector(15downto0);reg_5:instd_logic_vector(15downto0);reg_6:instd_logic_vector(15downto0);reg_7:instd_logic_vector(15downto0);ledout:outstd_logic_vector(6downto0);control:outstd_logic_vector(2downto0);endled;architectureoneofledissignalcontrols:std_logic_vector(2downto0);s

58、ignalled0,led1,led2,led3,led4,led5,led6,led7,outer:std_logic_vector(3downto0);beginled0<=reg_0(3downto0);led1<=reg_1(3downto0);led2<=reg_2(3downto0);led3<=reg_3(3downto0);led4<=reg_4(3downto0);led5<=reg_5(3downto0);led6<=reg_6(3downto0);led7<=reg_7(3downto0);process(clk)begin

59、ifclk'eventandclk='1'thenifcontrols="111"thencontrols<="000"elsecontrols<=controls+1;endif;endif;control<=controls;endprocess;process(controls)begincasecontrolsiswhen"000"=>outer<=led0;when"001"=>outer<=led1;when"010"

60、=>outer<=led2;when"011"=>outer<=led3;when"100"=>outer<=led4;when"101"=>outer<=led5;when"110"=>outer<=led6;when"111"=>outer<=led7;whenothers=>outer<="XXXX"endcase;caseouteriswhen"0000"=>

61、ledout<="0111111"when"0001"=>ledout<="0000110"when"0010"=>ledout<="1011011"when"0011"=>ledout<="1001111"when"0100"=>ledout<="1100110"when"0101"=>ledout<="1101101&

62、quot;when"0110"=>ledout<="1111101"when"0111"=>ledout<="0000111"when"1000"=>ledout<="1111111"when"1001"=>ledout<="1101111"when"1010"=>ledout<="1110111"when"1011"

63、=>ledout<="1111100"when"1100"=>ledout<="0111001"when"1101"=>ledout<="1011110"when"1110"=>ledout<="1111001"when"1111"=>ledout<="1110001"whenothers=>ledout<="XXXXXXX"

64、endcase;endprocess;endone;四、处理器各个模块的连接采用原理图连接的方法进行各个模块间的连接，连接后的原理图见附录1。五、操作说明及功能、时序仿真效果5、1功能仿真将R0<-6,R0-R1,R0%MaeHhwBar-25O.nEn$，卜|叱值印;178IEnsIM3T72.56mSt就OpaEnd5uFUntnClsekRoQIDOkmeLdn.LR|/工口国.tsi-foujLta-1e国rcgL3<eA.1-ztFr>sgL=t«,ij-rxwi_n-TTTTTTTTTTTTTTTTTJ-LJ-Ll,TTTl-rTJ-LnLliJCLOi

65、n=8U.ns.1ZO.0L5D.UnsZDO.OZ4D.0nsZBOJDil=320.0n.;S&DlOasESO71G力r-i"iir1i址(i加X砒X而X血1cto【卬inm?mir"ram5nnjmyYTinnmg"Y"irnnnnfTTT'Bi"'injnr"yirriLMJUO-UUUE工UJJUt口WJQiX口口PCXUUObLH-LbiUUtdULbLLU6KEU额即海回徽,：匍的,米MKJ,*!；一二二POOP51口2Sr«gt=t»RJ|rjr<mt311g国fii

66、glEtsuRSIraciut“匕方QsttECIncout廿电R4IrsculBKlrvml16fT国1E却小REIrsflul0%国的匚与5国rflgict«ROIrxnTLtiIIICOD二3DOdC):口首8ziiacrid);n.“D"OB?!?LhncAJL._|jrn-nt、一qgr.orajfQOU.!.L.LUJ:_LJU.LiJLbAUlJ.，5、2时序仿真i）、按设计说明书的仿真图中的数据进行设置，仿真结果如下2)、将R3<-1,R5<-6,R5R3R2,R5+R3R5、仿真结果如下Dgt知口必4CDmiOOiiEaDD»加。陡血

67、m140Dit周口M1800ic期1口出2900曲11z2BD0at2BD0uHD0330On340One3&00m工IIIIIUIIIIIIIII-Ih.'iujeon 'dd用”aCli也Lni nr3 MlH :a E1bd.目 ：Djiater ciarJ3喜口式门辰二3 值3 t幅出B0 U atirU El _+ L3:抽三t£ E375S山7JC一旅 1 n r1nrnr"r"B'T)rfir 4/切 c 7飞不CO丽ULLJIJLiCOOCam ko5lu：7570MULInnin)C11i】：1 J1：； ：,】：

68、"口 ，11:二：r1：y if no Qi5、3操作说明Clock接的就是数字时钟 1KHz,DIN15、0管脚分配到开关 K1K12、按键S5S8,Resetn管脚分配到按键S1,Run管脚分配到S2,R0R7的低四位值分别显示在led1led8数码管中。将Run改为低电平有效(因为按键按下为低电平，如此更好操作)。Busout15、0高12位管脚分配到二极管1) 、mvi R0,#D (D=5)L1L12。先将DIN置为“ 0010 0000 0000 FFFF ”(只与高六位有关)即K3向上拨(为高电平 电平),按键都不按，再按一下 S2(Run)键，此时指令已被读到，再将要置的数置入，5= "0000 0000 0000 0101 按下SS S7两键，再按一下S2(Run)键，即可瞧到了 led1(R0)显