阻塞和非阻塞赋值

1、CompanyLogo200647122006473200647module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always (posedge clk or posedge rst) if (rst) y1 = 0; / reset else y1 = y2; always (posedge clk or posedge rst) if (rst) y2 = 1; / preset else y2 = y1; endmodule42006475200647module fbosc2 (y1

2、, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always (posedge clk or posedge rst) if (rst) y1 = 0; / reset else y1 = y2; always (posedge clk or posedge rst) if (rst) y2 = 1; / preset else y2 = y1; endmodule62006477200647q1 q2q3dclk移位寄存器电路8200647module pipeb1 (q3, d, clk); output 7:0 q3

3、; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) begin q1 = d; q2 = q1; q3 = q2; end endmodulemodule pipeb2 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) begin q3 = q2; q2 = q1; q1 = d; end endmodule综合结果9200647q3dclk实际综合的结果10200647mod

4、ule pipeb3 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) q1 = d; always (posedge clk) q2 = q1; always (posedge clk) q3 = q2; endmodule module pipeb4 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) q2 = q1;

5、always (posedge clk) q3 = q2; always (posedge clk) q1 = d; endmodulenot goodnot good11200647module pipen1 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) begin q1 = d; q2 = q1; q3 = q2; end endmodule module pipen2 (q3, d, clk); output 7:0 q3; input 7:0 d

6、; input clk; reg 7:0 q3, q2, q1; always (posedge clk) begin q3 = q2; q2 = q1; q1 = d; end endmodule12200647module pipen3 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) q1 = d; always (posedge clk) q2 = q1; always (posedge clk) q3 = q2; endmodulemodule p

7、ipen4 (q3, d, clk); output 7:0 q3; input 7:0 d; input clk; reg 7:0 q3, q2, q1; always (posedge clk) q2 = q1; always (posedge clk) q3 = q2; always (posedge clk) q1 = d; endmodule1320064714200647module dffb (q, d, clk, rst); output q; input d, clk, rst; reg q; always (posedge clk) if (rst) q = 1b0; el

8、se q = d;endmodulemodule dffx (q, d, clk, rst); output q; input d, clk, rst; reg q; always (posedge clk) if (rst) q = 1b0; else q = d; endmodule15200647q3Sn1q1Sq2Spre_nclkq3QDQDQD16200647 module lfsrb1 (q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; wire n1; assign n1 = q1 q3; always

9、(posedge clk or negedge pre_n) if (!pre_n) begin q3 = 1b1; q2 = 1b1; q1 = 1b1; end else begin q3 = q2; q2 = n1; q1 = q3; end endmodulemodule lfsrb2 (q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; always (posedge clk or negedge pre_n) if (!pre_n) q3,q2,q1 = 3b111; else q3,q2,q1 = q2,(q

10、1q3),q3; endmodule17200647 module lfsrb1 (q3, clk, pre_n); output q3; input clk, pre_n; reg q3, q2, q1; wire n1; assign n1 = q1 q3; always (posedge clk or negedge pre_n) if (!pre_n) begin q3 = 1b1; q2 = 1b1; q1 = 1b1; end else begin q3 = q2; q2 = n1; q1 = q3; end endmodulemodule lfsrb2 (q3, clk, pre

11、_n); output q3; input clk, pre_n; reg q3, q2, q1; always (posedge clk or negedge pre_n) if (!pre_n) q3,q2,q1 = 3b111; else q3,q2,q1 = q2,(q1q3),q3; endmodule182006471920064720200647 module ao4 (y, a, b, c, d); output y; input a, b, c, d; reg y, tmp1, tmp2; always (a or b or c or d) begin tmp1 = a &a

12、mp; b; tmp2 = c & d; y = tmp1 | tmp2; endendmodule(a or b or c or d or tmp1 or tmp2)21200647 module ao4 (y, a, b, c, d); output y; input a, b, c, d; reg y, tmp1, tmp2; always (a or b or c or d) begin tmp1 = a & b; tmp2 = c & d; y = tmp1 | tmp2; endendmodule2220064723200647 module nbex2 (

13、q, a, b, clk, rst_n); output q; input clk, rst_n; input a, b; reg q; always (posedge clk or negedge rst_n) if (!rst_n) q = 1b0; / 时序逻辑时序逻辑 else q = a b;/ 异或，为组合逻辑异或，为组合逻辑 endmodule在一个在一个always块中同时实现组合逻辑和时序逻辑块中同时实现组合逻辑和时序逻辑 24200647 module nbex1 (q, a, b, clk, rst_n); output q; input clk, rst_n; inpu

14、t a, b; reg q, y; always (a or b) y = a b; always (posedge clk or negedge rst_n) if (!rst_n) q = 1b0; else q = y; endmodule将组合和时序逻辑分别写在两个将组合和时序逻辑分别写在两个always块中块中 252006472620064727200647 module ba_nba2 (q, a, b, clk, rst_n); output q; input a, b, rst_n; input clk; reg q; always (posedge clk or neged

15、ge rst_n) begin: ff reg tmp; if (!rst_n) q = 1b0; else begin tmp = a & b; q = tmp; end end endmodule28200647 module ba_nba6 (q, a, b, clk, rst_n); output q; input a, b, rst_n; input clk; reg q, tmp; always (posedge clk or negedge rst_n) if (!rst_n) q = 1b0; / 对对 q进行阻塞赋值进行阻塞赋值 else begin tmp = a & b; q = tmp; / 对对 q进行非阻塞赋值进行非阻塞赋值 end endmodule292006473020064731200647 initial begin a = 0; a = 1; end 32200647 module badco