FPGA交通灯实验报告参考模板

1、交通灯实验报告1 / 17一， 实验目的实现两路信号灯交替亮起，并利用两组数码管分别对两路信号进行倒计时。两路信号时间分别为：V:绿灯（30S） H:红灯（35S） 黄灯（5s） 绿灯（30S） 红灯（35S） 黄灯（5S）二， 实验步骤建立工程可在欢迎界面点击“Creat a New Project”进入工程建立界面，亦可关闭欢迎界面，点击菜单栏的“File”，点击“New Project Wizard”进入建立工程界面。右侧为建立工程界面，点击next。在此界面选定工程路径，取好工程名，点击“Next”。注意：路径中不能有中文，工程名也不能有中文。一直点击“Next”进入器件设置界面，DE

2、2-70开发工具采用的Cyclone II系列的EP2C70F896C6N。点击“Finish”，完成工程建立1、 点击“File”，点击“New” 选择“Verilog HDL”2， 点击主界面工具栏中的 选择“Verilog HDL” 3、写入verilog代码。代码如下：module traffic(Clk_50M,Rst,LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V,Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL,led15);parameter S1=2'b00;parameter S2=2'b01;paramet

3、er S3=2'b10;parameter S4=2'b11;input Clk_50M,Rst;output LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V;output6:0 Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL;output led15;/-div for 1Hz-start-reg Clk_1Hz;reg 31:0 Cnt_1Hz;always(posedge Clk_50M or negedge Rst)begin if(!Rst) begin Cnt_1Hz<=1; Clk_1Hz<=1; e

4、nd else begin if(Cnt_1Hz>=25000000) begin Cnt_1Hz<=1; Clk_1Hz<=Clk_1Hz; end else Cnt_1Hz<=Cnt_1Hz + 1; endend/-div for 1Hz-end-reg7:0 Cnt30,CntH,CntV,CntHH,CntVV;reg7:0CntDis,CntDiss;/-30 counter and seg7-start-reg LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V;always(posedge Clk_1Hz)begin ca

5、se(state) S1: begin if(Cnt30>=30) Cnt30<=1; else Cnt30<=Cnt30 + 1; endS2: begin if(Cnt30>=5) Cnt30<=1; else Cnt30<=Cnt30 + 1; endS3: begin if(Cnt30>=30) Cnt30<=1; else Cnt30<=Cnt30 + 1; endS4: begin if(Cnt30>=5) Cnt30<=1; else Cnt30<=Cnt30 + 1; end endcaseendalway

6、s(posedge Clk_1Hz)begin case(stateV) S1: begin if(CntV>=30) CntV<=1; else CntV<=CntV + 1; end S2: begin if(CntV>=5) CntV<=1; else CntV<=CntV + 1; end S3: begin if(CntV>=35) CntV<=1; else CntV<=CntV + 1; end endcaseendalways(posedge Clk_1Hz)begin case(stateH) S1: begin if(C

7、ntH>=35) CntH<=1; else CntH<=CntH + 1; end S2: begin if(CntH>=30) CntH<=1; else CntH<=CntH + 1; end S3: begin if(CntH>=5) CntH<=1; else CntH<=CntH + 1; end endcaseend always(negedge Clk_50M or negedge Rst) begin case(state) S1: CntVV=30-CntV; S2: CntVV=5-CntV; S3: CntVV=35

8、-CntV; S4: CntVV=35-CntV; endcaseend always(negedge Clk_50M or negedge Rst) begin case(state) S1: CntHH=35-CntH; S2: CntHH=35-CntH; S3: CntHH=30-CntH; S4: CntHH=5-CntH; endcaseend /16进制计数器转换为用于显示的10进制计数器always(posedge Clk_50M)begin if(CntVV>29)begin CntDis7:4<=3; CntDis3:0<=CntVV - 30;endel

9、se if(CntVV>19)begin CntDis7:4<=2; CntDis3:0<=CntVV - 20;endelse if(CntVV>9)begin CntDis7:4<=1; CntDis3:0<=CntVV - 10;endelse CntDis<=CntVV;endSEG7_LUT hex4(Seg7_VL,CntDis3:0);SEG7_LUT hex5(Seg7_VH,CntDis7:4);always(posedge Clk_50M)begin if(CntHH>29)begin CntDiss7:4<=3; Cn

10、tDiss3:0<=CntHH - 30;endelse if(CntHH>19)begin CntDiss7:4<=2; CntDiss3:0<=CntHH - 20;endelse if(CntHH>9)begin CntDiss7:4<=1; CntDiss3:0<=CntHH - 10;endelse CntDiss<=CntHH;endSEG7_LUT hex1(Seg7_HL,CntDiss3:0);SEG7_LUT hex2(Seg7_HH,CntDiss7:4); /-30 counter and seg7-end-reg 1:0

11、state,stateH,stateV;always(posedge Clk_1Hz)begin case(state) S1: if(Cnt30>=30) begin state<=S2; endS2: if(Cnt30>=5) begin state<=S3; endS3: if(Cnt30>=30) begin state<=S4; endS4: if(Cnt30>=5) begin state<=S1; enddefault: begin state<=S1; endendcaseendalways(posedge Clk_1Hz)

12、begin case(state) S1: begin stateH<=S1; stateV<=S1; endS2: begin stateH<=S1; stateV<=S2; endS3: begin stateH<=S2; stateV<=S3; endS4: begin stateH<=S3; stateV<=S3; endendcaseendalways(posedge Clk_50M or negedge Rst)begin if(!Rst) begin LedR_H<=0; LedG_H<=0;LedY_H<=0;

13、LedR_V<=0; LedG_V<=0;LedY_V<=0;endelse begin case(state) S1: begin LedR_H<=1; LedG_H<=0; LedY_H<=0; LedR_V<=0; LedG_V<=1; LedY_V<=0; end S2: begin LedR_H<=1; LedG_H<=0; LedY_H<=0; LedR_V<=0; LedG_V<=0; LedY_V<=1; end S3: begin LedR_H<=0; LedG_H<=1;

14、LedY_H<=0; LedR_V<=1; LedG_V<=0; LedY_V<=0; end S4: begin LedR_H<=0; LedG_H<=0; LedY_H<=1; LedR_V<=1; LedG_V<=0; LedY_V<=0; end default: begin LedR_H<=0; LedG_H<=0; LedY_H<=0; LedR_V<=0; LedG_V<=0; LedY_V<=0; end endcase endendassign led15=state;endmod

15、ule module SEG7_LUT(oSEG,iDIG);input3:0iDIG;output6:0oSEG;reg6:0oSEG;always (iDIG)begincase(iDIG)4'h1: oSEG = 7'b1111001;/ -t-4'h2: oSEG = 7'b0100100; / | |4'h3: oSEG = 7'b0110000; / lt rt 4'h4: oSEG = 7'b0011001; / | |4'h5: oSEG = 7'b0010010; / -m-4'h6: o

16、SEG = 7'b0000010; / | |4'h7: oSEG = 7'b1111000; / lb rb4'h8: oSEG = 7'b0000000; / | |4'h9: oSEG = 7'b0011000; / -b-4'ha: oSEG = 7'b0001000;4'hb: oSEG = 7'b0000011;4'hc: oSEG = 7'b1000110;4'hd: oSEG = 7'b0100001;4'he: oSEG = 7'b00001

17、10;4'hf: oSEG = 7'b0001110;4'h0: oSEG = 7'b1000000;endcaseendendmodule编译工程保存文件，将文件放在所建工程所在路径下点击主界面工具栏中的图标也可点击菜单栏中“Processing”，点击“Start Compilation”分配关键如下：Clk_50MInputPIN_AD15LedG_HOutputPIN_AD9LedG_VOutputPIN_AJ6LedR_HOutputPIN_AJ7)LedR_VOutputPIN_AJ5)LedY_HOutputPIN_AD8LedY_VOutputP

18、IN_AK5RstInputPIN_AA23Seg7_HH6OutputPIN_G1Seg7_HH5OutputPIN_H3Seg7_HH4OutputPIN_H2Seg7_HH3OutputPIN_H1Seg7_HH2OutputPIN_J2Seg7_HH1OutputPIN_J1Seg7_HH0OutputPIN_K3Seg7_HL6OutputPIN_E4Seg7_HL5OutputPIN_F4Seg7_HL4OutputPIN_G4Seg7_HL3OutputPIN_H8Seg7_HL2OutputPIN_H7Seg7_HL1OutputPIN_H4Seg7_HL0OutputPIN_H6Seg7_VH6OutputPIN_AD17Seg7_VH5OutputPIN_AF177Seg7_VH4OutputPIN_AE177Seg7_VH3OutputPIN_AG16Seg7_VH2OutputPIN_AF167Seg7_VH1OutputPIN_AE167Seg7_VH0OutputPIN_AG13Seg7_VL6OutputPIN_AD12Seg7_VL5OutputPIN_AD11Seg7_VL4OutputPIN_AF108Seg7_VL3OutputPIN_AD10S